WO2007131127A3 - Merging queued memory operation in a non-volatile memory - Google Patents

Merging queued memory operation in a non-volatile memory Download PDF

Info

Publication number
WO2007131127A3
WO2007131127A3 PCT/US2007/068172 US2007068172W WO2007131127A3 WO 2007131127 A3 WO2007131127 A3 WO 2007131127A3 US 2007068172 W US2007068172 W US 2007068172W WO 2007131127 A3 WO2007131127 A3 WO 2007131127A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory operation
queued
merging
operations
Prior art date
Application number
PCT/US2007/068172
Other languages
French (fr)
Other versions
WO2007131127A2 (en
WO2007131127A8 (en
Inventor
Yan Li
Original Assignee
Sandisk Corp
Yan Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/381,996 external-priority patent/US7463521B2/en
Priority claimed from US11/382,000 external-priority patent/US7486558B2/en
Application filed by Sandisk Corp, Yan Li filed Critical Sandisk Corp
Publication of WO2007131127A2 publication Critical patent/WO2007131127A2/en
Publication of WO2007131127A3 publication Critical patent/WO2007131127A3/en
Publication of WO2007131127A8 publication Critical patent/WO2007131127A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices

Abstract

Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.
PCT/US2007/068172 2006-05-05 2007-05-03 Merging queued memory operation in a non-volatile memory WO2007131127A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/382,000 2006-05-05
US11/381,996 US7463521B2 (en) 2005-04-01 2006-05-05 Method for non-volatile memory with managed execution of cached data
US11/382,000 US7486558B2 (en) 2005-04-01 2006-05-05 Non-volatile memory with managed execution of cached data
US11/381,996 2006-05-05

Publications (3)

Publication Number Publication Date
WO2007131127A2 WO2007131127A2 (en) 2007-11-15
WO2007131127A3 true WO2007131127A3 (en) 2008-04-03
WO2007131127A8 WO2007131127A8 (en) 2008-06-05

Family

ID=39471909

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068172 WO2007131127A2 (en) 2006-05-05 2007-05-03 Merging queued memory operation in a non-volatile memory

Country Status (1)

Country Link
WO (1) WO2007131127A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7499320B2 (en) 2007-03-07 2009-03-03 Sandisk Corporation Non-volatile memory with cache page copy
WO2008109411A1 (en) * 2007-03-07 2008-09-12 Sandisk Corporation Non-volatile memory and method for cache page copy
US7502255B2 (en) 2007-03-07 2009-03-10 Sandisk Corporation Method for cache page copy in a non-volatile memory
US10942843B2 (en) * 2017-04-25 2021-03-09 Micron Technology, Inc. Storing data elements of different lengths in respective adjacent rows or columns according to memory shapes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356485B1 (en) * 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
US20060126390A1 (en) * 2004-12-14 2006-06-15 Gorobets Sergey A Pipelined programming of non-volatile memories using early data

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356485B1 (en) * 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
US20060126390A1 (en) * 2004-12-14 2006-06-15 Gorobets Sergey A Pipelined programming of non-volatile memories using early data

Also Published As

Publication number Publication date
WO2007131127A2 (en) 2007-11-15
WO2007131127A8 (en) 2008-06-05

Similar Documents

Publication Publication Date Title
WO2006109289A3 (en) Smartcard power management
WO2013165786A3 (en) Power management for a system having non-volatile memory
WO2010141059A3 (en) Methods for controlling host memory access with memory devices and systems
WO2010080142A3 (en) Modifying commands
WO2007028036A3 (en) Photovoltaic cells integrated with bypass diode
WO2011056319A3 (en) Fan array control system
WO2006078531A3 (en) Scheduling of housekeeping operations in flash memory systems
WO2008092778A3 (en) Controlling instruction execution in a processing environment
WO2012177698A3 (en) Drift management in a phase change memory and switch (pcms) memory device
WO2012125200A3 (en) Dynamic core selection for heterogeneous multi-core systems
IL195380A0 (en) Glycolic acid production by fermentation from renewable resources
WO2011011452A3 (en) Component power monitoring and workload optimization
WO2009088451A3 (en) Forced idle of a data processing system
WO2008005145A3 (en) Controlling memory parameters
TW200951723A (en) Systems and methods for scheduling a memory command for execution based on a history of previously executed memory commands
WO2008063647A3 (en) Delaying an operation that reduces a lifetime of memory
WO2007028158A3 (en) Energy and chemical species utility management system
WO2008087779A1 (en) Array type processor and data processing system
WO2007072436A3 (en) Schedule based cache/memory power minimization technique
WO2006138522A3 (en) Interrupt-responsive non-volatile memory system and method
WO2005008504A8 (en) An executing automatically method using semiconductor storage devices
WO2007131127A8 (en) Merging queued memory operation in a non-volatile memory
WO2009003038A3 (en) Phased garbage collection and house keeping operations in a flash memory system
WO2012148987A3 (en) Cross-profile coordination of energy consumption policies
WO2010066816A3 (en) Method for managing data from analysis appliances

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07811866

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07811866

Country of ref document: EP

Kind code of ref document: A2