WO2007129773A1 - Iii族窒化物化合物半導体積層構造体 - Google Patents
Iii族窒化物化合物半導体積層構造体 Download PDFInfo
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Definitions
- the present invention relates to a light-emitting diode (L E D), a laser diode (L D), an electronic device, and the like that have good crystallinity used in the manufacture of I I I groups.
- I I Group I nitride compound semiconductor shall be represented by A 1 Ga I n N
- the present invention relates to a group I I I nitride compound semiconductor stacked structure that can be suitably used for epitaxially growing a group I II nitride compound semiconductor crystal having good crystallinity on a sapphire substrate, and a method for manufacturing the same.
- Group III nitride compound semiconductors have a direct transition type band gap with an energy equivalent to the visible to ultraviolet light region, and can emit light with high efficiency, so they have been commercialized as LEDs and LDs. .
- the electronic device has the potential to obtain characteristics that cannot be obtained with conventional I I I 1-V compound semiconductors.
- I I I 1-V compound semiconductors are not yet commercially available, and I I I 1-V compound semiconductors are generally grown by growing crystals on single crystal wafers of different materials. With such a different substrate
- the low temperature buffer layer made of aluminum nitride (A 1 N) or A 1 G a N is disclosed in In general, a method of first depositing a layer called “3” on a substrate and epitaxially growing a group III nitride compound semiconductor crystal thereon at a high temperature has been generally performed.
- the MO C VD method is used for film formation, as in the above-described conventional technology.
- the MO C VD method is suitable for forming a high-quality crystal film at a high growth rate, but in order to form a film having a structure like a columnar crystal with good uniformity, a plasma such as sputtering is used.
- the film-forming method using a metalized metal material is more suitable.
- these documents do not describe the density of columnar crystals.
- the sapphire, silicon, silicon carbide, zinc oxide, gallium phosphide, and arsenic are disclosed in Japanese Patent Nos. 3 4 0 8 7 3 and 3 7 0 4 9 2.
- Examples include gallium, magnesium oxide, manganese oxide, and group III nitride compound semiconductor single crystals.
- the sapphire a-plane substrate is described as the most suitable. Disclosure of the invention
- An object of the present invention is to stably obtain a group III nitride compound semiconductor layer having good crystallinity by using a buffer layer whose structure is controlled when forming a group III nitride compound semiconductor layer. is there.
- Another object of the present invention is to provide an efficient method for manufacturing a buffer layer having a controlled structure.
- the present invention provides the following inventions.
- a first layer made of a group III nitride compound semiconductor and a second layer made of a group III nitride compound semiconductor in contact with the first layer are provided on a substrate, and the first layer Contains columnar crystals with clear crystal interfaces
- the group III nitride compound semiconductor forming the first layer and the group III nitride compound semiconductor forming the second layer are different materials. Any one of the above (1) to (10) The group III nitride compound semiconductor multilayer structure described. . (1 2) The group III nitride compound semiconductor multilayer structure according to the above (1 1), wherein the first layer is A 1 N and the second layer is GaN.
- Substrate is made of sapphire, SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium oxide
- the above (consisting of a material selected from the group consisting of gallium, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium tantalum aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten and molybdenum ( The group III nitride compound semiconductor multilayer structure according to any one of 1) to (12).
- a first layer made of a columnar crystal of a group III nitride compound semiconductor was formed on a substrate by activating and reacting a group III metal raw material and a gas containing nitrogen element with plasma. Then, a method for producing a group III nitride compound semiconductor multilayer structure, comprising forming a second layer made of a group III nitride compound semiconductor in contact with the first layer.
- An III group nitride compound semiconductor light emitting device comprising the III group nitride compound semiconductor multilayer structure according to any one of the above (1) to (13).
- a lamp comprising the group III nitride compound semiconductor light-emitting device according to (2 6) above. Since the group III nitride compound semiconductor multilayer structure of the present invention has a surface layer made of a group III nitride compound semiconductor having good crystallinity, a group III nitride compound semiconductor such as an LED manufactured using the same is manufactured. The device has good characteristics. Further, in the method for producing a Group III nitride compound semiconductor multilayer structure of the present invention, the first layer is formed by a method of activating the raw material with plasma, so that a crystal film with good uniformity can be obtained in a short time. Can improve productivity. Brief Description of Drawings
- FIG. 1 is a schematic view showing a cross section of an epitaxy 18 having an epitaxy layer structure for a semiconductor light emitting device manufactured in Example 2 of the present invention.
- FIG. 2 is a plan view showing the electrode structure of the semiconductor light emitting device fabricated in Example 2 of the present invention.
- FIG. 3 is a planar TEM photograph of the first layer of the I II I nitride compound semiconductor multilayer structure produced in Example 1 of the present invention.
- FIG. 4 is a diagram schematically showing FIG.
- FIG. 5 is a cross-sectional TEM photograph of the I II I nitride compound semiconductor multilayer structure produced in Example 1 of the present invention.
- FIG. 6 is a diagram schematically showing FIG.
- FIG. 7 is a planar T EM photograph of the first layer of the I II Group nitride compound semiconductor multilayer structure produced in the comparative example of the present invention.
- Fig. 8 is a schematic diagram of Fig. 7. BEST MODE FOR CARRYING OUT THE INVENTION
- the group III nitride compound semiconductor multilayer structure of the present invention is used when epitaxially growing a group III nitride compound semiconductor crystal on a substrate.
- a layer containing columnar crystals with a clear crystal interface is used as the first layer on the substrate.
- the clear interface of the columnar crystal serves as a seed crystal for the generation of the second layer formed immediately above it, and can generate the seed crystal at an appropriate density.
- dislocations are looped and reduced, and a good crystalline layer can be formed with low dislocations.
- a step is generated at the interface of the columnar crystal, which becomes an active point, and it is considered that a seed crystal is generated, and a minute gap is generated at the interface portion, which becomes an active point and a seed crystal is generated.
- the details of the mechanism by which the seed crystal is generated cannot be specified.
- the columnar crystal having a clear crystal interface in the present invention is a crystal grain having a clear crystal interface having a cross-sectional shape based on a hexagon when viewed from a plane direction. The entire layer may be filled with this crystal grain, or it may be scattered in a layer that does not have a clear crystal interface.
- Figure 3 shows the Group III nitride compound prepared in Example 1 of the present invention.
- FIG. 6 is a TEM photograph of the first layer of the semiconductor multilayer structure viewed from the plane direction.
- Fig. 4 is a schematic diagram of Fig. 3. It can be seen that crystal grains surrounded by a clear crystal interface having a cross-sectional shape based on a hexagon are scattered in a crystal layer having no clear interface.
- the size is about 5 nm to 10 nm in diameter, and the density is about 500 mm in a square surrounded by 1 / im. (The photo shows the range of 85 nm x 120 nm, in which 47 crystal grains with clear crystal interfaces are seen.)
- a suitable density of columnar crystals with a clear crystal interface is about 100 to 100 in a square surrounded by 1 m. If the density is higher than this, many crystal interfaces are included. This is equivalent to low crystallinity. As a result, the crystallinity of the second layer is not improved. Even at a density lower than this, the crystal interface of the second layer is not improved due to too few crystal interfaces. More preferably, it is 1 5 0 0 to 5 0 0 0 0, and particularly preferably 2 0 0 0 to 1 0 0 0 0 0.
- FIG. 7 is a TEM photograph of the first layer of the group III nitride compound semiconductor multilayer structure fabricated in Comparative Example 1 of the present invention as seen from the plane direction, and FIG. 8 schematically shows FIG. FIG.
- FIG. 7 shows in the TEM image shown in Fig. 7, when an A 1 N crystal layer that only contains columnar crystals with about 500 distinct interfaces in 1 m 2 is used as the first layer, A favorable crystalline first layer cannot be obtained. In severe cases, the second layer does not become Mira's surface and becomes cloudy.
- the crystallinity of the n-type layer, light-emitting layer, and p-type layer stacked on the LED is also poor, current leakage occurs, and ESD resistance And inferior aging characteristics.
- whether or not the columnar crystal included in the first layer is a columnar crystal having a clear interface can be determined from a planar TEM photograph.
- the density can also be measured from planar TEM photographs.
- a columnar crystal is a crystal that has a columnar shape as a longitudinal cross-sectional shape, but whether or not it is columnar can be determined from a cross-sectional TEM photograph.
- Fig. 5 is a TEM photograph of the cross section of the group III nitride compound semiconductor multilayer structure fabricated in Example 1 of the present invention at almost the same position as Fig. 3, and
- Fig. 6 is a diagram schematically showing Fig. 5. is there. The first layer is delimited by the interface as shown by the solid line in Fig. 6, and the individual crystal masses between the interfaces are in the shape of hexagonal columns.
- a crystal layer containing many columnar crystals with a clear crystal interface means an aggregate of crystals with a well-aligned crystal lattice plane with respect to the substrate surface.
- the crystals can be continuously connected to each other, thus forming an aggregate in which the crystal interface is not clear.
- the half-width is small. This is equivalent to an aggregate containing many. Therefore, it is desirable that the half width of the X-ray rocking curve measurement of the (0 0 0 2) plane of the first layer is 0.5 ° or less. More preferably, it is 0.1 degrees or less.
- the width of each columnar crystal is a value between 0.1 nm and 100 nm. A value between i n m and 70 n m is more desirable.
- the size of the columnar crystal is preferably within a certain range so that the density of the crystal interface falls within an appropriate range. For example, it is desirable that the width of each columnar crystal is a value between 1 nm and 50 nm. A value between 2 nm and 30 nm is more desirable, and a value between 3 nm and 20 nm is particularly desirable.
- each columnar crystal can be easily measured by the above planar TEM photograph. That is, in FIG. 4, the diameter of each columnar crystal is the width of each columnar crystal.
- the width of the columnar crystal A is a
- the width of the columnar crystal B is b.
- the width of each columnar crystal cannot be precisely defined, and has a certain distribution. Therefore, even if there are about several percent of crystals in which the width of each columnar crystal is out of the above range, the effect of the present invention is not affected. 90% or more within the above range It is preferable to enter.
- the layer thickness of the first layer is preferably 10 nm to 500 nm. If it is thinner than this, the function as a buffer layer cannot be fulfilled sufficiently, and even if it is thicker than this, the function does not change, so that the processing time is simply extended. More desirably, the layer thickness is 20 nm to 10 mm.
- the thickness of the first layer can also be easily measured by the cross-sectional TEM photograph.
- the first layer (buffer layer) made of such columnar crystals covers the substrate without any gap. If the first layer does not cover the substrate and the surface of the substrate is partially exposed, the second layer formed on the first layer and the second layer formed directly on the substrate Because the lattice constants of the crystals differ between layers, uniform crystals cannot be obtained. : Rice field
- the first layer needs to cover at least 60% of the substrate surface. More desirably, it is 80% or more, and most desirably covers 90% or more.
- the proportion of the first layer covering the substrate can be measured from the cross-sectional TEM photo.
- the first layer is formed by scanning the interface between the substrate and the layer in parallel with the substrate surface using EDS or the like. It is also possible to estimate the ratio of areas that are not present.
- by preparing a sample on which only the first layer has been formed it is possible to measure the exposed area of the substrate using a technique such as AFM. In the present invention, the measurement was performed from the cross-sectional T EM photograph.
- any material can be used as long as it is a group III nitride compound semiconductor represented by the general formula A 1 Ga In N.
- As and V may be included as group V.
- a composition containing A 1 is desirable.
- G a A 1 N is desirable, and the composition of A 1 is preferably 50% or more.
- a 1 N is more preferable because it can efficiently form a columnar crystal aggregate.
- a method for forming the first layer a method generally known as a crystal growth method for a group I I I nitride compound semiconductor can be used without any problem.
- Commonly used crystal growth methods include the MOCVD method, the MBE method, the sputtering method, and the HVPE method.
- a method of forming a film by activating and reacting a group I II metal raw material and a gas containing nitrogen element with plasma is preferable because a columnar crystal with a clear crystal interface can be easily formed.
- I I I Group I metal materials are converted into plasma by sputtering, PLD, PED and CVD.
- Plasma can be generated by a sputtering method in which a high voltage is applied at a specific vacuum to generate a discharge, a PLD method that is generated by irradiating a high energy density laser, or a PED method that is generated by irradiating an electron beam.
- the sputtering method is the simplest method, and is easy to produce columnar crystals with an appropriate density and a clear crystal interface, and is suitable for mass production.
- the DC sputtering method may cause the target surface to be charged up and the deposition rate is likely to be unstable. Therefore, it is desirable to use pulse DC or the RF sputtering method.
- the substrate temperature during film formation is preferably in the range of 300 to 80 ° C. Below that temperature, the first layer may not cover the entire surface of the substrate, and the substrate surface may be exposed. Above this temperature, the migration of the metal raw material becomes active and it is difficult to form columnar crystals with a clear crystal interface, which is not suitable as the first layer. More desirably, the temperature is from 400 to 80 ° C.
- the important parameters are the pressure inside the furnace and the partial pressure of nitrogen, except for the substrate temperature. It is desirable that the pressure in the furnace is 0.3 Pa or more. At pressures below this, the amount of nitrogen present is small, and sputtered metal adheres without becoming nitrides.
- the upper limit of the pressure is not particularly defined, but it is needless to say that the pressure is low enough to generate plasma.
- the ratio of nitrogen flow rate to nitrogen and argon flow rate is preferably 20% to 90%. If the flow ratio is less than this, the sputter metal will adhere as metal, and if the flow ratio is higher than this, the amount of argon will be small and the spatter speed will decrease. Particularly desirable is 25% or more and 70% or less.
- a first layer containing columnar crystals with a clear crystal interface at a desired density can be formed.
- the film formation rate be from 0.0 1 nm to 10 nm / sec. At higher speeds, the film becomes amorphous rather than crystalline. At a deposition rate below this, the film grows in an island shape without forming a layer and cannot cover the surface of the substrate.
- a target metal is a mixture of metal materials from the beginning (not necessarily an alloy). There is a way to do this, or you can prepare two targets made of different materials At the same time, you can take a way to splatter.
- a target of a mixed material is used to form a film having a fixed composition, and a plurality of evening targets are installed in a chamber to form several kinds of films having different compositions.
- the nitrogen raw material used in the present technology generally known compounds can be used without any problem.
- ammonia and nitrogen are preferable because they are easily available and relatively inexpensive.
- Ammonia has good decomposition efficiency and can be deposited at a high growth rate.
- ammonia is highly reactive and toxic, requires a detoxification facility and a gas detector, and uses materials for the components used in the reaction equipment. It needs to be devised, for example, it needs to be chemically stable.
- nitrogen is used as a raw material, the apparatus is simple, but a high reaction rate cannot be obtained.
- the method of decomposing nitrogen by an electric field or heat and then introducing it into the apparatus is inferior to ammonia, but can provide a film forming speed that can be used, and is the most suitable considering the balance with the apparatus cost. Nitrogen source.
- the material making up the second layer need not be the same as the first layer. According to the results of experiments conducted by the present inventors, it was desirable to use II-I group nitrides containing Ga as the material for the second layer. It is necessary to loop dislocations by migration so that the crystallinity of the first layer, which is an aggregate of columnar crystals with a clear crystal interface, is not inherited, but what is a material that tends to cause dislocation looping? , Nitride containing Ga. In particular, A 1 G a N was desirable, and G a N was also suitable.
- the second layer can have a structure doped with a dopant as required, or a structure without doping.
- a structure in which electrodes are attached to both sides of the chip by doping the second layer so that current flows in the layer structure in the vertical direction.
- a chip structure in which electrodes are formed on the same surface of the chip is adopted. Therefore, the crystallinity is better if the layer immediately above the substrate is an undoped crystal.
- the method of laminating the second layer is not particularly limited. There is no problem as long as the crystal growth technique can cause the above-described dislocation looping.
- the MO C VD method, the MBE method, and the VPE method are generally suitable for forming such a film because they can produce such a fine film. Above all, the MO C VD method is
- the second layer can be formed using a sputtering method.
- a device can be made more easily than the M0 C V D method or the MB E method.
- Annealing is not particularly required after the first layer is deposited and before the first layer is deposited.
- the second film formation is performed by a gas phase chemical film formation method such as M 0 C VD, MB E, and VPE
- a temperature rising process without film formation and a temperature stabilization process are performed.
- Group V source gas is often circulated, and as a result, the effect of annealing may be produced.
- this does not particularly use the effect of annealing, but is a generally known technique.
- the carrier gas that circulates at that time can be used without any problem.
- hydrogen or nitrogen widely used in gas phase chemical film formation methods such as MO C VD may be used.
- chemically compared Temperature rise in active hydrogen may damage the crystallinity and crystal surface flatness and should not be performed for a long time.
- the substrate temperature when forming the second layer is preferably 800 ° C. or higher.
- the substrate temperature is high, atomic migration is likely to occur, and dislocation looping easily proceeds. More preferably, it is 90 ° C. or higher, and particularly preferably 100 ° C. or higher.
- the film formation must be performed at a temperature lower than the temperature at which the crystals decompose, and a temperature of 120 ° C. or higher is not suitable as the growth temperature of the second layer.
- any material can be used as long as it is generally a substrate on which an III group nitride compound semiconductor crystal can be formed.
- the oxide substrate is known to cause chemical modification by contact with ammonia at a high temperature. Also for metal substrates, etc., the first layer acts as a coat layer, which has the effect of preventing chemical alteration and can be used as an effective film formation method.
- the substrate is preferably subjected to wet pretreatment.
- pretreatment can be performed using a method such as sputtering.
- the surface can be prepared by touching in Ar or N 2 plasma.
- plasma such as Ar gas or N 2 gas
- plasma particles act on the substrate efficiently by applying a voltage between the substrate and the chamber.
- a semiconductor stacked structure having functionality can be stacked to form various semiconductor elements.
- an n-type dopant such as Si, G e and Sn
- a P-type conductive doped with a P-type dopant such as magnesium.
- a sex layer As a material, InGaN is widely used for the light emitting layer, and A1GaN is used for the cladding layer.
- a device in addition to a light emitting element, it can be used for a photoelectric conversion element such as a laser element and a light receiving element, or an electronic device such as HBT and HEMT.
- a photoelectric conversion element such as a laser element and a light receiving element
- an electronic device such as HBT and HEMT.
- Many of these semiconductor elements are known in various structures, and the element structure laminated on the second layer of the group III nitride compound semiconductor multilayer structure of the present invention is the well-known element structure. There is no limitation including.
- a light emitting element in the case of a light emitting element, it is possible to package an element manufactured by this technology and use it as a lamp.
- a technology that changes the color of emitted light by combining with a phosphor is known, and this can be used without any problems. For example, it is possible to obtain light having a longer wavelength than that of the light emitting element by appropriately selecting the phosphor, and by mixing the light emitting wavelength of the light emitting element itself with the wavelength converted by the phosphor, white light can be obtained. It can also be a package.
- a layer including a columnar crystal having a clear crystal interface made of A 1 N is formed as a first layer using an RF sputtering method, and a second layer is formed thereon.
- a layer made of G a N was formed using the MQ C VD method.
- the spatter used has a high-frequency power supply and a mechanism that can move the position of the magnet in the target.
- the substrate is heated to 75 ° C. in a sputtering apparatus, nitrogen gas is introduced at a flow rate of 15 sccm, the pressure in the chamber is maintained at 0.0 8 Pa, and the substrate is The substrate surface was cleaned by applying a high frequency bias of 50 W to the side and exposing to nitrogen plasma.
- the substrate temperature was lowered to 500 ° C.
- a high frequency bias of 2 00 0 W was applied to the metal
- the pressure in the furnace was maintained at 0.5 Pa
- Ar gas was circulated at 15 sccm
- nitrogen gas was circulated at 5 sccm.
- a 1 N was deposited on the sapphire substrate.
- the growth rate was 0.12 2 m / s.
- the magnet in the target was swung during both substrate cleaning and film formation.
- the sample containing the GaN layer was prepared using the MO C VD method according to the following procedure. First, a sapphire substrate was introduced into the reactor. The sapphire substrate was placed on a carbon susceptor for heating in a nitrogen gas-substituted glove box.
- the substrate temperature was raised to 1150 ° C. by operating Hihiyu. After confirming that the temperature had stabilized at 1 1 5 0 ° C, the ammonia piping valve was opened and the flow of ammonia into the furnace was started. Subsequently, hydrogen containing vapor of trimethylgallium (TMGA) was supplied into the reaction furnace, and a process of attaching the II-I group nitride compound semiconductor constituting the second layer on the sapphire substrate was started. The amount of ammonia was adjusted so that the ratio of group V element to group I I group I element was 60,000.
- TMGA trimethylgallium
- the valve of the TMG a piping was switched, the supply of the raw material to the reactor was terminated, and the growth was stopped. After the growth of the GaN layer was completed, the power supply to the heater was stopped and the substrate temperature was lowered to room temperature.
- the first layer of A 1 N with a columnar crystal structure with a clear crystal interface is formed on the sapphire substrate, and an undoped GaN layer with a thickness of 2 is formed on it.
- a group III nitride compound semiconductor multilayer structure of the invention was produced.
- the substrate taken out had a colorless and transparent mirror shape.
- XRC X-ray rocking curve
- the first layer made of an A 1 N film having a number of crystal interfaces in a direction substantially perpendicular to the substrate surface is observed between the sapphire substrate and the second layer made of gallium nitride. It was done.
- the film thickness was about 50 nm. This layer seems to be a layer containing vertically long columnar crystals.
- the first layer covered the entire surface of the substrate.
- a sample was produced in which only the first layer was formed at the same time in the same chamber when the first layer was formed in the spatter.
- the plane of the A 1 N layer of the obtained sample was observed with a transmission electron microscope (TEM).
- TEM transmission electron microscope
- Fig. 3 is a TEM photograph
- Fig. 4 is a schematic diagram of Fig. 3.
- the first layer contains hexagonal columnar crystals with a clear crystal interface and a size of about 5 nm to 1 O nm at a density of about 5 X 10 3 ⁇ ⁇ ⁇ 2. It is out.
- Example 2 the production of a group III nitride compound semiconductor light emitting device using the group III nitride compound semiconductor multilayer structure of the present invention will be described.
- an n-type contact layer with Si as a dopant is formed on an undoped GaN crystal (second layer) manufactured over 6 using the same conditions as in Example 1.
- an epitaxial layer having an epitaxial layer structure for a semiconductor light emitting device shown in FIG. 1 was fabricated.
- Epitaxial wafer is formed on a c-plane sapphire substrate 9 by a growth method similar to that described in Example 1 and includes a columnar crystal structure with a clear crystal interface.
- a 1 N layer 8 On top of the 50 nm A 1 N layer 8 (first layer), in order from the substrate side, a 6 m thick ampere G a N layer 7 (second layer), l X 1 0 19 S 1 doped thickness 2 zm having an electron concentration of c m- 3 G a N layer 6, 1 X 1 0 of 18 c m-3 with a thickness of 2 0 OA having an electron density I riQj G aQ.
- gN clutch Layer 5 starting with GaN barrier layer and ending with GaN barrier layer, 6 layers of GaN barrier layer 3 with a layer thickness of 1600 A, and 5 layers of layer thickness of 30 A non de one-flops I n 0. 2 G a Q .
- the fabrication of the wafer 18 having the epitaxial layer of the semiconductor light emitting device structure described above was performed by using the same MO C VD apparatus as used in Example 1 for the stack of the Si layer G a N layer 6 and the subsequent layers. And performed in the same manner as the formation of the second layer in Example 1.
- an epitaxial wafer having an epitaxial layer structure for a semiconductor light emitting device was fabricated.
- the Mg-doped Al Q. 02 G a Q. 98 N layer showed p-type without annealing to activate p-type carriers.
- FIG. 2 is a plan view of the electrode structure of the light emitting diode fabricated in this example.
- 10 is the 11-side electrode
- 1 is the exposed side of the Si-doped GaN layer 6 to form the side electrode
- 12 is the p-electrode bonding pad
- 13 is translucent p electrode.
- the produced wafer is Mg-doped A l by a known photolithography technique. .. 2 G aQ. 98 Translucent p-electrode 1 3 made of ITO on the surface of the N layer, and then on the surface of the p-electrode 1 3 A p-electrode bonding pad 1 2 having a structure in which Ti and Au are laminated is formed as a p-side electrode. After that, dry etching is performed on the wafer 18 to expose the portion 11 of the Si-doped G a N layer forming the n-side electrode, and the exposed portions of Cr, T i and A u are sequentially formed from the semiconductor side. An n-side electrode 10 consisting of three layers was produced. Through these operations, an electrode with the shape shown in Fig. 2 was fabricated on the wafer.
- the back surface of the sapphire substrate was ground and polished into a mirror-like surface.
- the wafer is cut into a 3500 im square chip, placed on the lead frame so that the electrode is on top, and connected to the lead frame with a gold wire to form a light emitting diode. It was.
- the forward voltage at a current of 20 mA was 3.0 V.
- the emission wavelength was 470 nm and the emission output was 15 mW at a current of 20 mA.
- Such characteristics of the light-emitting diodes were obtained with no variation for the light-emitting diodes fabricated from almost the entire surface of the fabricated wafers.
- an A 1 N layer is formed on the a-plane sapphire substrate using the DC sputtering method as the first layer, and then the second layer is formed on the G layer using the M ⁇ C VD method. a N layer was formed.
- the substrate temperature during sputtering was set to 500 ° C.
- the film thickness is the same as in Example 1.
- the surface of the wafer 18 taken out from the reaction apparatus was cloudy, and many pits were observed on the surface.
- FIG. 8 is a diagram schematically showing FIG.
- the first layer of A 1 N formed by DC sputtering has a columnar crystal density of about 5 X 10 2 m 2 with a clear crystal interface. However, it has been found that no clear columnar crystals are contained at the density specified in the present invention.
- the double-crystal X-ray rocking curve of the first layer was measured, and the (0 0 0 2) plane measurement showed a half-value width of 0.7 degrees.
- a layer containing a columnar crystal with a clear crystal interface composed of A 1 N is formed as a first layer using a rotational sword type RF sputtering method.
- a GaN layer was formed as a second layer by MOCVD, and the same epitaxial layer for LED as in Example 2 was formed thereon.
- the substrate temperature during sputtering was 700 ° C., and other conditions were the same as in Example 2.
- the first layer made of A 1 N deposited in 1) is a columnar crystal with a clear crystal interface with a crystal width of about 5 to 10 nm and a density of about 5 ⁇ 10 3 / im 2. Was included.
- the Wahachi manufactured as described above was made into a light emitting diode chip in the same manner as in Example 2.
- the forward voltage at a current of 20 mA was 3.1 V.
- the emission wavelength was 46 O nm and the emission output was 13 mA at 20 mA.
- the characteristics of such a light-emitting diode are manufactured from almost the entire surface of the manufactured wafer. The obtained light-emitting diodes were obtained without variation.
- an AlGaN layer doped with Si is formed as a second layer using the MO C VD method, and the same LED epitaxial layer as in Example 2 is formed thereon.
- the A1 composition of the first layer was 70%, and the A1 composition of the second layer was 15%.
- the substrate temperature during sputtering was set at 500 ° C. Other conditions are the same as in Example 2.
- the surface of the wafer taken out from the reactor was a mirror surface.
- the first layer was observed in the same manner as in Example 1.
- the A 1 G a N layer formed by RF sputtering contained columnar crystals with a crystal interface with a crystal width of about 20 nm and a density of about 2 XI 0 3 / m 2 .
- the wafer manufactured as described above was used as a light emitting diode chip in the same manner as in Example 2. This time, electrodes were installed on the top and bottom of the laminated structure side and the substrate side. When a forward current was passed between the electrodes, the forward voltage at a current of 20 mA was 2.9 V.
- the emission wavelength was 460 nm, and the emission output was 1 O mW at a current of 20 mA.
- Such characteristics of the light-emitting diode were obtained with no variation for light-emitting diodes fabricated from almost the entire surface of the fabricated wafer.
- the first layer is formed on a ZnO (0 0 0 1) substrate by using a PLD method in which a target is excited with a C 0 2 laser. Then, a layer containing columnar crystals with a clear crystal interface is formed, and a layer of A 1 G a N doped with Ge is formed thereon as a second layer using the MO C VD method.
- the same LED epitaxial layer as in Example 2 was formed.
- the A 1 composition of the second layer was 10%.
- the substrate temperature during the formation of the first layer was set to 7500C.
- we tried to produce a green LED near 525 nm this time we increased the flow rate of the In raw material during the formation of the light-emitting layer.
- the surface of the wafer taken out from the reactor was a mirror surface.
- the first layer was observed in the same manner as in Example 1.
- G a N layer was film by the PLD method, the width of each crystal about 5 nm, density of 5 X 1 0 3 or Roh ⁇ m 2 about the crystal interface contained distinct columnar crystals.
- the wafer manufactured as described above was used as a light emitting diode chip in the same manner as in Example 2.
- the electrodes were placed above and below the laminated structure side and the substrate side.
- the forward voltage at a current of 20 mA was 3.3 V.
- the emission wavelength was 5 25 nm and the emission output was 10 mW at a current of 20 mA.
- Such characteristics of the light-emitting diode were obtained with no variation for light-emitting diodes fabricated from almost the entire surface of the fabricated wafer.
- an epitaxial layer structure having an epitaxial layer structure for a semiconductor light emitting device shown in FIG. I made Kishaluweiha.
- Epitakisaruueha has a columnar crystal structure formed by the same growth method as described in Example 1 on a c-plane sapphire substrate 9 and a 50 m thick A 1 N layer.
- G a N barrier layer and ending in G a N barrier layers Ri begins in, G a N barrier layer 3 of six layers of the 1 6 OA layer thickness, 5 layers of non-inductive In Q. 2 Ga with a layer thickness of 3 OA. .Multi-quantum well structure consisting of 8 N well layer 4 20 and 50 A Mg doped Al Q. i G ao.g N cladding layer 2 and thickness 0 Mg doped
- a 1 Q. Q 2 G a Q. 98 N layer 1 is laminated.
- FIG. 2 shows a plan view of the electrode structure of the semiconductor light emitting device manufactured in this example.
- 10 is an n-side electrode
- 1 1 is an exposed surface of a Ge-doped GaN layer 6 for forming an n-electrode
- 12 is an electrode bonding pad
- 13 is a translucent p-electrode. is there.
- Fabrication of the wafer 8 having the epitaxial layer having the above-described semiconductor light-emitting element structure was performed by the following procedure using the MO C VD method. The same procedure as in Example 1 was used until an A 1 N layer (first layer) 8 having a columnar crystal structure was formed on a sapphire substrate.
- an epitaxial wafer having an epitaxial layer structure for a semiconductor light emitting device was fabricated.
- the Mg-doped A 1 Q .0 2 Ga 98 N layer showed p-type without annealing to activate P-type carriers.
- a light-emitting diode which is a kind of semiconductor light-emitting element, was fabricated using an epitaxial wafer in which an epitaxial layer structure was stacked on the sapphire substrate.
- Mg d A. Q. 2Gafl For the wafers that were produced.
- dry etching is performed on the wafer to expose the portion 11 of the Ge-doped GaN layer forming the n-side electrode, and the exposed portion is composed of four layers of Ni, A1, Ti and Au.
- An n-side electrode 10 was prepared. Through these operations, an electrode having the shape shown in Fig. 2 was produced on the wafer. The wafer on which the p-side and n-side electrodes were thus formed was ground and polished on the back surface of the sapphire substrate.
- the wafer is cut into a 3500 m square chip, placed on the lead frame so that the electrode is on top, and connected to the lead frame with a gold wire and the light emitting element. did.
- the forward voltage at a current of 20 mA was 3.0 V.
- the emission wavelength was 470 nm and the emission output was 15 mW.
- an A 1 G a N layer is formed on the c-plane sapphire substrate using the RF sputtering method as the first layer, and the MO C VD method is formed thereon as the second layer.
- the substrate temperature was 300 and other conditions were the same as in Example 1.
- the composition of A 1 in the first layer and the second layer was the same, and A 1 was 20%.
- the surface of the wafer 8 taken out of the reaction device was a mirror surface, but when viewed with an optical microscope, it contained fine irregularities.
- the A 1 G a N layer deposited by RF sputtering was a columnar crystal, but in some places there was a portion where A 1 N was not formed, and it was not a continuous film, but covered only about 60% of the substrate. Was not.
- the wafer manufactured as described above was made into a light emitting diode chip in the same manner as in Example 6.
- the forward voltage at a current of 20 mA was 2.9 V. This value is too low, indicating that current is leaking.
- the emission wavelength was 460 nm and the emission output was only 7 mW.
- an aggregate of columnar crystals of GaN is formed on a ZnO (0 0 0 1) substrate using a PLD method in which a target is excited with a C 0 2 laser as a first layer.
- a layer of A 1 Ga N doped with Ge was formed as a second layer using the MO C VD method, and the same LED structure as in Example 6 was formed thereon.
- the A 1 composition of the second layer was 10%.
- the substrate temperature at the time of sputtering was set to 7500.
- the surface of the wafer 8 taken out from the reactor was a mirror surface.
- This cross section was observed using the cross-sectional TEM method.
- the deposited GaN layer consisted of columnar crystals with a width of about 5 nm for each crystal.
- the first layer covered the entire surface of the substrate.
- the wafer manufactured as described above was used as a light emitting diode chip.
- the electrodes were placed above and below the laminated structure side and the substrate side.
- the forward voltage at a current of 20 mA was 3.3 V.
- the luminescence wavelength was 5 25 nm and the luminescence output was 10 m W.
- the I II I nitride compound semiconductor multilayer structure of the present invention has a surface layer made of a II II nitride compound semiconductor crystal having good crystallinity. Therefore, by forming a group III nitride compound semiconductor crystal layer having further functions on this laminated structure, a semiconductor element such as a light emitting diode, a laser diode, or an electronic device having excellent characteristics can be obtained. Can be produced.
Abstract
Description
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EP07743255.7A EP2019437B1 (en) | 2006-05-10 | 2007-05-08 | Iii nitride compound semiconductor laminated structure |
CN2007800165680A CN101438429B (zh) | 2006-05-10 | 2007-05-08 | Ⅲ族氮化物化合物半导体叠层结构体 |
US12/300,306 US8148712B2 (en) | 2006-05-10 | 2007-05-08 | Group III nitride compound semiconductor stacked structure |
JP2008514533A JPWO2007129773A1 (ja) | 2006-05-10 | 2007-05-08 | Iii族窒化物化合物半導体積層構造体 |
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04297023A (ja) | 1991-01-31 | 1992-10-21 | Nichia Chem Ind Ltd | 窒化ガリウム系化合物半導体の結晶成長方法 |
JPH0586646B2 (ja) | 1984-02-14 | 1993-12-13 | Nippon Telegraph & Telephone | |
JPH11354846A (ja) * | 1996-01-19 | 1999-12-24 | Matsushita Electric Ind Co Ltd | 窒化ガリウム系化合物半導体発光素子及び窒化ガリウム系化合物半導体の製造方法 |
JP3026087B2 (ja) | 1989-03-01 | 2000-03-27 | 豊田合成株式会社 | 窒化ガリウム系化合物半導体の気相成長方法 |
JP3440873B2 (ja) | 1999-03-31 | 2003-08-25 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子の製造方法 |
JP2003243302A (ja) | 2002-02-15 | 2003-08-29 | Showa Denko Kk | Iii族窒化物半導体結晶、その製造方法、iii族窒化物半導体エピタキシャルウェーハ |
JP2004096021A (ja) * | 2002-09-04 | 2004-03-25 | Showa Denko Kk | Iii族窒化物半導体結晶、その製造方法、iii族窒化物半導体エピタキシャルウェーハ |
JP2005210091A (ja) * | 2003-12-22 | 2005-08-04 | Showa Denko Kk | Iii族窒化物半導体素子およびそれを用いた発光素子 |
JP2005244202A (ja) * | 2004-01-26 | 2005-09-08 | Showa Denko Kk | Iii族窒化物半導体積層物 |
JP3700492B2 (ja) | 1999-09-21 | 2005-09-28 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0817283A1 (en) * | 1996-01-19 | 1998-01-07 | Matsushita Electric Industrial Co., Ltd. | Gallium nitride compound semiconductor light emitting device and process for producing gallium nitride compound semiconductor |
US6713789B1 (en) * | 1999-03-31 | 2004-03-30 | Toyoda Gosei Co., Ltd. | Group III nitride compound semiconductor device and method of producing the same |
US7501023B2 (en) * | 2001-07-06 | 2009-03-10 | Technologies And Devices, International, Inc. | Method and apparatus for fabricating crack-free Group III nitride semiconductor materials |
WO2005071720A1 (en) * | 2004-01-26 | 2005-08-04 | Showa Denko K.K. | Group iii nitride semiconductor multilayer structure |
KR100841269B1 (ko) * | 2004-01-26 | 2008-06-25 | 쇼와 덴코 가부시키가이샤 | Ⅲ족 질화물 반도체 다층구조물 |
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Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0586646B2 (ja) | 1984-02-14 | 1993-12-13 | Nippon Telegraph & Telephone | |
JP3026087B2 (ja) | 1989-03-01 | 2000-03-27 | 豊田合成株式会社 | 窒化ガリウム系化合物半導体の気相成長方法 |
JPH04297023A (ja) | 1991-01-31 | 1992-10-21 | Nichia Chem Ind Ltd | 窒化ガリウム系化合物半導体の結晶成長方法 |
JPH11354846A (ja) * | 1996-01-19 | 1999-12-24 | Matsushita Electric Ind Co Ltd | 窒化ガリウム系化合物半導体発光素子及び窒化ガリウム系化合物半導体の製造方法 |
JP3440873B2 (ja) | 1999-03-31 | 2003-08-25 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子の製造方法 |
JP3700492B2 (ja) | 1999-09-21 | 2005-09-28 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子 |
JP2003243302A (ja) | 2002-02-15 | 2003-08-29 | Showa Denko Kk | Iii族窒化物半導体結晶、その製造方法、iii族窒化物半導体エピタキシャルウェーハ |
JP2004096021A (ja) * | 2002-09-04 | 2004-03-25 | Showa Denko Kk | Iii族窒化物半導体結晶、その製造方法、iii族窒化物半導体エピタキシャルウェーハ |
JP2005210091A (ja) * | 2003-12-22 | 2005-08-04 | Showa Denko Kk | Iii族窒化物半導体素子およびそれを用いた発光素子 |
JP2005244202A (ja) * | 2004-01-26 | 2005-09-08 | Showa Denko Kk | Iii族窒化物半導体積層物 |
Non-Patent Citations (2)
Title |
---|
JOURNAL OF CRYSTAL GROWTH, vol. 115, 1991, pages 628 - 633 |
See also references of EP2019437A4 * |
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JP2008053665A (ja) * | 2006-08-28 | 2008-03-06 | Kanagawa Acad Of Sci & Technol | 半導体基板の製造方法、半導体基板の製造装置及び半導体基板 |
JP2009155672A (ja) * | 2007-12-25 | 2009-07-16 | Showa Denko Kk | Iii族窒化物半導体の製造方法、iii族窒化物半導体発光素子の製造方法、iii族窒化物半導体製造装置、iii族窒化物半導体及びiii族窒化物半導体発光素子、並びにランプ |
JP2009170672A (ja) * | 2008-01-16 | 2009-07-30 | Showa Denko Kk | 光源、発光装置および表示装置 |
WO2009096270A1 (ja) * | 2008-01-31 | 2009-08-06 | Canon Anelva Corporation | AlNヘテロエピタキシャル結晶体とその製造方法、該結晶体を用いてなるIII族窒化物膜用下地基板、発光素子、表面弾性波デバイス、及びスパッタリング装置 |
JP2014123765A (ja) * | 2014-02-27 | 2014-07-03 | Sumitomo Electric Ind Ltd | ウエハ生産物、窒化ガリウム系半導体光素子 |
WO2017119305A1 (ja) * | 2016-01-07 | 2017-07-13 | Jfeミネラル株式会社 | 窒化アルミニウム単結晶 |
JP2017122028A (ja) * | 2016-01-07 | 2017-07-13 | Jfeミネラル株式会社 | 窒化アルミニウム単結晶 |
CN108463582A (zh) * | 2016-01-07 | 2018-08-28 | 杰富意矿物股份有限公司 | 氮化铝单晶 |
US10704162B2 (en) | 2016-01-07 | 2020-07-07 | Jfe Mineral Company, Ltd | Aluminum nitride single crystal |
JP2017138104A (ja) * | 2016-02-01 | 2017-08-10 | スタンレー電気株式会社 | 積層体を構成する元素割合の算出方法 |
JP2019142771A (ja) * | 2019-06-06 | 2019-08-29 | Jfeミネラル株式会社 | 窒化アルミニウムウェーハの製造方法 |
Also Published As
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JPWO2007129773A1 (ja) | 2009-09-17 |
US8148712B2 (en) | 2012-04-03 |
KR101066135B1 (ko) | 2011-09-20 |
TW200814369A (en) | 2008-03-16 |
CN101438429A (zh) | 2009-05-20 |
KR20080098550A (ko) | 2008-11-10 |
CN101438429B (zh) | 2011-04-27 |
TWI352436B (ja) | 2011-11-11 |
EP2019437A4 (en) | 2014-05-07 |
US20090146161A1 (en) | 2009-06-11 |
EP2019437B1 (en) | 2018-07-11 |
EP2019437A1 (en) | 2009-01-28 |
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