WO2007120075A1

WO2007120075A1 - Method for switching context of tasks and procedures in a processor

Info

Publication number: WO2007120075A1
Application number: PCT/RU2007/000124
Authority: WO
Inventors: Sergei Savvich Kovalenko; Sergei Andreevich Khromov; Yury Petrovich Krylatykh; Nikolai Petrovich Vasiliev; Andrei Vladimirovich Vinokurov
Original assignee: Limited Liability Company (Llc) 'unicorne Microsystems'
Priority date: 2006-04-18
Filing date: 2007-03-15
Publication date: 2007-10-25
Also published as: RU2006112635A; RU2320002C2

Abstract

The invention relates to computer engineering, in particular to processors used in a multitask operation mode and comprising hardware for automatically switching the task and procedure context. Said invention makes it possible to increase the switching speed of the task and procedure context and to reduce the number of used hardware. The result is attainable by the inventive method consisting in allocating available resources to each new task or procedure in the ring buffer of general-purpose registers for processing data and in a ring context switching stack for data characterising the pre-allocated context space in an external memory and in fully automatically preempting the contexts saved at the hardware level to the memory without using software when the ring buffer of the general-purpose registers and the ring context switching stack are full, wherein data from the ring context switching stack make it possible to organise the contexts preempted to the memory in the form of a linked list and, when necessary to restore the saved contexts.

Description

Metof of Taksks apd Rrosedures sopteht switcheship ip and rssessor

The invention relates to computing, and in particular to processors for data processing, designed to operate in multitasking mode, and can be used, in particular, in embedded applications.

When working in multitask mode, switching the context of tasks and procedures is usually required, i.e. implementation of the conservation and restoration of their corresponding processor resources. The task context includes resources such as instruction counter values, processor status words, general purpose registers, and contexts of all procedures caused by the task.

The difference between the task and the procedure is that the task is started by interruption (trp), and the procedure is called from the task (call), possibly with the transfer of parameters and, in essence, is a subroutine or function, upon completion of which it is possible to return the results to the given one task procedure. For the operating system, this is a subprocess of the task process.

In this description, the following abbreviated notation of terms is used:

ALU - arithmetic-logical device included in the processor; BI - instruction buffer /

BOP - a block of memory access for reading / writing data (LOAD / Store UP) /

BFAVI - block for generating the address of the selected instruction (ipstructiopopetсh upit); DK - command decoder /

DPRK - descriptor of the beginning and size of the memory area for context allocation (context location memory descriptor) /

IP - the identifier of the process (PID - rcеss idеptifiеr) _/

CBD - ring buffer RONs /

KSPK - ring stack providing context switching (ring stack context switching); OZU-D - random access memory for data storage /

OZU-I - random access memory for storing instructions / ПЗЗ - sign of the task launch / ПП - process priority /

PRVO - signs of the result of the completed operation / MSSP - sign of the BSC _/ RO-CBD - register of access to the CBD; RO-KSPK - the register of the appeal to KSPK; RO-P - memory access register / RONs - general purpose registers; CK - command counter;

SSP - processor status word (PSW - processor statusus);

СУПК - the control structure of the context switching mechanism and the choice of CBD and KSPK operating modes

(context switching control structure); UV-KBR - pointer to the beginning of the current window in the CBD

(pointer to the top of the CBD);

UV-KSPK - a pointer to the beginning of free space in the KSPK (top pointer KPSK);

UD-CBD - a pointer to the beginning of filling the CBD (bottom indicator of the CBD);

UD-KSPK - a pointer to the beginning of filling the KSPK (bottom indicator KPSS);

UKK-P - a pointer to the end of the context in RAM (pointer to the end of the context); USA-P - a pointer to the address of RAM for writing / reading the next context element

(pointer to the next address in memory); UT-DPRK - pointer to a row of the DPRK table (pointer to the DPRK table);

CSR-CBD - the number of stored CBR RONs of the relevant context. One of the first implementations of context switching support, which has become widespread, refers to RISC processors with SPARC V8 architecture (Те SPARC Architects Map. Version 8. SPARC International IPs, 1992, 303 p.). One of the features of SPARC V8 is a large register file with circular buffer properties and register window technology. However, in this case, the control of the context switching mechanism should be implemented by software, which leads to a relatively low context switching speed compared to the possible hardware implementation of this mechanism and, therefore, leads to limited processor performance of this architecture.

The task of increasing the context switching speed has been partially solved in the processors of the TriCore architecture (TriCore ™ 1. 32-Bit Upgrade Rocessor Core. Volume 1: Vl. implement context switching hardware. However, all saved contexts are placed in the memory module, the access time to which is significantly longer than the access time to the internal registers of the processor.

A significant increase in the context switching speed was achieved due to the use of two register files in the processor for intermediate storage of contexts with their subsequent transfer to the memory module (patent US6553487B1, 04/22/2003). The context switching procedure in this implementation of the method can be accelerated by using a larger number of register files. However, as the number of register files increases, the complexity of managing them increases significantly.

The closest analogue of the claimed invention is a method of switching context in the processor (patent US6115777A, 09/05/2000), which consists in the operational storage of contexts in a large circular register stack and transferring contexts to memory when it is full. Moreover, each ring stack register, in addition to the data storage area, contains an additional information bit indicating the validity of the stored data. The indicated implementation of the context switching method uses an additional register for temporary storage of the indicated information bits. In addition, to control the mechanism for saving and restoring contexts, registers of pointers to storage areas of contexts in external memory were used. This method is also able to provide high speed context switching.

The objective of the claimed invention is to minimize hardware costs for the implementation of context switching while maintaining a relatively high speed of context switching and its functionality. b

The technical result in this case is to increase the switching speed of the context of tasks and procedures.

This technical result is provided by a method of switching the context of tasks and procedures in the processor.

The technical result is achieved due to the fact that according to the method of switching the context of tasks and procedures in the processor, the processor contains KBP, register SSP, CK and KSPK. Moreover, KSPK is made with the possibility of storing the values of the SSP and CK context, and data characterizing the placement of task contexts in the RAM. The processor also comprises hardware for context switching control (CMS). Moreover, the method includes sequential reservation of contexts in KBP and KSPK with the subsequent restoration, if necessary, of contexts in the reverse order. When an overflow of KBP or KSPK produce the crowding out of the earliest context in memory. If necessary, such repression is repeated until the resources required by the task or procedure to be started are released in KBP and / or KSPK. Upon completion of a task or procedure, contexts are restored from memory to, in the reverse order, the released resources of KBP and KSPK in the absence of the necessary resources in KBP and / or KSPK.

The way to switch the context of tasks and procedures in the processor is that it contains a ring buffer of general purpose registers, a status word register a processor, a command counter, a context switching ring stack, configured to store values of the processor status word register and a context command counter, data characterizing the placement of task contexts in RAM and hardware designed to control context switching, and containing sequential reservation of contexts in the ring buffer general purpose registers and ring stack context switching with subsequent recovery, or with context recovery In the reverse order, when the ring buffer of general purpose registers and the ring context switch stack are overflowed, the earliest context is forced out into the memory by reading 14 from the register reference access ring stack values of the current register of the context switch ring stack, and this extrusion is repeated until release the resources required by the task or procedure to be run in the ring buffer of general purpose registers and / or the ring switch stack text, and upon completion of a task or procedure, contexts are restored from memory in the reverse order to the freed resources of the ring buffer of general registers and the ring stack of context switching, and in the absence of the necessary resources in the ring buffer of general registers and the annular stack of context switching, when placing the contexts of tasks and procedures in the RAM, a pointer to the end of the context in the memory for the previous context is written to the first element of the context of the task; a handle to the beginning and size of the memory area is written to the last element of the context of the task to place the context of the next task, and the contexts of all The procedures of the task are sequentially placed inside the context of the given task, when forming the processor status word, the processor status word is written into the register the values of the bits of the attribute fields of the result of the performed operation, the process priority, the number of general-purpose registers to be saved, the circular buffer registers of the general purpose registers of the context of the given task or procedure, the process identifier, the sign of the task launch and the sign defining this word as the processor status word when switching the context when transferring contexts of tasks and procedures in the RAM provide a command to the processor, and as a result of decoding and execution of this command, the process rum all contexts other than the current sequentially transferred from the processor to the memory, wherein for each context value transferred processor status word, program counter, and start the descriptor storage area to accommodate the size of context and a pointer to the end of the context in the memory during setup context switching parameters of tasks and procedures in the processor, the processor is instructed to write new values to the service context switching registers decoded and executed by the processor, the service registers including a register pointer to a row table of descriptors of the beginning and size of memory areas for placing contexts.

Moreover, according to the method of placing contexts of tasks and procedures in RAM, in RAM-D memory cells allocated for the first element of the context of the task, write UKK-P for the previous context, and in the last element of the context of the task in the same way write the DPRK of the next task. Moreover, the contexts of all procedures of the task are sequentially and continuously placed inside the context of this task.

According to the method of forming the MSS, the values of the bits of the fields PRVO, PP, ChSR-KBR, IP, PZZ and MSSP are recorded in the MSS register.

According to the method of transferring the contexts of tasks and procedures to RAM, the processor is given a command, characterized in that as a result of decoding and execution of this command by the processor, all contexts, except the current one, are sequentially transferred from the processor to memory. Moreover, for each context, the values of BSC, CK, DPRK and UKK-P are transferred. According to the method of initial setting the context switching parameters of tasks and procedures in the processor, the processor is instructed to write new values to the service context switching registers decoded and executed by the processor. Moreover, one of the service registers is the UT-DPRK register.

In particular cases of its implementation, the claimed invention is additionally characterized by the fact that in the method of switching the context of tasks and procedures in the processor, the contexts for all procedures of the task are sequentially placed in memory, inside the context of this task.

In another particular case, the data characterizing the placement of task contexts in memory is represented by the values of DPRK and UKK-P associated, respectively, with the value of UCC-P for the previous context and the value of the DPRK of the next context.

At the same time, the QPSC can be arranged to place the SSP and CK values of one context or the values of CCC-P and DPRK in one register of the stack, one of which refers to the first context, and the other to the second context, which are adjacent.

In addition, in order to oust the context into memory, the values of RONs, CK, and BSC of the ousted context are sequentially written into the memory. Number of RONs, values which will be stored in the CBD when the context is supplanted, is determined based on the values of the fields CSR-KBR and PSZ MSS. Moreover, in the case of the truth of the RPS, the values of all RONs of the problem are recorded, otherwise, the values of RONs, the number of which are specified in the CSR-KBR, are recorded. Immediately after the SSP value, the DPRK value is recorded for placing the next context, and the value of the CCC-P of the extruded context in the memory is recorded at the beginning of the memory area to place the next context.

For such an implementation of the method, the processor contains architectural registers DPRK, UKK-P and USA-P. When switching the context of the task, the values of UKK-P and DPRK from the indicated registers are entered into the KSPK. The DPRK value is obtained from the DPRK table containing all predetermined DPRK values. The initial value of the register UKK-P is set equal to the value of the register DPRK. When the context is supplanted, the tasks in memory increase the value of the UKK-P register by the size of the context elements stored in the memory. Write to the memory by means of the PO-P, configured to display the memory element with the address contained in the register USA-P. Moreover, after recording in RO-P, the value of USA-P is increased by a single value.

To provide the possibility of reconstructing contexts from memory, in the SSP and UKK-P initially include the attribute field SSP or UKK-P, respectively. Moreover, when recovering contexts from memory, a context element with an address from USA-P is read from memory by means of RO-P. If this element has the sign of SSP, then the context to be read is the context of the procedure embedded in the task, to restore which the values of SSP and CK are successively read in the KSPK, and RONs, numerically corresponding to the value of CSR-KBR from SSP, in KBR. If the element originally read from memory has the sign of UKK-P, then the read context is the context of the task. In this case, a transition to the address from the read UKK-P is carried out, indicating the end of the context previously stored in the memory, after which the values of the SSP and CK are read in sequence in the KSPK, and all RONs of this context in the KBR.

The method for placing the contexts of tasks and procedures in RAM in their particular cases is characterized by the fact that the value of UCC-P is read from the UCC-P field of the KSPK register, and the value of DPRK is read from the DDRK field of the same register. Or, in the case when no procedures were called from the task, the UCC-P value is calculated as the sum of memory elements for placing the RON values, CK values, the SSP value of this task, and the DPRK values of the following context. If there are procedures called up from the task, the sum of the addresses of the memory elements additionally includes the addresses of the memory elements to place the RON values, CK values, and SSP values of all procedures of this task. In the particular case of this method, UKK-P contains a feature field that defines the contents of this register as UKK-P. Moreover, the attribute field UKK-P has a zero value, cannot be changed, and is located in the thirty-second from the beginning of the register bit, which is the last.

For each memory area intended for placing the context of the task in it, a DPRK value can be generated in advance, and when the task is started, the corresponding DPRK value is recorded in the CSPC.

Any of the private implementations of this method can be further characterized in that each context occupies a continuous memory area.

The method of forming SSP in special cases is characterized by the fact that the value of the bits of the SSSP field is always set different from the value of the bits having the same position in UKK-P. In this case, the bit of the MSSP field is always set equal, for example, to one.

In another particular case of the implementation of the method, when starting a task, the value of the bit of the PPZ field is set to unity.

In another particular case, the values of the bits of the CSR-KBR field are directly set by the processor command having the code 11100100 in their high order bits, and the field of four bits in the first low order bits for the value of the number of stored RONs specified by the write command in the SSP. In any of the particular cases of this method, four bits are sequentially allocated to the FIR fields, the PP field and the CSR-KBR field starting from the beginning of the MSS, the next five bits are allocated to the IP field, and the thirty-second bit, which is the last, is allocated to the MSS field.

In the particular case of the method of transferring the contexts of tasks and procedures into the RAM, the command issued to the processor has the code 11101100 in its high order bits.

In one of the special cases, the method of initial setting the parameters for switching the context of tasks and procedures in the processor is additionally characterized by the fact that the service registers include the KSPK working registers, and the new values recorded are DPRK.

In another particular case, the method is characterized in that the service registers include the UV-KSPK register.

In any of the particular cases of this method, the write command issued to the processor may have a code 11101111 or 11011101 or 01110000 in its bits 25 through 32.

These sets of features provide the specified technical result in all cases to which the requested amount of legal protection applies.

The invention is illustrated by the following schemes: Fig. 1: schematic diagram of the context switch; Fig. 2: diagram of a general context switching algorithm; Fig. 3: diagram of the algorithm for displacing the context in RAM; Fig. 4: a sequence diagram of the start of the context switching mechanism; Fig. 5: simplified block diagram of the microprocessor "Orchid".

The implementation of the invention is illustrated by the example of a processor in which a fully hardware-based mechanism for switching the context of tasks and procedures is implemented. Initial tasks require only memory areas for placing contexts.

The processor contains the architectural registers CK, SSP, DPRK, UKK-P, UT-DPRK and USA-P, as well as the KBR 1 and KSPK 2 shown in FIG.

BSC characterizes the task or procedure, and CK characterizes the stage of their implementation.

The architectural registers DPRK, UKK-P, UT-DPRK and USA-P are made separate from KBR 1 and KSPK 2, and are designed to organize the storage of contexts in RAM 3.

CBD 1 is a collection of 32-bit registers. The processor directly processes data only from registers falling into the current window (frame) 4. These registers are RONs of the task or procedure being performed. In this example implementation of the method, the RON window contains 16 registers. When switching between tasks or procedures, the shift of window 4 is from 1 to 16 registers.

Addressing RONs in CBD 1 is such that the address of the next register is 1 higher than the address of the previous register, and when the address of the most recent register is reached, the next address will belong to the very first register.

For the management of CBD 1 are the registers UD-CBD and HC-CBD.

KSPK 2 is a stack of registers for storing the values of SSP, CK, DPRK and UKK-P, corresponding to RONs from CBD 1. A pair of values {KCP, CK} or a pair of values {UKK-P, DPRK} can be written to each register of KSPK 2 . Moreover, UKK-P should relate to the first of two neighboring contexts, and the value of DPRK to the second context, immediately following the first. Due to this, KSPK 2 implements the functions of the return stack (returp stask) and the stack of memory accesses.

The address in KSPK 2, at which the following entry can be made, is contained in the UV-KSPK register. In order to be able to distinguish between occupied and free areas of KSPK 2, use the register UD-KSPK.

Reading and writing to the registers KBR 1 and KSPK 2 is carried out through the registers RO-KBR and RO-KSPK, which are the registers of indirect addressing.

RO-CBD is configured to display a CBD element 1 with the address contained in the register UD-CBD. Moreover, after reading from the RO-CBD, the value of the address in the register UD-CBD increases by a single value. Before writing to the RO-CBD, the address in the UD-KBR is reduced by a single value.

RO-KSPK is made with similar properties in relation to the register UD-KSPK.

To implement the context switching mechanism, special fields are included in the BSC and UKK-P.

The BSC format is characterized by the fact that the BSC contains the fields of attributes PRVO, PP, ChSR-KBR, IP, PPZ and PSSP. The value of the bit of the PSSS field is always set different from the value of the bit having the same position in UKK-P, which allows them to be distinguished when restoring the context.

For the switching mechanism of the task context to work, the values of the DPRK must be determined, containing data on the size and location in memory of 3 of all areas for the saved contexts. All DPRK at the stage of initial installation of the processor are placed in table 5 DPRK in memory 3. The line for reading from table 5 DPRK determines the value of the register UT-DPRK.

Context switching in the processor is as follows.

After receiving b (figure 2) the interrupt signal is checked 7 for the availability of free resources in CBD 1 and KSPK 2. A necessary condition for the availability of free resources for a new task in this processor example is the presence of at least 16 free RONs in CBD 1 and at least two free register lines in KSPK 2. If the necessary resources are not available, 8 of the earliest (old) context is forced out of CBD 1 and KSPK 2 in random access memory 3.

If the necessary free resources are available, 9 current contexts are backed up in CBD 1 and KSPK 2, which includes an offset of 10 in KBR 1 of the current RON window by increasing the value of HC-CBD by the value of CSR-KBR from the current SSP. In this case, the value of the CSR-CBD is inherited from the previous context or, if necessary, is reinstalled programmatically.

Then, the 11 values of the SSP and CK registers related to the current task are stored in KSPK 2 at the address contained in the UV-KSPK 2. These values are written in one register and represent one line in KSPK 2.

In the next line of KSPK 2 write 12 values of DPRK for the new launched task and UKK-P for the current task, which is reserved. Moreover, the value of the DPRK is read from the row of the DPRK table in memory by UT-DPRK, and the UCC-P is calculated as the sum of memory elements for placing RONs, CK, MSS and DPRK. If there are procedures called from the task, the sum of memory elements additionally includes memory elements for 7 000124

19 placement of RONs, CK and BSC of all procedures.

After successfully backing up 9 current contexts, 13 registers of MTP and CK are initialized for the task to be started.

The crowding out 8 of the earliest context from the CBD 1 and the BSCC 2 into the RAM 3 is illustrated in FIG. 3, and includes reading 14 from the RO-BSCC values of the current register of the BSCC.

Since the MTS contains the field of the PPZ, it is always possible to determine 15, this context refers to the task or procedure.

If this context refers to the task, then the number of subsequent reading cycles is set to 16 equal to the total number of RONs of the task - 16. In the case of the context of the procedure, the number of subsequent reading cycles is set to 17 equal to the value of the CSR-CBD from the BSC. After that, the required number of 18 cycles of reading values from the RO-CBD and their writing to the RO-P are performed. Register RO-P is a register of indirect addressing and displays a memory element with the address contained in USA-P. Moreover, before reading from RO-P, the contents of USA-P are increased by a single value, which leads to a shift of the pointer to the next memory element.

Thus, the stored RONs of the same context are transferred to the RAM 3.

Then, the value of CK and BSC is recorded in PO-P 19. If this context is the 20th context of the procedure, then its extrusion into RAM 3 is completed 21.

If this context is the 20 context of the task, then a sequential reading of 22 from the RO-KSPK pair of UKK-P and DPRK values is made, writing 23 in the RO-P values of the DPRK, writing 24 in the USA-P values of the DPRK and writing 25 in the RO-P values UKK-P. Thus, the extrusion of the task context into RAM 3 is completed 21. Moreover, the contexts of all procedures caused by this task are sequentially placed inside the context of this task.

There may be situations when it is necessary to transfer all saved contexts from CBD 1 and KSPK 2 to memory 3. For example, in order to view or change some context, in particular, the value of the SSP. For this, the processor command system must include a command for transferring the contexts of tasks and procedures to memory 3, as a result of decoding and execution of which all contexts, with the exception of the current one, must be transferred from the processor registers to memory 3.

When the current task is completed, it is automatically restored to the context from which the current task was called.

Upon completion of the task, the HC-CBFR decreases by a single value, and at the same time, the HC-CBD decreases.

The values of the resulting pointers are compared with the values of UD-KBR and UD-KSPK, on the basis of which the availability of the required data in KBR 1 and KSPK 2 is determined. If there is no data required for restoration in them, the mechanism for their recovery from memory 3 is automatically turned on. Moreover, the value of PO-P already reflects USA-P content, indicating a place in memory 3 from which recovery should be made.

If this context element is UKK-P, then go to the address contained in it, and then sequentially read in KSPK 2 values DPRK, SSP, CK. The values of 16 RONs are transferred to KCB 1. After that, the value of UKK-P of the previous context located in the last context element in memory 3 is entered in KSPK 2.

If the current context element is SSP, then SSP, CK are transferred to KSPK 2, and RONs are transferred to KCB 1, the number of which is recognized from the CSR-KBR field of the read SSP.

The organization of contexts in CBD 1, KSPK 2, and memory 3 is illustrated by the example shown in FIG. 1, in which the context of one task is highlighted.

RONs 26 CBD 1 and data 27 KSPK 2 represent the context of one task.

In the situation shown in FIG. 1, the context of the task "B" includes two contexts, one of which relates directly to this task - the context "IN", and the second refers to the procedure called "Bl" from it. Communication contexts in memory 3 is organized due to the fact that in the last element 28 of the previous context "A" write the value DPPK (B) that determines the location of the first context element "B". The value UKK-P (A) is recorded at this memory address, indicating the location of element 28 in memory. Moreover, to read the values DPPK (B) and UKK-P (A) from KSPK 2 requires one read operation, because these values are located in one register KSPK 2.

Following UKK-P (A), the values of 29 RONs, CK, and BSC are recorded in memory for all contexts included in the context of this task. Then the value UKK-P (B) is placed in the very first element 30 of the context of the task "B".

The startup sequence of the context switching mechanism is illustrated in Fig. 4.

After turning on 31 processor power, it is necessary to apply 32 to it an external reset signal (RESET), through which the initial setup of 33 processor registers is performed. In this case, the highest priority is set in the SSP register and the initial value of CK.

After removing the RESET signal, the processor starts to execute the program from the specified address. At the same time, the table of interrupt vectors and the DPRK table have not yet been determined. In this mode, the processor cannot respond to interrupts and switch from task to task, but at the same time it can 7 000124

23 call procedures with a maximum nesting depth of up to eight.

First, a 34 initial processor installation program is executed, after which a 35 command is executed for the initial installation of the mechanism for saving / restoring the context of tasks when the contexts are pushed into memory, and 36 primary tasks are launched.

The initial setup program of the processor generates 37 DPRK tables, forms 38 UT-DPRK. Then, a 39 interrupt vector table is generated and a 40 pointer to an interrupt vector table is generated.

Upon completion of these steps, it becomes possible to execute the initial installation command 35 of the mechanism for saving / restoring the context of tasks when the contexts are pushed into memory (RESTART), which leads to the reading of the first value from the DPRK table and its placement 41 in the KSPK. Then, from the table of interrupt vectors, 42 SSP and CK values corresponding to the restart task are selected. After that, the bootstrap context is forgotten.

The RESTART command is executed as a special interrupt without saving the current context.

To bring the mechanism of saving / restoring contexts in memory to their initial state, the address of the zero descriptor of the DPRK table should be written in the UT-DPRK register. Then write zero values in the registers UV-CBD, 24

UD-KBR, UV-KSPK and UD-KSPK. A pair of DPRK values is recorded in KSPK 2, after which the value of the UV-KSPK is increased by a single value and the value of the DPRK is assigned to the UCC-P register.

An example implementation of the claimed invention is a microprocessor for embedded applications "Orchid". In Fig. 5 presents a simplified structural diagram of this processor.

Microprocessor "Orchid" is a processor with a reduced set of instructions (RISC) and is characterized by fully automatic support for the mechanism of switching tasks and procedures, and all the necessary steps for this are performed at the hardware level, except for the formation of the DPRK table.

"Orchid" contains KBR 1, ALU 43, DK 44 and BI 45, CK 46 and BFAVI 47, as well as BOP 48, which are typical for a number of RISC processors.

A significant difference between "Orchids" and conventional RISC processors is a context switching mechanism, an essential element of which are blocks KSPK 2 and CUPK 49 (figure 5).

In this case, the input-output data ALU 43 and the first input-output data BOP 48 are connected to the input-output data CBD 1.

DK 44 is connected by its data input to the data output of the RAM-I 50 through the BI 45 through the data bus. Outputs control DC 44 are connected to the control inputs of ALU 43, BOP 48, CK 46 and the first control input of CBD 1. DC 44 is also connected to the control system 49 through the input-output control.

The input-output data CK 46 is connected to the input-output data KSPK 2, and the data output is connected to the data input RAM-50 through BFAVI 47 and the address bus.

The first output of the CBD 1 data and the output of the KSPK 2 data are connected to the control system 49. The first and second control outputs of the control system 49 are connected, respectively, to the control input of the KSPK 2 and the second control input of the KBR 1.

The output of the control system 49 is connected to the data input of the BOP 48.

The second input-output data BOP 48 is connected to the input-output data OZU-D 51 via the data bus, and the data input RAM-D 51 is connected to the data output BOP 48 via the address bus.

CMSC 49 is an abstract generalization of the hardware needed to control context switching. These hardware, in essence, are means of working with system registers through read and write operations in accordance with a context switching algorithm implemented on the basis of a state machine. The hardware implementation of the control system can have various options and is not difficult with respect to existing technologies. Saving and restoring contexts to / from memory is as follows.

Based on the sign of overflow of resources, at least in KBR 1 or KSPK 2, a start-up signal is generated for СУПК 49, during the operation of which data is transferred from KBR 1 and KSPK 2 to RAM-D 51 through BOP 48, which generates the address, data and write signals to RAM- D 51

On the basis of the lack of resources in KBR 1 or KSPK 2, a start-up signal is generated for CPSK 49, which transfers data from RAM-D 51 to KBR 1 and KSPK 2 through BOP 48. In this case, BOP 48 generates an address, data and read signals from RAM-D 51.

Moreover, during the operation of writing to the SSP register from RAM-I 50, an instruction code is selected, which is subsequently decoded in DC 44 in order to obtain signals for controlling the logic of the SSB register writing, and when the command for transferring task and procedure contexts to RAM-D 51 is executed , from the RAM-I 50, an instruction code is selected, which is further decrypted in DC 44 in order to obtain a logical start signal for the control system 49.

The implementation of "Orchid" is characterized by the fact that the value of the bit of the PSSS field is always equal to one, and the corresponding bit in UKK-P always has a zero value. The value of the bit of the PPZ field when starting the task is equal to one.

In addition, the fields of PRVO, PP and CSR-KBR in the SSP "Orchids" occupy four bits starting from the beginning of the MSS, the IP field occupies the next five bits, and the MSSP field occupies the last, thirty-second bit. Moreover, setting the bits of the CSR-KBR field is carried out by a command with machine code 11100100 in its high order bits, and containing a field of four bits in the first low order bits for the value of the number of stored RONs in KBR 1 set by the write command in the SSP.

The command to transfer all saved contexts to the memory for "Orchid" has the code 11101100 in high order, and the write command issued to the processor has the code 11101111 or 11011101 or 01110000 in its bits 25 to 32.

Claims

Claim .

1. A method for switching the context of tasks and procedures in a processor containing a general-purpose circular buffer buffer, a processor status word register, an instruction counter, a context switching ring stack, configured to store processor status word register values and a context command counter that characterize the placement in the operational task context memory and hardware designed to control context switching and containing sequential reservation of contexts in the ring When the general buffer of general registers and the ring stack of context switching are overwritten, the earliest context is erased by reading from the register the call to the ring stack context switch the values of the current register of the ring stack context switch, and repeat such crowding until release the resources required by the task or procedure in the ring buffer of general registers and / or the ring context switch stack, and upon completion of the task or procedure, contexts are restored from memory in the reverse order to the freed resources of the ring buffer of general registers and the ring context switch stack, and when lack of necessary resources in the ring buffer of general purpose registers and the ring stack of context switching, when placing contexts back h and procedures in main memory in the first element of the context of the task write a pointer to the end of the context in memory for the previous context in the last element of the context of the task write a descriptor of the beginning and size of the memory area to place the context of the next task, and the contexts of all procedures of the task are sequentially placed inside the context of this task , when forming the processor status word, in the word register processor states record the values of the bits of the feature fields of the result of the operation, the process priority, the number of general purpose registers saved, the ring buffer of general purpose registers of the context of the given task or procedure, the process identifier, the sign of the task launch and the sign defining this word as the processor state word when switching the context, transferring the contexts of tasks and procedures into the RAM memory gives a command to the processor, and as a result of decoding, you When this command is completed by the processor, all contexts, with the exception of the current one, are sequentially transferred from the processor to memory, and for each context, the values of the processor status word, command counter, start descriptor and size of the memory area are transferred to place the context and a pointer to the end of the context in memory, at the initial setting the parameters for switching the context of tasks and procedures in the processor, the processor is instructed to write new values to the service registers of context switching, decoded and executed processor, moreover, service registers include a register pointer to a row in the table of descriptors of the beginning and size of memory areas for placing contexts.

2. The method according to p. 1, characterized in that in memory the contexts of all the procedures of the task are sequentially placed inside the context of this task.

3. The method according to claim 1, characterized in that the data characterizing the placement of task contexts in the memory is represented by the values of the start descriptor and the size of the memory area to place the context and the pointer to the end of the context in the memory associated with, respectively, the value of the context end pointer in the memory for the previous context and the descriptor value of the beginning and size of the memory area to place the context of the next context.

4. The method according to p. 3, characterized in that the annular context switching stack is configured to place in one register of the stack the values of the register of the processor status word and the counter of commands of one context or values a pointer to the end of the context in memory and a handle to the beginning and size of the memory area to place the context, one of which relates to the first context, and the other to the second context, which are adjacent.

5. The method of claim 3, wherein the processor status word register contains a field for the number of saved general purpose registers of the ring buffer of general purpose registers of the context of a given task or a procedure for the number of stored registers of general purpose ring buffer of the general registers of general purpose registers and a flag for launching a task for crowding out context, sequentially recorded in the memory of general registers, a command counter and a register of the processor status word of the displaced context, and in the case of truth n In terms of the task launch, all general purpose registers of the task are written; otherwise, the number of general registers specified in the number of general purpose registers of the ring buffer of general purpose registers of the context of the given task or procedure is recorded; immediately after the value of the register of the processor status word, the value of the start descriptor and the size of the memory to place the context to place the next context, and the value of the pointer to the end of the context in RAM in The crowded out context is stored in memory at the start address of the memory area to accommodate the next context.

6. The method according to claim 5, characterized in that the processor contains the registers of the start descriptor and the size of the memory area to place the context of the next context, a context pointer in the main memory and a pointer to a memory address for writing / reading the next context element, when switching the task context to the ring stack for providing context switching is loaded with the values of a pointer to the end of the context in memory and a descriptor of the beginning and size of the memory area to place the context of the next context from the indicated registers, p When in use, the start value descriptor and the memory area size to accommodate the context of the next context is obtained from a table containing all predetermined values the start descriptor and the size of the memory area to place the context of the next context, the initial value of the end context pointer register in the memory is equal to the value of the start descriptor register and the size of the memory area to place the context of the next context of the start descriptor and the size of the memory area to place the next context context, when the context is extruded increase the value of the register of the end of context pointer in memory by the size of the context elements stored in the memory, and recording creates a memory access register, configured to display a memory element with the address contained in the register, a pointer to the address of the main memory for writing / reading the next context element, and after writing to the memory access register, the value of the pointer to the main memory address for writing / reading the next the context element is incremented by a single value.

7. The method according to claim b, characterized in that the processor status word and the pointer to the end of the context in the RAM contain the attribute field the processor status word or the pointer to the end of the context in the RAM, respectively, and when recovering contexts from memory, read from memory a context element with an address from a pointer to a RAM address for writing / reading the next context element by means of a memory access register, if this element is characterized by the sign of a status word process ora, then the context being read is the context of the procedure embedded in the task, to restore which the values of the processor status word and command counter are sequentially read in the ring stack to ensure context switching, and the general registers numerically correspond to the number of general registers of the general buffer of the general register registers from processor status words in the general-purpose ring buffer of the general-purpose registers, in case the element ha was originally read from memory is characterized by a sign of a pointer to the end of the context in RAM, then the context being read is the context of the task, while they go to the address from the read pointer to the end of the context in RAM, and then sequentially read the values of the processor status word, the instruction counter in the ring stack of context switching, and all general-purpose registers of this context into the ring buffer of general-purpose registers.

8. The method according to claim 1, wherein the value of the context end pointer in the random access memory is read from the context end pointer field of the context switch ring stack register, and the context allocation memory descriptor value is read from the context placement memory descriptor field of the same register.

9. The method according to p. 1, characterized in that in the case when no procedures were called from the task, the value of the context end pointer in the main memory is calculated as the sum of memory elements for placing the values of general registers, values of the instruction counter, values of the processor status word the given task and the values of the memory descriptor of the context location of the next context, and in the case of the procedures called from the task, the sum of the addresses of the memory elements additionally includes the addresses of the memory elements for the placement of values Istria general purpose of the program counter values, the status word processor of all procedures.

10. The method according to p. 1, characterized in that the context end indicator contains a sign field defining the contents of this register as a context end indicator, wherein the sign field of the context end indicator in RAM is zero, cannot be changed and is located in the thirty-second from Begin register is the last bit.

11. The method according to p. 1, characterized in that for each memory area, designed to accommodate the context of the task, pre-form the value of the descriptor of the beginning and size of the memory area to place the context, and when the task starts the corresponding value of the context placement memory descriptor in the ring stack for providing context switching.

12. The method according to any one of p. 8-11, characterized in that each context occupies a continuous memory area.

13. The method according to p. 1, characterized in that the value of the bit of the attribute field, the processor status word is always set different from the value of the bit having the same position in the pointer to the end of the context in memory.

14. The method according to claim 1, characterized in that the bit of the attribute field is always set to one.

15. The method according to claim 1, characterized in that when the task is started, the value of the bit of the field is set to the start sign of the task equal to one.

16. The method according to p. 1, characterized in that the values of the bits of the field of the number of stored general purpose registers of the circular buffer of general registers of the corresponding context are directly set by the processor team having the code 11100100 in their high order bits, and a field of four bits in the first low order bits for the values set by the command to write to the processor status word the value of the number of general purpose registers to be saved.

17. The method according to any one of paragraphs.13-16, characterized in that the attribute fields of the result of the operation, the process priority field and the field of the number of saved general purpose registers of the circular buffer of general registers of the corresponding context are allocated four bits in sequence starting from the beginning of the word the processor state, the next five bits are allocated to the processor identifier field, and the thirty-second bit, which is the last, is allocated to the attribute field of the processor status word.

18. The method according to p. 1, characterized in that the command issued to the processor has a code 11101100 in its upper digits.

19. The method according to p. 1, characterized in that the service registers include the working registers of the ring stack context switch, and the recorded new values are descriptors of the beginning and size of memory areas for placing contexts.

20. The method according to p. 1, characterized in that the service registers include a register of a pointer to the beginning of free space in the ring context switching stack.

21. The method according to any one of paragraphs.19-20, characterized in that the write command issued to the processor has a code 11101111 or 11011101 or 01110000 in its bits 25 to 32.