WO2007117198A1 - Microelectromechanical pressure sensor with integrated circuit and method of manufacturing such - Google Patents

Microelectromechanical pressure sensor with integrated circuit and method of manufacturing such Download PDF

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Publication number
WO2007117198A1
WO2007117198A1 PCT/SE2007/000337 SE2007000337W WO2007117198A1 WO 2007117198 A1 WO2007117198 A1 WO 2007117198A1 SE 2007000337 W SE2007000337 W SE 2007000337W WO 2007117198 A1 WO2007117198 A1 WO 2007117198A1
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WO
WIPO (PCT)
Prior art keywords
membrane
layer
substrate
cavity
integrated
Prior art date
Application number
PCT/SE2007/000337
Other languages
French (fr)
Inventor
Frank Niklaus
Göran Stemme
Original Assignee
Niklaus Consulting
Bonsens Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to SE0600802-3 priority Critical
Priority to SE0600802 priority
Application filed by Niklaus Consulting, Bonsens Ab filed Critical Niklaus Consulting
Publication of WO2007117198A1 publication Critical patent/WO2007117198A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R19/00Electrostatic transducers
    • H04R19/01Electrostatic transducers characterised by the use of electrets
    • H04R19/016Electrostatic transducers characterised by the use of electrets for microphones
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0051Transmitting or indicating the displacement of flexible diaphragms using variations in ohmic resistance
    • G01L9/0052Transmitting or indicating the displacement of flexible diaphragms using variations in ohmic resistance of piezoresistive elements
    • G01L9/0054Transmitting or indicating the displacement of flexible diaphragms using variations in ohmic resistance of piezoresistive elements integral with a semiconducting diaphragm
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/02Sensors
    • B81B2201/0257Microphones or microspeakers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/02Sensors
    • B81B2201/0264Pressure sensors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019Bonding or gluing multiple substrate layers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R17/00Piezo-electric transducers; Electrostrictive transducers
    • H04R17/02Microphones

Abstract

The device according to the invention comprises an integrated device (10) with a pressure sensor (11) having a membrane (20) comprising a high performance material over a cavity (34). The pressure sensor (11) is integrated on a semiconductor substrate (14) that comprises an integrated circuit (15) so that the membrane (20) with the cavity (34) underneath is located at least partly over the integrated circuit (15). The present invention also provides a method for manufacturing an integrated device (10).

Description

Integrated device and method of manufacturing such

Technical field of the invention

The present invention relates to MEMS (Microelectromechanical Systems) pressure sensors or microphones.

Background of the invention

Various types of pressure sensors and microphones are used in medical, mobile, automotive and computer applications. For most applications, the electronics for the signal processing and sensor communications are provided on an electronic chip that is separate from the pressure sensor chip. This has the disadvantage of increased cost for two separate chips and the chip-scale integration of the MEMS pressure sensor or microphone and the electronic chip in a single package. Such a design also increases the total size of the resulting pressure sensor or microphone system. Although the present invention relates to both pressure sensors and microphones, the term pressure sensor is preferably used in the following.

In general, it is difficult to integrate e.g. high performance pressure sensors with a reference pressure cavity on prefabricated integrated circuit wafers. One reason therefore is that the deposition temperatures for the pressure sensor materials are limited to below 400 0C if the materials shall be deposited directly on standard integrated circuit wafers. Temperatures significantly higher than 400 0C destroy the electronics of the substrate. This prevents many high-temperature deposited and/ or mono-crystalline materials for the pressure sensor from being used on top of integrated circuit wafers.

One way to avoid this problem is to first fabricate the sensor on a semiconductor substrate and subsequently manufacture the integrated electronic circuits on the same substrate beside the sensor. However, pre-processed semiconductor wafers (e.g. with pressure sensors on the substrate) can not be easily introduced in IC foundries environments due to compatibility and contamination issues. Also, the total chip size is increased in such an approach, since the pressure sensor and the integrated electronic circuit are placed side by side on the chip. A method for manufacturing and integration of MEMS transducers made of high temperature deposited, epitaxially grown or mono-crystalline materials on integrated electronic substrates is disclosed in US7067345 , filed in 2001, and in SEO 102925, comprises an adhesive sacrificial bonding technique", filed in 2001. However the MEMS transducers that are described in the mentioned patents do not contain features such as cavities with a defined atmosphere, which typically is required to obtain a reference pressure in a pressure sensor.

Summary of the invention

Obviously the prior art has drawbacks with regards to being able to provide MEMS pressure sensors or microphones that comprises high performance materials and a cavity integrated on top of electronic circuits.

The object of the present invention is to overcome the drawbacks of the prior art. This is achieved by the device as defined in claim 1 and the method as defined in claim 18.

The device according to the invention comprises an integrated device with a pressure sensor having a membrane comprising a high performance material over a cavity. The pressure sensor is integrated on a semiconductor substrate that comprises an integrated circuit so that the membrane with the cavity underneath is located at least partly over the integrated circuit.

In addition the cavity is optionally hermetically sealed with a pre-defined pressure inside. Either the sealing layer at least partly covers the semiconductor substrate and the membrane or the cavity is enclosed in a layer underneath the membrane.

The high performance material is low-stress, high temperature deposited/ annealed and/ or crystalline materials such as mono-crystalline silicon, mono-crystalline SiGe, mono-crystalline SiC or polysilicon with a thickness of 0.05 μm up to 5 μm. Moreover, the high performance material may be at least partly doped, at least partly covered with a metal or metal alloy film or may comprise at least one integrated resistive element or transistor in order to enable read out from the pressure sensor. The semiconductor may be provided with different layers, such as passivation layers, electrodes or components.

The method according to the present invention comprises: bonding a first substrate comprising a pre-fabricated integrated circuit to a second substrate comprising a membrane layer, which comprises a high performance material, using an intermediate adhesive layer; at least partly removing the second substrate, leaving the membrane layer comprising the high performance material; etching the membrane layer to form a membrane at least partly over the pre-fabricated integrated circuit, and to form at least one via hole extending from the first substrate up through the membrane layer; depositing a via material in the via hole forming a via, which connects and supports the membrane with the first substrate; and forming a cavity underneath the membrane.

Optionally the cavity is formed by removing the intermediate adhesive layer, leaving an open cavity underneath the membrane and depositing a first sealing layer onto the first substrate and the membrane to seal the cavity. Optionally the sealing layer is patterned to improve the properties of the membrane and/ or to expose electrical contacts. The sealed cavity may also be provided before the bonding step, using e.g. a sacrificial layer and deposition of a second sealing layer.

Embodiments of the invention are defined in the dependent claims. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings and claims.

Brief description of the drawings

Preferred embodiments of the invention will now be described with reference to the accompanying drawings, wherein

Fig. 1 is a cross sectional view of a general pressure sensor,

Fig. 2 is a cross sectional view of a pressure sensor device according to the invention, Fig. 3 is a cross sectional view of a pressure sensor device according to the invention using a capacitive sensing principle,

Fig. 4 is a process scheme for manufacturing of a pressure sensor device with a sensing electrode according to the present invention,

Fig. 5 is a process scheme for manufacturing of a pressure sensor device with a recessed sensing electrode according to the present invention,

Fig. 6 is a cross-sectional view of an integrated circuit wafer provided with an embedded sensing electrode according to the present invention,

Fig. 7 is a process scheme for bonding a pre-fabricated and hermetically sealed pressure sensor cavity to a pre-fabricated integrated circuit wafer,

Fig. 8 is another process scheme for manufacturing a pressure sensor according to the present invention,

Fig. 9 is process schemes for making either a solid electrical via or a hollow electrical via, and

Fig. 10 is a top view of an integrate device comprising bond pads, a pressure sensor and a flow sensor.

Detailed description of embodiments

Pressure sensors are commonly made using MEMS technology (MicroElectroMechanical Systems) in order to obtain small sensors with high performance and at low cost. The MEMS technology also generally allows a high level of integration, which is important to reduce the cost and the size of the overall system and to enable installation of pressure sensors in all environments. Most pressure sensors micromachined using MEMS technologies are mechanical pressure sensors. However, microphones and related acoustic sensors are basically also pressure sensors. Commonly, a microphone does not have a sealed cavity, but instead use the gas in an open cavity as a damping medium. The following description refers to pressure sensors in general.

For the purpose of this application, the terms wafer and substrate are used interchangeably, the differences between them merely amounting to dimensions thereof.

Component shall be interpreted as any structure that is provided as a subunit on a wafer or substrate, and may comprise entire devices, as well as details of such devices, even a single piece of material.

Adhesive material shall be interpreted as any material or material combination that can be used as an intermediate bonding material when bonding two wafers. The method according to the present invention is particularly suitable for, however not limited to, manufacturing of pressure sensor devices comprising high performance MEMS materials, e.g. high temperature deposited, epitaxial grown or crystalline materials, integrated on an integrated circuit, e.g. a CMOS substrate.

A mechanical pressure sensor 11 is schematically illustrated in Fig. 1. The basic operation principle of the mechanical pressure sensor 11 is to couple an applied pressure 36 to be measured to one surface of a membrane 20 and to measure its deflection 30. To measure the displacement or deflection 30 of the membrane 20 or any other movable object that is subjected to the pressure 36 to be measured different sensing techniques can be utilized. Strain gauges or capacitive sensing is the most common techniques, but for example optical, piezoresistive or piezoelectric sensing mechanisms can also be used. With knowledge of how the applied pressure 36 is related to the deflection 30 of the membrane 20 the applied pressure 36 can be derived from the output signal from the sensor device. As illustrated in Fig. 1 the pressure sensor 11 can be built to measure the applied pressure 36 relative to a pre-defined pressure 37 in a reference pressure cavity 34. The pressure 36 to be measured is applied on a top surface of a membrane 20, which has the reference pressure cavity 34 located between the membrane 20 and a substrate 13. One particular pressure sensor 11 of this kind contains vacuum. Another alternative is to measure the pressure differentially by applying the pressure 36 to be measured on the top surface of the membrane 20 and applying another pressure, e.g. ambient pressure, on the opposite surface of the membrane 20 through a passage in the substrate 13.

As shown in Fig. 2, one embodiment of the integrated device according to the present invention comprises a semiconductor substrate 14 comprising integrated circuits 15 and a membrane 20 of a high performance material, e.g. mono-crystalline silicon, silicon germanium or silicon carbide or polysilicon, that is arranged above the substrate with a gap in between so that integrated circuits 15 in the substrate are at least partly underneath the membrane 20. Distance posts 32 protruding from the semiconductor substrate 14 and through the membrane 20 supports the membrane 20. Optionally a sealing layer (not shown) bridging the gap between the substrate 14 and at least the circumferential of the membrane 20 encapsulates the cavity 34 under the membrane 20, forming an integrated pressure sensor device 10 with a reference pressure cavity 34.

In another embodiment of the present invention according to Fig. 2 the crystalline membrane 20 is made of a high performance material such as polysilicon and the distance posts 32, which are made of electroless plated or electroplated metal or metal alloy, or deposited (e.g. sputtered or evaporated) metal with subsequent patterning of the deposited metal layer, are functional as electrical vias 32, which connects the semiconductor substrate 14 to the membrane 20. Optionally a sealing layer (not shown), e.g. made of silicon nitride, silicon oxide, metal or metal alloy, covers at least partly the membrane 20 and the semiconductor substrate 14. Thereby the cavity 34 is sealed.

As shown in Fig. 3, one embodiment of the present invention comprises a semiconductor substrate 14 consisting of a monolithic integrated circuit and a membrane 20 of a high performance material that is arranged above the substrate 14 with a gap in between so that electronic circuits 15 in the substrate are located at least partly underneath the membrane 20. The substrate is provided with an electrode 25 for sensing and a patterned passivation layer 27. Distance posts 32 protruding from the substrate 14 and through the membrane, supports the membrane. The distance posts 32 are further functional as electrical vias 32. A sealing material 39 arranged around the circumferential of the membrane 20 encapsulates the cavity 34 under the membrane 20, forming a pressure sensor 11 with a reference pressure cavity 34 with a pre-defined pressure therein. Furthermore, the membrane 20 is at least partly doped and is functional as a second electrode 24 and a first electrode 25 is arranged on the semiconductor substrate within the reference pressure cavity 34. Hence the deflection 30 of the membrane 20 due to the applied pressure 36 can be sensed using a capacitive sensing principle.

In one embodiment according to Fig. 3 the membrane 20 is from 0.05 up to 5 μm thick and made of undoped mono-crystalline silicon, the first electrode 25 is made of a metal, such as Al, Au or Cu, and the sealing layer 39 is silicon nitride. The silicon membrane 20 may be coated with a metal layer (not shown) of e.g. Ti or Al, which serves as a second electrode 24 in the capacitive pressure sensor 11.

In one embodiment according to the invention a pressure sensor device 10 comprises a membrane 20 made of mono-crystalline silicon, which comprises at least one integrated resistive sensing element (not shown). This resistive sensing element may have been formed by local doping of the membrane 20.

In another embodiment the membrane comprises at least one transistor element (not shown), which may be used as sensing element.

In another embodiment, the above invention comprises a pressure senor 11 that consist of a thin (0.05-5 μm) membrane 20 made of high temperature deposited/ annealed polycrystalline silicon, optionally with an integrated resistive sensing element (local doping of the membrane). Even transistor structures in the membrane 20 are possible as sensing elements.

In another embodiment of the present invention the substrate comprises electronic circuits 15 such as radio frequency circuits, CMOS based circuits, circuits based on III /V technology, sensor signal read-out circuits, radio communication circuits or a combination of these circuits.

In one embodiment of the present invention the integrated electronic circuits 15 of the substrate 14 are fully underneath the membrane 20. In another embodiment the electronic circuits 15 are partly underneath the membrane 20, e.g. radio communication circuits are located beside the pressure sensor. In both cases the integration of the membrane 20 above the circuits 15 saves space compared with a conventional pressure sensor device where the electrical circuits are located at the side of the membrane or even on another substrate.

In another embodiment according to the present invention the integrated sensor device 10 comprises a pressure senor 11 that contains techniques for temperature compensation of the pressure sensor signals, e.g. a temperature sensor and a temperature compensating circuit in the substrate.

Other sensing principles than capacitive sensing principles, such as piezoelectric sensing principles or piezoresistive sensing principles, however not limited to those, are possible.

In one embodiment according to the present invention the integrated pressure sensor device comprises a membrane made of a high temperature deposited/ annealed piezoelectric material. A signal related to the pressure is generated as the membrane 20 is deflected.

An integrated device according to the present invention may, as disclosed by the above mentioned embodiments show, be varied in terms of design, dimension, materials, etc. Hence, the present invention is not limited to e.g. the specific materials or combination of materials given in the above mentioned embodiments.

As mentioned above, the membrane 20 comprises a high-performance, high temperature (deposited or annealed) or crystalline materials, such as, however not limited to, mono-crystalline and polycrystalline silicon, mono-crystalline silicon germanium (SiGe) or silicon carbide (SiC) or a combination of these materials.

The sealing layer 39 may be selected from numerous materials, partly depending on the choice of materials for e.g. the membrane 20 and the electrical vias 32. Suitable materials for the sealing include, but are not limited to: PECVD silicon nitride, silicon oxide, CVD metal/metal alloy or a combination of these materials. Although the common choice of substrate material 14 is silicon, other semiconductor substrates such as, but not limited to, different III/V materials and silicon-on-insulator (SOI) substrates can be used. Moreover the substrates may be provided with different components, electrodes, contact areas etc.

The present invention provides a method of manufacturing an integrated device 10 that comprises an integrated circuit substrate 14 and a membrane 20 made of a high performance material, i.e. a low-stress, high temperature deposited/ annealed or crystalline material, with an intermediate cavity 34, which optionally is sealed. The membrane may also comprise components such as transistor structures or resistive elements.

A method of manufacturing an integrated device 10 in accordance with one embodiment of the present invention is illustrated in Fig. 4. (a) A first wafer/ substrate 14 comprising a pre-fabricated integrated circuit 15 is optionally provided with a passivation layer 27, contact pads 26 and an electrode 25. The passivation layer 27 is deposited on the first wafer 14 and patterned, e.g. by photolithography and etching, and thereafter a metal or metal alloy is filled into the openings in the passivation layer 27 to form the contact pads 26 and the electrode 25. A second wafer 18 is provided with a sacrificial layer 16, an optional etch stop layer 19 of silicon oxide (SiC^), and a membrane layer 21 comprising a high performance material, e.g. mono -crystalline silicon. The second wafer 18 is provided with an adhesive layer 29, e.g. a polymer, an imprint resist etc. For example, the sacrificial layer 16, the etch stop layer 19, and the membrane layer 21 is made of a silicon-on-insulator (SOI) wafer 18 with a corresponding sacrificial bulk layer of Si, an etch stop layer and a device layer. The adhesive layer 29 is deposited either to any of the two substrates 14, 18 or to both of them. In Fig. 4 the alternative where the adhesive layer 29 is deposited onto the surface of the mono -crystalline silicon is shown, (b) The wafers 14, 18 are then bonded to each other with the passivation layer 27 of the first wafer 14 adjacent the membrane layer 21 of the second wafer 18 using the intermediate adhesive layer 29. (c) After the wafer bonding, the second wafer 18 is at least partly sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the membrane layer 21 (mono- crystalline silicon) on top of the structure with the contact pads 26 and electrodes 25 embedded under the adhesive layer 29. (d) The membrane layer 21 and the adhesive layer 29 are then etched to form e.g. a pressure sensor membrane 20, and via holes 31 extending from the contact pads 26 through the membrane layer/ membrane 20. (e) In those via holes 31, electrical vias 32 are deposited using for example electroless plating or electroplating of a metal or metal alloy, or depositing (e.g. sputtered or evaporated) metal with subsequent patterning of the deposited metal layer, in such way that the electrical vias 32 protrude above the surface of the membrane layer 21 and with a larger diameter than the part of the electrical via 32 embedded in the membrane layer 21. (f) Subsequently, the adhesive layer 29 is selectively removed by wet or dry etching leaving a cavity 34. (g) The cavity 34 is optionally sealed by depositing a sealing layer 29, e.g. polysilicon, PECVD silicon nitride or silicon oxide, covering the top surface of the whole structure and particularly the gap between the membrane 20 and the passivation layer 27 of the first wafer (or the substrate 14, if no passivation layer is used), (h) Optionally the sealing layer 29 is patterned by wet or dry etching so that at least a part of the membrane 20 is exposed. The patterning may lower the membrane stress, enhance the functionality or sensitivity of the device or simply exposes electrical contacts.

In Fig. 5 a method of manufacturing an integrated device 10 with a sealed cavity 34 in accordance with another embodiment of the present invention is schematically illustrated showing cross-sectional views of a portion of a wafer, wherein the portion of the wafer corresponds to one integrated pressure sensor device, (a) A first wafer 14 comprising a pre-fabricated integrated circuit 15 is optionally provided with a passivation layer 27, which is patterned to form openings through the passivation layer 27. A metal or a metal alloy is deposited into a first group of openings so that at least one contact area 26 or electrode 25, which are planar with the passivation layer 27, is formed. A second group of openings are also filled, however to a level below the upper surface of the passivation layer 27, with a metal or metal alloy in the same step as the filling of the first group of openings or in a subsequent step forming a contact area 26 or an electrode 25 for capacitive measurements. The electrode 25 and contact areas 26 may also be formed within the substrate 14 or by other means. A second wafer 18 made of silicon is provided with a sacrificial layer, an etch stop layer 19 of silicon oxide (SiCb), and membrane layer 21 comprising a high performance material, e.g. mono-crystalline silicon, SiC, SiGe or polysilicon. The membrane layer 21 can be un-doped, doped or can comprise different components 23 such as resistors or transistors e.g. obtained by local doping of the layer. An adhesive layer 29 is deposited onto the surface of the membrane layer 21. (b) The wafers 14, 18 are then bonded to each other with the membrane layer in contact with the intermediate adhesive layer 29. (c) After the wafer bonding, the second wafer 18 is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the membrane layer 21 comprising the high performance material (polysilicon) on top of the structure with the contact pads 26 and the electrode 25 embedded under the adhesive layer 29. (d) The membrane layer 21 and the adhesive layer is then etched to form e.g. a pressure sensor membrane 20, and via holes extending from the contact pads 26 through the membrane layer 21. (e) In those via holes 31, electrical vias 32 are deposited using for example electroless plating of a metal or metal alloy, or depositing (e.g. sputtered or evaporated) metal with subsequent patterning of the deposited metal layer, in such way that the electrical vias 32 protrude above the surface of the membrane and with a larger diameter than the part of the electrical via 32 embedded in the membrane layer, (f) Subsequently, the adhesive layer 29 is selectively removed by wet or dry etching leaving a cavity 34. (g) The cavity 34 is optionally sealed by depositing a sealing layer of polysilicon, covering the whole structure and particularly the gap between the membrane 20 and the optional passivation layer 27 of the first wafer 14. (h) Optionally the sealing layer 29 is patterned by lithography and wet or dry etching so that at least a part of the membrane 20 is exposed, e.g. to lower the membrane stress, enhance the functionality or sensitivity of the sensor device or simply to expose contact areas or electrodes. In Fig. 6 a method of manufacturing an integrated device 10 with a sealed cavity in accordance with another embodiment with different treatment of the first wafer 14 is shown, (a) A first wafer 14 comprising a pre-fabricated integrated circuit 15 is provided with a passivation layer 27, which is patterned to form openings through the passivation layer 27. A metal is deposited into a first group of openings so that at least one contact area 26 or electrode 25, which are planar with the passivation layer, is formed. A second group of openings are also filled, however to a level above the upper surface of the passivation layer 27, with a metal forming at least one contact area or an electrode for capacitive measurements, (b) An additional passivation layer 28 is deposited onto the passivation layer 27 and the metal areas 25, 26 so that the surface of the first wafer 14 is planarised. The additional passivation layer 28 is opened, e.g. by lithography and wet or dry etching, above the first group of openings, which are filled with metal. The following processing is performed in analogy with the above described embodiments. In the final structure e.g. a membrane 20 of a capacitive pressure sensor 11 is prevented from electrically short circuiting opposing capacitive electrodes 24, 25.

In Fig. 7 a method of manufacturing an integrated device 10 with a sealed cavity 34 in accordance with yet another embodiment of the present invention is schematically illustrated showing cross-sectional views of a portion of a wafer, (a) A first wafer 14 comprising a pre-fabricated integrated circuit 15 is provided with a passivation layer 27, which is patterned to form openings through the passivation layer 27. A metal is deposited into a first group of openings so that at least one contact area 26 or electrode 25 is formed. A second group of openings are also filled with a metal forming at least one contact area or an electrode for capacitive measurements. The metal filled areas 25, 26 are planar with the passivation layer 27. A second wafer 18 made of silicon is provided with a sacrificial layer 16, an optional etch stop layer 19 of silicon oxide (SiCb), and a membrane layer 21 of a high performance material, e.g. mono-crystalline silicon. A micromachined cavity 34 is formed on the surface of the membrane layer 21 and sealed to provide a cavity 34 with a pre-defined atmosphere, by deposition of a sealing layer 29 made of e.g. polysilicon, PECVD silicon nitride, silicon oxide, high temperature deposited silicon nitride or silicon oxide (e.g. LPCVD silicon nitride or oxide), metal/metal alloy or any combination of such materials, (b) The wafers 14, 18 are then bonded to each other with an intermediate adhesive layer 29. (c) After the wafer bonding, the second wafer 18 is at least partly sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving at least the membrane layer 21 on top of the structure with the contact areas 26 and electrodes 25 embedded under the adhesive layer 29. (d) The membrane layer 21, the sealing layer 39, and the adhesive layer 29 is then etched to form e.g. a pressure sensor membrane 20, and via holes 31 extending from the contact areas 26 through the membrane layer 21. (e) In those via holes 31, electrical vias 32 are deposited using for example electroplating of a metal or metal alloy in such way that the electrical vias 32 protrude above the surface of the membrane layer 21 and with a larger diameter than the part of the electrical via 32 embedded in the membrane layer 21.

In one method according to the present invention a cavity 34 is provided on the membrane layer 21 by the steps of:

- depositing a sacrificial layer 38 adjacent to the membrane layer 21 of the second substrate 18;

- patterning the sacrificial layer 38;

- depositing a layer 40 on the sacrificial layer 38;

- removing the sacrificial layer 38 through etch openings in the layer 40 and thus, creating a cavity 34;

- Optionally sealing the cavity 34 by depositing another sealing layer to close the etch openings through which the sacrificial layer 38 was etched and thus, sealing the cavity 34.

In Fig. 8 a method of manufacturing an integrated device 10 with a sealed cavity 34 in accordance with one embodiment of the present invention is schematically illustrated showing cross-sectional views of a portion of a wafer corresponding to one integrated device. The wafer comprises a plurality of like or similar devices that are processed at the same time, (a) A first wafer 14 comprising a prefabricated integrated circuit 15 is provided with a passivation layer 27, which is patterned and etched to form recesses in the passivation layer 27. At least one metal contact pad 26 and/ or an electrode 25 are formed by depositing metal or metal alloy into the recesses. An additional passivation layer 28 is deposited onto the passivation layer 27 and the metal areas 25, 26. The additional passivation layer 28 is patterned leaving protrusions on each side of the electrode 25, wherein the protrusion located above the contact pad 26 has a hole 31 extending from the contact pad 26. The hole 31 is filled by a metal or metal alloy using e.g. electroless plating so that the metal protrudes above the protrusion forming a plated distance post 32. A second wafer 18 consists of a SOI (silicon-on-insulator) wafer with a sacrificial bulk silicon layer 16, a Siθ2 etch stop layer 19, and a membrane layer 21 made of a high performance material, e.g. mono -crystalline silicon, SiGe, SiC or polysilicon. (b) An adhesive layer 29 is deposited onto the first wafer 14 providing a planar top surface onto which the second wafer 18 is bonded using the intermediate adhesive layer 19. However, the adhesive layer 19 can generally be provided on the first, the second or both wafers 14, 18. (c) At least the bulk silicon layer 16 is removed by lapping or etching. Thereafter the membrane layer 21 is patterned to define a membrane 20 and to open the membrane layer 21 above the plated distance posts 32. Metal is plated or deposited (e.g. sputtered or evaporated) with subsequent patterning of the deposited metal layer to prolong the plated distance posts 32 to above the membrane layer 21 and in such way that the plated material is wider above the membrane layer than within the membrane layer 21, whereby the membrane layer 21 is fixated, (d) The adhesive layer 29 is selectively removed using e.g. dry or wet etching, (e) Finally, a sealing layer is deposited and patterned to form a sealed cavity 34 with a pre-defined reference pressure and a membrane 20 made of a high performance material. In step (a) of Figs. 5 to 8, which have been described above, the first wafer 14 is provided with passivation layers 27, 28 and electrodes 25 or contact areas 26. This wafer is typically a CMOS wafer. CMOS wafer surfaces can have different types of surface structure and materials (metals integrated in the passivation layers, passivation layers on top of the metal, flat surface, surface topography, etc). They may be used as they are provided or different layers or components apart from those mentioned above, i.e. the passivation layers 27, the contact areas 26 and the electrodes 25, may be added on the surface of the wafer 14.

In Fig 9 the process steps (c)-(e) described above are shown in detail to the left. To the right another method to form the plated distance posts 32 in accordance with one embodiment of the present invention is shown. Therein the hole 31 through the membrane layer 21 is not completely filled with the metal. Rather the sidewalls and the periphery of the upper surface of the hole 31 are plated with a layer of metal or coated (e.g. sputtered or evaporated) with a metal layer and subsequently patterning the metal layer (e.g. using lithography in combination with etching techniques).

In Fig. 10 a top view of an integrated device 10 according to the embodiment shown in Fig. 8 is shown. In this embodiment a pressure sensor 11 comprising a square membrane 20 with four plated distance posts 32 and a sealed reference pressure cavity 34 underneath, a flow sensor 12 and two in/ out pads 17 are integrated side by side on a pre-fabricated integrated circuit substrate 14.

A method in accordance with another embodiment of the present invention comprises the steps of:

- adhesively bonding a first wafer 14 comprising integrated circuits 15 to a second wafer 18 comprising a high-performance material, i.e. low-stress, high temperature deposited/ annealed and/or crystalline, film or components, using an intermediate adhesive layer 29 (see US7067345);

- at least partly removing the second wafer 18, and leaving a membrane layer 21 comprising the thin film or components on top of the adhesive layer 29 using e.g. grinding, chemical mechanical polishing, etching or a combination of such techniques, possibly in combination with an etch stop layer 19;

- electrically and/ or mechanically contacting the membrane layer 21 comprising the transferred film or components to the first substrate 14 and/ or to electrical or mechanical contacts 26 on the first substrate 14 (with material deposition techniques and/ or etching techniques);

- removing the intermediate adhesive layer 29;

- creating a cavity 14 underneath the membrane layer 21 comprising the transferred film or components by material deposition inside a controlled pressure atmosphere, e.g. using sputtering, plasma enhanced chemical vapour deposition or other suitable techniques, and thus sealing off the transferred membrane layer 21; and

- optionally, patterning the deposited sealing layer 39 using lithographical and dry or wet etching techniques to enhance the functionality or sensitivity of the components or the accessibility of the electrical contact pads.

In one embodiment of the present invention a sacrificial adhesive layer 29 with a thickness from 0.1 up to 5 μm is used, which results in a cavity 34 height essentially the same as the thickness of the adhesive layer 29.

In another embodiment the membrane layer of transferred thin film or components comprises a mono-crystalline silicon layer, e.g. from a SOI wafer. The silicon layer can be un-doped, doped or can comprise components 23 such as resistors or transistors obtained by local doping of the layer. The silicon layer can also contain metal, e.g. contact pads, or other materials at its surface.

In one embodiment of the invention, again according to Fig. 7, the method of manufacturing an integrated device 10 comprises the steps of:

- manufacturing a cavity 34 with an encapsulated controlled pressure atmosphere that consists of high-performance (low-stress, high temperature deposited/ annealed and/ or crystalline) materials using surface micromachining techniques and high/low temperature deposition and annealing techniques. A first substrate 14 is provided with integrated circuits 15. A second substrate 18 can optionally be a SOI wafer with a thin mono-crystalline silicon device layer; - adhesively bonding the second wafer 18 containing the surface micromachined cavity 34 with the encapsulated controlled pressure atmosphere and the high-performance (low-stress, high temperature deposited/ annealed and/ or crystalline) film or components, to the first wafer containing integrated circuits (see US7067345);

-at least partly removing the substrate wafer 18 and/ or etching holes 31 in the substrate wafer 18 on the membrane areas (with stopping the etch at the etch stop layer), and leaving the thin film or components on top of the adhesive layer 29 on top of the wafer 14 with the integrated circuits 15 using e.g. grinding, etching or a combination, possibly in combination with an etch stop layer 19, e.g. SiCb for Si etching;

- electrically and /or mechanically contacting the transferred film or components with the cavity to the first substrate 14 and/ or to electrical or mechanical contacts on the first substrate 14 using material deposition techniques and/ or etching techniques; and

- optionally removing the intermediate adhesive layer.

In another embodiment of the present invention the method comprises providing the wafer 14 with the integrated circuits 15 with a passivation layer 27, which is an electrical isolator. Optionally the passivation layer 27 can be patterned to expose underlying contact pads 26 or electrodes 25 for capacitive sensing.

In another embodiment of the present invention the method comprises manufacturing of metal pads/surfaces at the wafer surface 14 above the passivation layer 27, and optionally creating an electrical contact to the contacts of the integrated circuits 15 on the wafer.

In another embodiment of the present invention the method comprises using wafers 14 with integrated circuits 15 having a moderate surface topography, i.e. a surface topographies of up to 10 μm.

In another embodiment of the present invention the method comprises planarisation of the surface of the wafer 14 with the integrated circuits 15 by e.g. spin-coating or spray- coating an adhesive bonding layer or a sacrificial layer, e.g. a polymer coating. In another embodiment of the present invention the method comprises using an intermediate adhesive layer 29 for the bonding process on at least one of the wafers to be bonded.

In another embodiment of the present invention the method comprises using patterned distance holding components that define the distance between the transferred films/ components and the surface of the wafer with the integrated electronic circuits.

In another embodiment of the present invention the method comprises using a patterned intermediate adhesive layer with metal bumps on one or both of the substrates to be bonded and creating a metal-to-metal bond at the same time while creating an adhesive bond. Thus, electrical contacts do not need to be manufactured after the sacrificial substrate is removed and the pressure sensor materials are transferred to the wafer with the integrated circuits.

There are several possible alternatives in the processing of the integrated device 10 according to the present invention. The electrical/mechanical vias 32 described above are preferably provided using electroplating or electroless plating of a metal and/ or a metal alloy. Different sealing layer 29 materials are possible and different deposition methods can be used, e.g. poly silicon, PECVD nitride or oxide, high temperature deposited nitride or oxide, metal or any combination of such materials.

The high performance material can optionally compromise components 23 such as integrated resistors or transistors, metal layer or other features.

Components are provided on the first wafer that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. Integrated circuits, radio frequency circuits, radio communication circuits, analogue to digital conversion circuits, signal analysis and processing circuits and other type of circuits and/ or parts of pressure sensors can be implemented on this substrate wafer. The surface of this wafer can contain contact pads or electrode surfaces, see for example Figures 3, 4, 5 and 6, which may be passivated and the upper surface thereof may be located below, above or in level with the wafer surface. The second (sacrificial) wafer 18 may comprise components 23 such as sensors (e.g. pressure sensors), electrical contact lines, integrated circuits or parts of such devices that are made of high-performance (e.g. low-stress, high temperature deposited/ annealed, crystalline) materials. Often this second wafer 18 is made of a SOI wafer.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, on the contrary, is intended to cover various modifications and equivalent arrangements within the appended claims.

Claims

1. An integrated device (10) comprising a pressure sensor (11) having a membrane (20) over a cavity (34) integrated on a semiconductor substrate (14), characterised in that
the membrane (20) comprises a high performance material (21); the semiconductor substrate (14) comprises a integrated circuit (15); the membrane (20) and the cavity (34) are integrated on the semiconductor substrate (14) at least partly over the integrated circuit (15); and
2. An integrated device (10) according to claim 1, wherein the cavity (34) is hermetically sealed.
3. An integrated device (10) according to claim 2, wherein a sealing layer (39) at least partly covers the semiconductor substrate (14) and the membrane (20) to seal the cavity (34).
4. An integrated device (10) according to claim 2, wherein the cavity (34) is enclosed in a layer (40) underneath the membrane (20).
5. An integrated device (10) according to any of the preceding claims, wherein the high performance material (21) is a mono-crystalline material.
6. An integrated device (10) according to claim 5, wherein the mono- crystalline material is selected from silicon, silicon germanium or silicon carbide.
7. An integrated device (10) according to claim any of the preceding claims, wherein the high performance material (21) is polysilicon.
8. An integrated device (10) according to any of the claims 5- 7, wherein the high performance material (21) is at least partly doped.
9. An integrated device (10) according to any of the preceding claims, wherein the membrane (20) comprises a metal or metal alloy film that is adapted to be used as an electrode.
10.An integrated device (10) according to any of claims 5- 9 wherein the membrane (20) is from 0.05 μm up to 5 μm in thickness.
11.An integrated device (10) according to any of the preceding claims, wherein the membrane (20) comprises at least one component (23) such as an integrated resistive element or a transistor.
12.An integrated device (10) according to claim 11, wherein the integrated resistive element comprises a locally doped region in the membrane (20).
13.An integrated device (10) according to any of the preceding claims, wherein the semiconductor substrate (14) comprises a first electrode, the membrane (20) comprises a second electrode, and the first and the second electrode are adapted to be used for capacitive sensing.
14.An integrated device (10) according to any of the claims 1-4, wherein the membrane (20) comprises a high temperature deposited or annealed piezoelectric material adapted to be used for piezoelectric sensing.
15.An integrated device (10) according to any of the claims 1-4, wherein the membrane (20) comprises a piezoresistive element adapted to be used for piezoresistive sensing.
16.An integrated device (10) according to any of the preceding claims, wherein the pre-fabricated integrated circuit (15) comprises circuits selected from radio frequency circuits, CMOS-based circuits, III/V technology based circuits, sensor readout circuits, temperature compensating circuits, and radio communication circuits.
17.An integrated device (10) according to the preceding claims, further comprising a flow sensor (12).
18.A method of manufacturing an integrated device (10) comprising a pressure sensor with a membrane (20) comprising a high performance material (21) integrated on a first substrate (14), comprising the steps of:
- providing a first substrate (14), which comprises a pre-fabricated integrated circuit (15);
- providing a second substrate (18), which comprises a membrane layer (21), wherein the membrane layer (21) further comprises a high performance material;
- bonding the second substrate (18) to the first substrate (14) using an intermediate adhesive layer (29);
- at least partly removing the second substrate (18), leaving the membrane layer (21);
- etching the membrane layer (21) to form the membrane (20) to be located at least partly over the pre-fabricated integrated circuit (15), and to form at least one via hole (31) extending up through the membrane (20);
- depositing a via material in the via hole (31) forming a via (32), which connects the membrane (20) with the first substrate (14); and
- forming a cavity (34) underneath the membrane (20).
19.A method according to claim 18, wherein the step of forming a cavity (34) comprises the steps of:
- removing the intermediate adhesive layer (29), leaving an open cavity (34) underneath the membrane layer (20); and
- depositing a first sealing layer (39) onto the first substrate (14) and the membrane (20) to form a hermetically sealed cavity (34);
20.A method according to claim 19, further comprising patterning of the deposited first sealing layer (39) using lithographical and dry or wet etching techniques.
21. A method according to claim 18, wherein the step of forming a cavity (34) comprises the step of providing a hermetically sealed cavity (34) on the membrane layer (21) of the second substrate (18).
22.A method according to claim 21, wherein the step of providing a cavity (34) comprises the steps of:
- depositing a sacrificial layer (38) adjacent to the layer of membrane layer (21) of the second substrate (18);
- patterning the sacrificial layer (38);
- providing a layer (40), enclosing the sacrificial layer (38); and
- removing the sacrificial layer (38).
23.A method according to any of the claims 18-22, further comprising providing the first substrate (14) with at least one contact area (26) and/ or electrode (25) and/ or passivation layer (27).
24.A method according to any of the claims 18-22, further comprising providing the layer of the membrane layer (21) with components (23) such as integrated resistive elements or transistor structures for sensing.
25.A method according to any of the claims 18-22, comprising using an intermediate adhesive layer (29) with a thickness from 0.1 μm up to 5 μm.
26.A method according to claim any of the claims 18-22, wherein the high performance material is a mono-crystalline material selected from silicon, silicon germanium or silicon carbide silicon.
27.A method according to any of the claims 18-22, wherein the high performance material (21) is polysilicon.
28.A method according to claim 26 or 27, wherein the high performance material (21) is at least partly doped.
PCT/SE2007/000337 2006-04-07 2007-04-05 Microelectromechanical pressure sensor with integrated circuit and method of manufacturing such WO2007117198A1 (en)

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