WO2007116335A2 - Data processing circuit and a method with erasure based error correction of a deinterleaved signal - Google Patents

Abstract

A series of data symbols is received. Unreliable units in the series of data symbols are detected on a per unit basis. A block of the data symbols that comprises a plurality of units is stored in a memory for de-interleaving. The information about unreliability has been found to have more redundancy than the data symbols. This used to reduce the amount of information stored for de-interleaving. Respective compressed reliability symbols are formed for successive parts of the series during reception of the series, using compressive coding of combinations of reliability information for respective ones of the units. The data symbols of the block are read from the memory in a de-interleaved order. The compressed reliability symbols are decompressed out of order, according to the de- interleaved order, in combination with said reading according to the de-interleaved order.

Description

Data processing circuit and a method with erasure based error correction of a deinterleaved signal

The invention relates to a data processing circuit and a method of processing data. In particular embodiments a data processing circuit and a method are an error correction circuit and method and a receiver circuit and method.

US patent No 6,564,343 describes a circuit and method for receiving bits, de- interleaving the bits and using the de-interleaved bits for error correction. As is well known de-interleaving involves reordering of serially received bits, typically followed by the application of error correction to the reordered bits. The error correction applies to codewords that contain bits that are successive in the reordered sequence of bits. De-interleaving has the effect that bits from bursts of successive errors are distributed over different codewords, so that the number of errors per code word does not exceed the correction capacity of the error correction.

US patent No 6,564,343 also describes the use of an inhibit signal that indicates bits (symbols) that were received with low signal strength. The inhibit signal serves to improve error correction, by acting as an "erasure" signal as known from error correcting decoding. During error correction erased bits (symbols) are ignored. This has the effect that more errors can be corrected than if these bits (symbols) are treated in the same way as the remaining bits (symbols). Of course, when the received bits (symbols) are de-interleaved, a corresponding de-interleaving-like operation has to be applied to the erasure signal, in order to be able to identify the erased bits (symbols) after de-interleaving.

US patent No 6,564,343 describes the use of a memory to implement de- interleaving. The memory is organized as a matrix of rows and columns (this organization may coincide with a circuit structure of rows and columns, but this is not necessary).

Received bits (symbols) and bits of the erasure signal are written into the memory row after row. Subsequently the received bits (symbols) and bits of the erasure signal are written column after column successively in a row. Thus the order in which the bits (symbols) are read out differs from the order of writing, with the effect that the bits are interleaved.

In practice, a memory of considerable size will often be needed for storing the received bits (symbols) and the bits of the erasure signal.

Among others, it is an object of the invention to reduce the size of memory needed to store the received symbols and the information about reliability of the symbols for used as erasure signal. According to one aspect information that represents sections of unreliable data symbols in the stream is compressed before storage and decompressed upon reading. This is based on the insight that the reliability information for data symbols has a high redundancy, in contrast to the data symbols themselves. Hence, although little or no memory space can be saved by compressing the data symbols, a more relevant memory reduction can be gained by compressing the reliability information. Preferably, the data symbols are not compressed together with the reliability information to avoid redundant compression and decompression. In an embodiment a receiver is provided that comprises a compression circuit configured to form respective compressed reliability symbols for successive parts of a series of data symbols that are applied to a de-interleaver. The compression circuit receives input from as detector that detects units of unreliable data symbols in the series. Units of detection of unreliability may be individual data symbols, or blocks with a plurality of data symbols (for example a block that corresponds to codewords in an error correcting code that is used to pre-process the data symbols etc.). The units may have fixed or variable size. The compression circuit compresses the reliability information by combining reliability information for different units if possible. In one example, a run- length code is used to realize compression. When the data symbols are retrieved in de-interleaved order the reliability symbols are decompressed in a different order than the one in which they where compressed.

In an embodiment a decompression circuit is provided with storage locations wherein parallel decompression information for a plurality of reading positions is maintained. Thus for example during matrix de-interleaving wherein data symbols are read a row at a time (after being written a column at a time) decompression information is kept in parallel for respective positions in a row. In the case of run length compression the decompression information may comprise remaining lengths of runs for different positions in the row. In a further embodiment the compression circuit is configured to store starting information for decompression of the reliability information for different reading positions, for example each time when it stores a data symbol that will form the start of a next column. In this way decompression can start without preparatory decompression actions.

These and other objects and advantages will be come apparent from a description of exemplary embodiments using the following Figures:

Fig. 1 shows a receiver circuit; Figs. 2a,b shows a matrix wherein data symbols are arranged;

Fig. 3 shows a stream of data symbols;

Fig. 4 shows a memory layout for reliability information;

Fig. 5 flow chart of a read-out process;

Fig. 6 shows a parallel reliability information regeneration circuit.

Fig. 1 shows a receiver circuit with units 12, 14, 16, 18 coupled in series between a signal input 10 and a signal output 19. The units are typically implemented as respective circuits, optionally programmable circuits programmed to perform required processing, but optionally some of the units may be implemented with a same circuit, which performs the functions of different units at different times. A front unit 12, which may comprise a plurality of sub-units, is configured to receive signals from signal input 10 and has a signal output 10a for producing a stream of received data symbols and a reliability output 10b for supplying information indicating a reliability of the data symbols. In one embodiment each symbol is a bit of data, but in other embodiment each symbol may be an n- bit word, with n=8 or n=16 for example.

A second unit 14 is a de-interleaving unit 14. De-interleaving unit 14 comprises a de-interleaving memory 140, an addressing circuit 142, a run length encoder 144, a reliability information memory 146 and a read-out circuit 148. Addressing circuit 142 and signal output 10a of front unit 12 are coupled to de-interleaving memory 140. Reliability output 10b of front unit 12 is coupled to reliability information memory 146 via run length encoder 144. Read-out circuit 148 is coupled to de- interleaving memory 140 and reliability information memory 146. A third unit 16 is an error correcting decoding unit, which has inputs coupled to read-out circuit 148. In operation front unit 12 receives an input signal at signal input 10, for example from an antenna (not shown) and decodes data symbols from the input signal. In an embodiment decoding involves one or more stages of error correction, such as error correction according to a convolution code followed by error correction according to a block code. In an embodiment front unit 12 outputs a stream of decoded data symbols, in a sequence that substantially corresponds to a sequence of reception of signal parts that encode the symbols at signal input 10, data symbols being output later if they derive from later signal parts.

Front unit 12 also comprises a detector 120 that determines a reliability of the decoded data symbols. In an embodiment wherein error correction according to a block code is used, for example, the detector of front unit 12 may indicate a block of data symbols as unreliable if more than a threshold number of errors is detected in the block. In other embodiments the detector may use information about the signal strength of the input signal at signal input 10, or detection of interfering signals to determine the reliability of data signals. Typically, each item of reliability information applies equally to a respective group of symbols from the stream of successive symbols output by front unit 12. In the embodiment wherein the symbols are obtained from block based error correction, for example, each item of reliability information applies to a respective block. In the embodiment wherein the reliability information is derived from signal strength or the presence of interfering signals, for example, each item of reliability information may apply to all symbols derived from a time interval for which such conditions are detected.

The data symbols are stored successively in de-interleaving memory 140, at a sequence of addresses determined by addressing circuit 142. On read-out data symbols are read-out of de-interleaving memory in a sequence that differs from the sequence in which the data items are written, by using a different address sequence for read out. This has the effect that data items that are close to each other in the incoming stream are moved apart from each other. Various addressing schemes may be used to realize this.

Figs. 2a and 2b show a conceptual matrix of data symbols that may be used in the case of matrix de-interleaving. By way of example successive data symbols being written at column by column, as indicated by arrows 20, the data symbols being written into locations in successive rows in a current column until the current column is full, after which data symbols are written into the next column. Thus, in the write in process has successive stages, each stage involving a respective column. In the case of matrix de-interleaving the data symbols are subsequently read out row by row, as indicated by arrows 22, the data symbols being read from locations in successive columns in a current row until the current row has been fully read, after which data symbols read from the next row and so on. Thus, in the read out process has successive stages, each stage involving a respective row.

Addressing to implement such a conceptual matrix can be realized in various ways. For example each column of the matrix may be taken to correspond to a respective series of memory locations with successive addresses, successive columns having successive series of addresses. In such an embodiment addressing circuit 142 increments the addresses for successive symbols in the stream by one symbol location each time when a next symbol from symbol output 10a is stored. Alternatively, each row may be taken to correspond to a respective series of memory locations. In this case, addressing circuit 142 increments the address with a stride value that corresponds to the address distance between successive rows each time when a next symbol from symbol output 10a is stored, a next address from the first row being used each time when a whole column has been written. If the row or column address range is a power of two, this can be easily implemented by incrementing a binary counter upon reception of successive symbols and using part of the bits of the counter to form a row address and another part to form a column address. However, it should be emphasized that many other forms of addressing, and allocation of addresses may be used to implement matrix de-interleaving and that other forms of de-interleaving than matrix de-interleaving may be implemented, by using other address sequences. Run length encoder 144 receives the information that indicates the reliability and encodes this information as a series of length values, each length value indicating a length of a section of the stream of symbols that has have same reliability.

Fig. 3 illustrates a stream of data symbols as a function of time, sections 30 of unreliable symbols being indicated by shading and leading, following and intermediate sections 32 of reliable symbols being indicated without shading. Corresponding locations of unreliable symbols in the de-interleaving matrix are indicated by shading in Fig. 2. Run length encoder 144 stores the length values in reliability information memory 146, in combination with information from which the reliability can be derived for each section. Run length encoder 144 may be implemented for example as a suitably programmed micro processing circuit, or as a dedicated hardware circuit.

In an embodiment run length encoder 144 is configured to detect locations 34 in the data stream where successive columns start. In this embodiment run length encoder 144 also records indications of the locations of the length values for first sections in the respective columns. In one embodiment, run length encoder 144 breaks sections that span from one column to another, recording separate length codes for the parts of these sections. In other embodiment run length encoder 144 records for each column a location of last length of the section up to the data symbol at the start of the column.

Fig. 4 shows an example of information recorded in reliability information memory 146. In this embodiment reliability information memory 146 comprises a first area 40 with length values of sections of data symbols in de-interleaving memory 140. Reliability information memory 146 comprises second, third and fourth area's 42, 44, 46 for respective ones of the columns, the second area 42 for a column storing an indication of the reliability of a first symbol in the column, the third area 44 for the column storing a pointer to a location where a length of a first start of a section in the column is stored in first area 40 and the fourth area 46 storing a number Nc indicating the number of symbols from the start of the column up to the start of the first section. Read-out circuit 148 reads data symbols from de- interleaving memory 140 in de-interleaved sequence. For example, in the case of matrix de- interleaving and when data symbols have been stored column-by-column, read-out circuit 148 reads out symbols row by row as indicated by arrows 22. Read-out circuit 148 also regenerates reliability information for the data symbols from run length values from reliability information memory 146.

Fig. 5 shows a flow-chart of operation of an embodiment of read-out circuit 148 for regenerating the reliability information for a row of data symbols. In a first step 51 read-out circuit 148 initializes a column counter to a first column in the row. In a second step 52 read-out circuit 148 reads out a data item for the column in the current row from de- interleaving memory 140 and uses the column counter to read out the reliability information from the second area 42 for the column and associates this reliability with the data item. In a third step 53 read-out circuit 148 tests whether the whole row has been processed. If not, read-out circuit 148 executes a fourth step 54, updating the column counter before repeating from second step 52.

If on third step 53 a whole row has been processed, read-out circuit 148 executes an update step 55 before returning to first step 51 for a next row. Update step 55 first executes a first sub-step 551 initializing a column counter to a first column. In a second sub-step 552 read-out circuit 148 tests whether a number Nc of remaining symbols for the column, stored in fourth area 46 is zero. If not read-out circuit 148 executes a third sub-step 553 decrementing the number Nc in fourth area 46. If the number was zero, read-out circuit 148 executes a fourth sub-step 554, wherein the pointer from third area 44 for the column is used to retrieve a next length value from first area 40. Read-out circuit 148 stores this value in the fourth area 46 for the column, as a new value for Nc. Read-out circuit 148 then increments the pointer in third area 44 for the column and updates the reliability information in the second area 42 for the column. After third or fourth sub-step 553, 554 read-out circuit 148 executes a fifth sub-step 555 testing whether information for all columns has been updated. If not read-out circuit 148 executes a sixth sub-step 556 incrementing the column counter and repeating from second sub-step 552. When the information for all columns has been updated the update is complete and read-out circuit 148 repeats from first step 51 for a next row. Read out circuit 148 may be implemented for example as a suitably programmed micro processing circuit, or as a dedicated hardware circuit. Read-out circuit supplies the data symbols with corresponding reliability information to the error correcting decoding unit 16, which uses the reliability information for example to ignore symbols that are indicated as unreliable during the computation of error corrections. Techniques for doing this are known per se and will therefore not be described here. From error correcting decoding unit 16 the data is supplied to fourth unit 18.

In one embodiment this unit performs video decompression to control rendering of video information dependent on the data. In other embodiments other use may be made of the data.

It will be appreciated that the method of re-generating the reliability information that has been illustrated in connection with Fig. 5 is merely one example. For example, in another embodiment the update step 55 may be integrated with the steps for retrieval of reliability information. As another example, searches in first area 40 may be performed for each column instead of using information stored for respective columns in second, third and fourth area's 42, 44, 46. However, the use of pre-stored information per column has the advantage that much faster generation of reliability information is possible. But even in this case not all described information need be stored for each column.

In the illustrated embodiment first area 40 stores length values for successive sections successively. This has the effect that there are no reserved areas for respective columns. When more than an average number of sections occur in a column, storage the length codes for these sections may be stored in storage space that becomes available because the number of sections in another column is below the average number of sections. In this way a smaller first area 40 suffices. In an embodiment a fixed size first area 40 is used, with a size that is smaller than necessary for the maximum number of possible length codes. In this embodiment all data in the de-interleaving matrix is marked unreliable if more length codes would be needed to store them than can be accommodated in first area 40. The size of first area is preferably selected to that this occurs only if the number of unreliable sections is so large that the matrix is useless for further processing in any case.

In an alternative embodiment, predetermined (data independent) sub-areas are reserved in first area 40 for respective columns. In this case pointer information to retrieve the data for the columns may be omitted. However, in this case a larger first area is needed, because the size of each sub-areas has to be larger than the average area needed for each column, to accommodate for fluctuations in the number of length values per individual column. In this alternative embodiment run length encoder 144 preferably breaks sections of symbols that run over from one column to another into separate sections, so that each column starts with a start of a section.

In one embodiment front unit 12 is configured to produce blocks of data symbols of predetermined size and to indicate reliability per block, so that the length of a section of unreliable symbols is always an integer multiple of blocks. In this case, the length codes may be designed to indicate a number of blocks. In another embodiment, variable sized blocks may be used. In this case length values of higher resolution, possibly a per symbol resolution may be needed.

In an embodiment the reliability information is allowed to assume one of two values for each section, corresponding to reliable and unreliable data. In this embodiment an initial value of the reliability information suffices to regenerate reliability information for all symbols, because the reliability information toggles back and forth between sections. In the embodiment where pointers are used to the length code, preferably run length encoder 144 stores initial values per column to enable regeneration without access to other columns.

In another embodiment the reliability information may be selected from more than two values (e.g. from four values) to indicate a degree of unreliability. In this case reliability values for sections are preferably stored in association with the lengths of the sections.

In an embodiment length values of sections are stored only for sections that contain reliable data, a unit length section of unreliable symbols (for example a block of data from an error correcting decoder in front unit 12) being assumed to lie between the sections of reliable data. In this embodiment a special code (such as a length code for zero length) is used when more than one unreliable unit length section occurs successively. In the case where unreliable data occurs infrequently, this may reduce the amount of memory needed to store the length values. More generally a variable length code that is optimized to minimize the average amount of data to represent length values may be used to represent stored length values. Optionally different variable length codes may be used for lengths of unreliable sections and lengths of reliable sections.

Fig. 6 shows an embodiment of a reliability generating circuit. The circuit comprises a plurality of units 60, one for each column. Each unit comprises a shift register 62, a counter 64, a control circuit 66 and an output register 68. Shift register 62 has an output coupled to an input of counter 64, which has an output coupled to control circuit 66. Control circuit 66 has outputs coupled to shift register 62, counter 64 and output register 68. Output register 68 has an output for supplying a reliability value.

In operation, run length encoder 144 loads length of an initial section in a column into counter 64. Run length encoder 144 sets the output register according to the reliability information for the symbol in the first row of the column. Run length encoder 144 loads length values of the subsequent sections of symbols in a column into the shift register 62 for the column, length values further down the column being loaded into positions increasingly further from the output of shift register 62. Upon output, each time when a next row is processed the counters 64 in all units 60 are decremented. Control circuit 66 detects whether the counter has reached zero. If so, control circuit toggles the value in output register 68, causes counter 64 to load a next value from shift register 62 and makes shift register 62 shift the lengths by one step towards the output of shift register 62.

As will appreciated this circuit provides for the output of a plurality of reliability values for a plurality of columns in parallel. In this embodiment preferably de- interleaving memory 140 is configured to output the data symbols for the plurality of columns in parallel. This supports an error correcting decoding unit 16 that is configured to operate symbols from the plurality of columns in parallel. In an embodiment wherein the reliability information can assume more that two values, these values are also stored in shift register 62 and loaded into output register 68 from shift register 62 when counter 64 has reached zero.

Although an embodiment has been described wherein run length coding (and optionally run length- value coding) is used, it should be appreciated that other forms of compressing and decompressing the reliability information could be used. For example, a variable length code could be used to represent vectors of reliability bits for respective columns. When the sections of unreliable symbols are likely to occur in repeating patterns, forms of compression that exploit such patterns may be used (for example by coding a repeating part of the unreliability information in terms of a displacement vector with respect to another part). However, due to the nature of sources of unreliability in general the least memory will be needed if some form of run- length coding is used.

CLAIMS:

1. A receiver comprising: an input (10); an input circuit (12) configured to obtain a series of data symbols from a signal at the input (10); - a de-interleaving circuit (14) configured to de-interleave the series of data symbols; a detector (120) configured to detect unreliable units in the series of data symbols on a per unit basis before de-interleaving; a compression circuit (144) configured to form and store respective compressed reliability symbols for successive parts of the series, using compressive coding of combinations of reliability information for different ones of the units; a decompression circuit (148) configured to decompress the compressed the stored reliability symbols out of order, in an order determined by de-interleaved output of the data symbols.

2. A receiver according to claim 1, wherein the de-interleaving circuit (14) is configured to output the data symbols in a succession of stages of operation, each stage comprising outputting data symbols from a respective set of at least partly not mutually successive positions in the series, the respective sets for successive stages having at least partly corresponding positions that succeed each other in the series from one stage to another; and wherein the receiver comprises storage locations (146), the decompression circuit (148) being configured to maintain parallel decompression information for a plurality of said corresponding positions from a respective set in said storage locations and to update and reuse the parallel decompression information in said storage locations for successive ones of said stages.

3. A receiver according to claim 2, wherein the compression circuit (144, 146) is configured to store respective items of starting information for use to determine initial values

Claims

for said parallel compression information for respective ones of said at least part of the positions during said forming of respective compressed reliability symbols.

4. A receiver according to claim 1, wherein said compressive coding is run- length coding.

5. A receiver according to claim 4, wherein the de-interleaving circuit (14) is configured to output the data symbols in a succession of stages of operation, each stage comprising outputting data symbols from a respective set of at least partly not mutually successive positions in the series, the respective sets for successive stages having at least partly corresponding positions that succeed each other in the series from one stage to another; and wherein the receiver comprises storage locations (146), the decompression circuit (148) being configured to maintain remaining length information for respective runs at said at least part of the positions in the storage locations (146); to update the remaining length information for said at least part of the positions for successive ones of said stages for the decompression in the storage locations (146) and to replace the remaining length information for each position in the storage locations (146) by length information for a next run at said position when the remaining length for that position becomes zero.

6. A receiver according to claim 5, wherein the decompression circuit (148) is configured to maintain for each of said at least part of the positions a reliability value and a remaining length value in said storage locations (146).

7. A receiver according to claim 6, wherein the decompression circuit (148) is configured to maintain for each of said at least part of the positions a pointer to a next length value for that position in a pool (40) of length values for the block in said storage locations (146).

8. A receiver according to claim 5, comprising a plurality of decompression circuits (60), each comprising a shift register (62), a counter (64) and a control circuit (66), the counter (64) being configured to count down on successive ones of the stages, the control circuit (66) being configured to cause a length value to be loaded from the shift register (62) into the counter (64) and to shift length values through the shift register (62) when the counter (64) reaches zero.

9. An error correction method, the method comprising: supplying a series of data symbols; detecting unreliable units in the series of data symbols on a per unit basis; - storing a block of the data symbols that comprises a plurality of units in a memory; forming respective compressed reliability symbols for successive parts of the series during reception of the series, using compressive coding of combinations of reliability information for respective ones of the units; - reading the data symbols of the block from the memory in a de-interleaved order; decompressing the compressed reliability symbols out of order, according to the de-interleaved order in combination with said reading according to the de-interleaved order.

10. An error correction method according to claim 9, wherein said reading in de- interleaved order comprises a succession of stages, each stage comprising outputting data symbols from a respective set of at least partly not mutually successive positions in the series, the respective sets for successive stages having at least partly corresponding positions that succeed each other in the series from one stage to another; the method comprising: maintaining parallel decompression information for a plurality of said corresponding positions; updating and reusing the parallel decompression information from stage to stage for the decompression.

11. An error correction method according to claim 9, wherein said compressive coding is run-length coding.