WO2007109225A2 - Générateur d'horloge et procédé de génération d'horloge utilisant une boucle à verrouillage de retard - Google Patents

Générateur d'horloge et procédé de génération d'horloge utilisant une boucle à verrouillage de retard Download PDF

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Publication number
WO2007109225A2
WO2007109225A2 PCT/US2007/006800 US2007006800W WO2007109225A2 WO 2007109225 A2 WO2007109225 A2 WO 2007109225A2 US 2007006800 W US2007006800 W US 2007006800W WO 2007109225 A2 WO2007109225 A2 WO 2007109225A2
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WO
WIPO (PCT)
Prior art keywords
clock signal
frequency
clock
oscillator
signals
Prior art date
Application number
PCT/US2007/006800
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English (en)
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WO2007109225A3 (fr
Inventor
Joonbae Park
Kyeongho Lee
Original Assignee
Gct Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060024677A external-priority patent/KR100710127B1/ko
Application filed by Gct Semiconductor, Inc. filed Critical Gct Semiconductor, Inc.
Publication of WO2007109225A2 publication Critical patent/WO2007109225A2/fr
Publication of WO2007109225A3 publication Critical patent/WO2007109225A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path

Definitions

  • the present invention relates to a clock generator and a clock generating method.
  • a clock generator has been widely used to provide a microprocessor, a digital signal processor, an integration circuit and the like with a system clock.
  • a clock generator using a phase locked loop (PLL) has been often used as a related art clock generator.
  • the PLL clock generator generally includes a phase detector for detecting a phase difference between a clock signal provided by a frequency generator and a clock signal outputted from a frequency divider, a loop filter, a voltage controlled oscillator and a frequency divider.
  • the loop filter is for removing a high frequency component from the phase difference detected by the phase detector, and the voltage controlled oscillator is for changing a frequency of an output clock signal according to the phase difference outputted by the loop filter.
  • the frequency divider is for dividing the frequency of the output clock signal by N (e.g., N is a natural number) to output the divided output clock signal.
  • N is a natural number
  • Such a PLL clock generator has advantages including the frequency of the output clock signal is N times that of the input clock signal by including the frequency divider. Further, the frequency divider can be implemented by using a counter so that the implementation of the frequency divider is simple and the N value may be easily changed.
  • there are also disadvantages including at least that a restored clock signal has an increased phase noise because the voltage controlled oscillator of the PLL clock generator employs a positive feed back circuit. Further, the phase noise is seriously increased if a noise of a supply voltage increases.
  • a delay locked loop (DLL) clock generator can include a phase detector for detecting a phase difference between a clock signal provided by a frequency generator and a clock signal outputted from a voltage controlled delay- line, a loop filter and a voltage controlled delay line.
  • the loop filter is for removing a high frequency component from the phase difference detected by the phase detector
  • the voltage controlled delay line is for changing a delay of an input clock signal according to the phase difference outputted by the loop filter to generate an output clock signal. Since such a DLL clock generator does not include a voltage controlled oscillator, the DLL clock generator includes advantages in that the above-described disadvantages occurring in the PLL clock generator can be reduced or prevented.
  • disadvantages of the DLL clock generator include the DLL clock generator can generate only an output clock signal having the same frequency as that of the clock signal provided by the frequency generator.
  • USPN 6,784,707 discloses a conventional DLL clock generator that addressed the above- described disadvantages by including a frequency multiplier for outputting a clock signal having a frequency that is N/2 times that of a clock signal transmitted from a frequency divider by using a plurality of clock signals.
  • the plurality of clock signals are outputted from a voltage controlled delay line and each clock signal has a different delay.
  • N means the number of delay cells included in the voltage controlled delay line.
  • USPN 6,784,707 has disadvantages because N delay cells are required to obtain a frequency of N/2-tuple and the number of transistors included in the frequency multiplier has to be increased in proportion to N. That is, the complexity of the frequency divider of the PLL clock generator increases approximately in proportion to log2N and the complexity of the frequency multiplier disclosed in USPN 6,784,707 also increases in proportion to N. Therefore, one drawback in the frequency generator of USPN 6,784,707 is a large number of transistors are required to make a variety of frequencies. [0004] The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
  • FIG. 1 is a diagram of a DLL clock generator in accordance with an embodiment of the application;
  • FIG. 2 shows a diagram of an embodiment of a delay locked loop having a frequency multiply function employed in a clock generator shown in FIG.
  • FIG. 3 illustrates an embodiment of a voltage controlled delay line employed in the delay locked loop shown in FIG. 2;
  • FIG. 4 shows an embodiment of a frequency multiplier employed in the delay locked loop shown in FIG.2;
  • FIG. 5 provides a diagram displaying each signal shown in FIG.4; and [0011]
  • FIG. 6 is a diagram showing another embodiment of a frequency multiplier employed in the delay locked loop shown, in FIG. 2.
  • Embodiments according to the application can provide a clock generator or clock generating method.
  • Embodiments according to the application can provide a clock generator or clock generating method using a DLL delay lock loop (DLL).
  • DLL delay lock loop
  • Embodiments according to the application can provide a clock generator or clock generating method using a DLL delay lock loop (DLL) that can solve disadvantages of the related or conventional art.
  • Embodiments according to the application can provide a DLL clock generator and a DLL clock generating method that can be less affected by a phase noise of an input voltage without using a voltage controlled oscillator.
  • DLL delay lock loop
  • Embodiments according to the application can provide a DLL clock generator and a DLL clock generating method capable of generating clock signals having frequencies that are various and accurate without increasing the complexity of hardware.
  • a clock generator including: a first crystal oscillator for generating a first clock signal having a frequency corresponding to a control signal; a delay locked loop having a frequency multiply function for generating a second clock signal having a frequency higher than that of the first clock signal by using the first clock signal; a frequency divider for generating a third clock signal having a frequency lower than that of the second clock signal by using the second clock signal; a second crystal oscillator for generating a fourth clock signal; and a phase frequency detector for generating the control signal corresponding to a phase difference and a frequency difference between the third clock signal and the fourth clock signal.
  • clock generating method including the steps of:
  • FIG. 1 is a diagram of a DLL clock generator in accordance with an embodiment of the application.
  • the clock generator can include a first oscillator XoI (e.g., a first crystal oscillator); a delay locked loop 100 having a frequency multiplier function; a frequency divider 200; a second oscillator
  • Xo2 e.g., a second crystal oscillator
  • phase frequency detector 300 e.g., a phase frequency detector
  • the first crystal oscillator XoI can generate a first clock signal Cxol having a frequency corresponding to a control signal Ctrl.
  • a dynamic frequency range of the first crystal oscillator XoI can be wider than that of the second crystal oscillator Xo2.
  • the first crystal oscillator XoI may be a digitally controlled crystal oscillator for changing the frequency of the first clock signal Cxol according to a digital control signal Ctrl, or a voltage controlled crystal oscillator for changing the frequency of the first clock signal Cxol according to an analog control signal Ctrl.
  • the frequency of the first clock signal Cxol is 10 times or more that of a fourth clock signal Cxo2.
  • the delay locked loop 100 having a frequency multiply function can generate a second clock signal Cout having a frequency higher than that of the first clock signal Cxol by using the first clock signal Cxol.
  • the second clock signal Cout can be an output clock signal that the DLL clock generator wants to obtain.
  • the frequency of the second clock signal Cout is M times that of the first clock signal.
  • M can be a programmable value. For example, if the delay locked loop 100 includes the frequency multiplier disclosed in USPN 6,784,707, M may have a value corresponding to N/2, where N means the number of delay cells.
  • the frequency divider 200 can generate a third clock signal Cdiv having a frequency lower than that of the second clock signal Cout by using the second clock signal Cout.
  • the frequency of the third clock signal Cdiv can be equal to a value corresponding to the second clock signal frequency divided by K.
  • K can be a programmable value.
  • the frequency divider 200 may be implemented by using, for example, a counter (not shown), and K preferably is a natural number.
  • the second crystal oscillator Xo2 can generate the fourth clock signal Cxo2.
  • the second crystal oscillator Xo2 may be a temperature compensated crystal oscillator for preventing (or reducing a possibility that) a frequency of the fourth clock signal Cxo2 from being changed according to temperature.
  • the phase frequency detector 300 can generate the control signal Ctrl corresponding to a phase difference and a frequency difference between the third clock signal Cdiv and the fourth clock signal Cxo2.
  • the DLL clock generator employing the above-described configuration in accordance with one embodiment of the application has advantages including the second clock signal Cout, e.g., output signal, having a variety of frequencies can be generated without increasing the hardware size (e.g., in comparison with a clock generator disclosed in USPN 6,784,707).
  • the 425MHz clock signal and the 601MHz clock signal may be generated by using a delay locked loop including 12 delay cells and a frequency oscillator of IMHz.
  • a large number of delay cells have to be included in such a configuration, so that the complexity of hardware increases remarkably.
  • the 425MHz clock signal and the 601MHz clock signal can also be generated by using a delay locked loop including 12 delay cells and a frequency oscillator having a dynamic range from IQOMHz to HOMHz.
  • the frequency of the generated clock signal has an inaccurate value because it is difficult to set the output frequency of the frequency oscillator to 425MHz/4 or 601MHz/6 exactly.
  • the first crystal oscillator XoI having the dynamic range from 100MHz to HOMHz and the second crystal oscillator Xo2 capable of outputting an exact clock signal of IMHz.
  • the frequency of the first clock signal Cxol can automatically become 425MHz/4 according to the control signal Ctrl, so that the output clock signal, e.g., the second clock signal Cout, can have the frequency of 425MHz.
  • the frequency of the first clock signal Cxol can automatically become 601MHz/6 according to the control signal Ctrl, so that the output clock signal, e.g., the second clock signal Cout, can have the frequency of 601MHz. Since M has an upper value or the maximum value 6, the complexity of the delay locked loop scarcely increases. Moreover, the accuracy of the frequency of the second clock signal Cout can be maintained by using the second crystal oscillator that is capable of providing an accurate frequency.
  • the clock generator since the clock generator according to one embodiment employs the first crystal oscillator XoI having a "wide dynamic range and the second crystal oscillator having an accurate frequency, it is possible to obtain an output signal capable of meeting a wide dynamic range and an accurate frequency at the same time.
  • embodiments of a clock generator according to the application have advantages including that the accuracy of the frequency of the output clock signal, e.g., the second clock signal Cout, can be maintained by the second crystal oscillator Xo2 capable of providing an accurate frequency.
  • the frequency of the second clock signal Cout can have a value that is K times the frequency of the fourth clock signal Cxo2 outputted from the second crystal oscillator Xo2 by using a closed loop control. Since the second crystal oscillator Xo2 can provide the fourth clock signal Cxo2 having an accurate frequency, the second clock signal Cout can also have an accurate frequency that is K times that of the fourth clock signal.
  • the output clock signal e.g., the second clock signal
  • the output clock signal has a wide dynamic range.
  • the first crystal oscillator XoI having a dynamic range from 100 to HOMHz and the delay locked loop 100 capable of multiplying a frequency by 10 to 50 times may be used.
  • the second clock signal Cout having a frequency from 1.0 to 1.1GHz can be obtained by setting M to 10.
  • the frequency of the fourth clock signal Cxo2 generated by the second crystal oscillator XO2 is IMHz
  • the frequency of the second clock signal Cout becomes 1.000GHz in case of setting K of the frequency- divider 200 to 1000.
  • the frequency of the second clock signal Cout can become 1.001GHz in case of setting K to 1001, and the frequency of the second clock signal Cout can become 1.100GHz in case of setting K to 1100.
  • the second clock signal Cout having the dynamic range from 1.0 to 1.1GHZ can be obtained, for example, while changing the second clock signal frequency according to K.
  • M is set to 11
  • the second clock signal Cout having the dynamic range from 1.1 to 1.2GHZ may be obtained, for example, while changing the second clock signal frequency according to K.
  • the second clock signal Cout having the dynamic range When M is set to 49, the second clock signal Cout having the dynamic range from 4.9 to 5. OGHZ may be obtained, for example, changing the second clock signal frequency according to K. As described above, it is possible to obtain the second clock signal Cout having the dynamic range from 1.0 to 5. OGHZ by changing M in such a manner.
  • embodiments of a clock generator according to the application have advantages including that it is possible to increase the resolution of the output clock signal, e.g., the second clock signal.
  • the frequency of the fourth clock signal Cxo2 generated by the second crystal oscillator Xo2 is IMHz
  • signals can be generated in frequency- units of IGHZ. That is, signals of 1.000GHZ, 1.001GHz, 1.002GHz, ..., 5.000GHz frequency may be generated.
  • K can be variable within a range from 1000 to 5000.
  • the second crystal oscillator Xo2 for generating a signal of Q. IMHz frequency and the frequency divider 200 for changing K within a range from 10,000 to 50,000 may simply be used. Since the hardware complexity of the frequency divider 200 scarcely increases although K increases, it is possible to improve the resolution without increasing the hardware complexity by using such a configuration.
  • FIG. 2 shows a diagram of an embodiment of a delay locked loop having a frequency multiply function.
  • the delay lock loop shown in FIG. 2 can be used in the clock generator shown in FIG. 1.
  • embodiments of the application are not intended to be so limited.
  • the delay locked loop includes a phase detector 110; a loop filter 120; a voltage controlled delay line 130; and a frequency multiplier 140.
  • the phase detector 110 can obtain a phase difference P_ERR between the first clock signal Cxol and a fifth clock signal Cxol_D.
  • the loop filter 120 can receive the phase difference P_ERR and remove a high frequency component from the phase difference PJERR to output a removed phase difference.
  • the voltage controlled delay line 130 can output at least a portion of a plurality of sixth clock signals (e.g., Al, A2, ..., A8) generated by delaying the first clock signal Cxol.
  • a plurality of sixth clock signals e.g., Al, A2, ..., A8 generated by delaying the first clock signal Cxol.
  • all the sixth clock signals e.g., Al, A2, ..., A8 are outputted to the frequency multiplier 140 is illustrated in FIG. 2.
  • a portion of the plurality of sixth clock signals e.g., Al, A2, ..., A8, e.g., only Al to A4 signals, can be provided to the frequency multiplier 140.
  • Delays of the plurality of sixth clock signals are changed in response to the phase difference P_ERR_L where a high frequency component is removed, and the fifth clock signal Cxol_D can be one of the plurality of sixth clock signals (e.g., Al, A2, ..., A8).
  • the frequency multiplier 140 can generate the second clock signal Cout having a frequency higher than that of the first clock signal Cxol by using the outputted sixth clock signals (e.g., Al, A2, ..., A8).
  • the outputted sixth clock signals e.g., Al, A2, ..., A8.
  • FIG. 3 illustrates an embodiment of the voltage controlled delay line that can be used in the delay locked loop shown in FIG. 2.
  • the voltage controlled delay line can include a plurality of delay cells (e.g., Dl, D2, ..., D8) connected in series that output the plurality of sixth clock signals (e.g., Al, A2, ..., A8), and a multiplexer MUX can receive at least two signals (e.g., A4, A8) of the sixth clock signals (e.g., Al, A2, ..., A8) and output a signal selected from the inputted signals (e.g., A4, A8) according to a selection signal SEL as the fifth clock signal Cxol_D.
  • a multiplexer MUX can receive at least two signals (e.g., A4, A8) of the sixth clock signals (e.g., Al, A2, ..., A8) and output a signal selected from the inputted signals (e.g., A4, A8) according to a selection signal SEL as the fifth clock signal C
  • Eack delay of the plurality of delay cells can be changed in response to the phase difference P_ERR_L where a high frequency component is removed.
  • the first clock signal Cxol is inputted to a first delay ceE Dl of the plurality of delay cells (e.g., Dl, D2, ..., D8).
  • Each of the plurality of delay cells may be an inverter.
  • the voltage controlled delay line shown in FIG. 3 can vary a delay of each delay cell according to the selection signal SEL, so that the output clock signal, e.g., the second clock signal Cout, can be varied by changing M.
  • the output clock signal e.g., the second clock signal Cout
  • FIG. 4 shows an embodiment of the frequency multiplier that can be used in the delay locked loop shown in FIG. 2.
  • the frequency multiplier includes a plurality of XOR operators 141 and an OR operator 142.
  • the plurality of XOR operators 141 can receive the plurality of sixth clock signals (e.g., Al, A2, ..., A8) and perform XOR operations between adjacent two clock signals to output the XOR result (e.g., Bl, B2, B3, B4).
  • the OR operator 142 can perform an OR operation on the signals (e.g., Bl, B2, B3, B4) outputted from the plurality of XOR operators 141 and output the OR result as the second clock signal Cout.
  • the second clock signal Cout outputted from the frequency divider shown in FIG. 4 can have a value calculated by formula 1. [formula 1]
  • Al to A(2m) mean the plurality of sixth clock signals (e.g., Al, A2, ..., A8) and XOR and OR in.dica.te an exclusive logical sum and a logical sum, respectively.
  • FIG. 5 is a diagram displaying each signal shown in FIG. 4.
  • the plurality of sixth clock signals e.g., Al, A2, ..., A8), the signals (Bl, B2, B3, B4) outputted from the XOR operators 141 and the second clock signal Cout are shown in FIG. 5.
  • a period of the generated second clock signal Cout can be two times a delay occurring in each delay cell. Accordingly, if the delay of each delay cell is varied, for example, using the method shown in FIG. 3, the period of the second clock signal Cout may be varied.
  • FIG. 6 is a diagram showing another embodiment of a frequency multiplier that can be used in the delay locked loop shown in FIG. 2.
  • the frequency multiplier can include a plurality of XNOR operators 143 and an AND operator 144.
  • the plurality of XMOR operators 143 can receive the plurality of sixth clock signals (e.g., Al, A2, constructive., A8) and perform XNOR operations between adjacent two clock signals to output the XNOR result (Bl, B2, B3, B4) shown in FIG. 6,
  • the AND operator 144 can perform an AND operation on the signals (Bl, B2, B3, B4) outputted from the plurality of XNOR operators 143 and output the AND result as the second clock signal Cout.
  • the second clock signal Cout outputted from the frequency divider shown in FIG. 6 can have a value calculated by formula 2.
  • Al to A(2m) mean the plurality of sixth clock signals (e.g., Al, A2, ..., A8) and XNOR and AND indicate an exclusive negative logical sum and a logical product, respectively.
  • the pre-signals (Bl, B2) among the signals (Bl, B2, B3, B4) outputted from the XNOR operators 143 can be the same as the post-signals (B3, B4). Accordingly, it is possible to omit the XNOR operators 143 outputting the post- signals (B3, B4) among the XNOR operators 143 of the frequency multiplier.
  • Each, signal of the frequency multiplier shown in FIG. 6 can be easily understood with reference to FIGs. 4 and 5, and thus an additional detailed description is omitted.
  • Embodiments of a DLL clock generator and DLL clock generating method in accordance with the application have various advantages. For example, embodiments of DLL clock generators and methods can be less affected by a phase noise of an input voltage because a voltage controlled oscillator is not employed. Further, embodiments of a DLL clock generator and a DLL clock generating method can generate clock signals having frequencies which are various and accurate without increasing the complexity of hardware.
  • any reference in this specification to "one embodiment,” “an embodiment,” “example embodiment,” etc. means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.
  • the appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment.

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  • Theoretical Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

Des modes de réalisation de la présente invention concernent un générateur d'horloge et un procédé de génération d'horloge pouvant utiliser une boucle à verrouillage de retard (DLL). Dans un mode de réalisation, un générateur d'horloge peut comporter un premier oscillateur pour générer un premier signal d'horloge ayant une fréquence correspondant à un signal de commande, une boucle à verrouillage de retard pour générer un second signal d'horloge ayant une fréquence supérieure à celle du premier signal d'horloge, un diviseur de fréquence pour recevoir le second signal d'horloge afin de générer un troisième signal d'horloge ayant une fréquence inférieure à celle du second signal d'horloge, un second oscillateur pour générer un quatrième signal d'horloge et un détecteur de fréquence de phase pour générer le signal de commande correspondant à une différence de phase et/ou une différence de fréquence entre le troisième signal d'horloge et le quatrième signal d'horloge.
PCT/US2007/006800 2006-03-17 2007-03-16 Générateur d'horloge et procédé de génération d'horloge utilisant une boucle à verrouillage de retard WO2007109225A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020060024677A KR100710127B1 (ko) 2006-03-17 2006-03-17 지연 동기 루프를 이용한 클록 생성기 및 클록 생성 방법
KR10-2006-0024677 2006-03-17
US11/724,319 US7436265B2 (en) 2006-03-17 2007-03-15 Clock generator and clock generating method using delay locked loop
US11/724,319 2007-03-15

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WO2007109225A2 true WO2007109225A2 (fr) 2007-09-27
WO2007109225A3 WO2007109225A3 (fr) 2008-07-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012099992A1 (fr) * 2011-01-18 2012-07-26 Qualcomm Incorporated Boucle à verrouillage de retard d'un demi-cycle et son utilisation dans un multiplicateur de fréquence

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Publication number Priority date Publication date Assignee Title
US20040257124A1 (en) * 2003-06-23 2004-12-23 Renesas Technology Corp. Spread spectrum clock generator capable of frequency modulation with high accuracy
US6943609B2 (en) * 2001-11-20 2005-09-13 Symmetricom Inc Stratum clock state machine multiplexing switching
US7102403B2 (en) * 2005-02-03 2006-09-05 Mediatek Incorporation Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943609B2 (en) * 2001-11-20 2005-09-13 Symmetricom Inc Stratum clock state machine multiplexing switching
US20040257124A1 (en) * 2003-06-23 2004-12-23 Renesas Technology Corp. Spread spectrum clock generator capable of frequency modulation with high accuracy
US7102403B2 (en) * 2005-02-03 2006-09-05 Mediatek Incorporation Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012099992A1 (fr) * 2011-01-18 2012-07-26 Qualcomm Incorporated Boucle à verrouillage de retard d'un demi-cycle et son utilisation dans un multiplicateur de fréquence
US8487678B2 (en) 2011-01-18 2013-07-16 Qualcomm Incorporated Half cycle delay locked loop

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