WO2007105270A1

WO2007105270A1 - Information processing device, operation mode control program, and computer readable recording medium with the program recorded therein

Info

Publication number: WO2007105270A1
Application number: PCT/JP2006/304729
Authority: WO
Inventors: Shinobu Tokita
Original assignee: Fujitsu Limited
Priority date: 2006-03-10
Filing date: 2006-03-10
Publication date: 2007-09-20

Abstract

In order to suppress a coil resonance phenomenon due to alternatively switching operations with different electric power consumption in power saving mode, which can be achieved without spoiling such electric power saving effects, an information processing device is comprised of switching instruction units (20a)-(20c) to instruct a processing unit (3) of switching modes of operations, wherein the processing unit (3) operable to switch a plurality of operation modes with different power consumption is asynchronously switched from a first mode of operation mode to a second mode of operation that is different in electric power consumption from the first mode of operation.

Description

Specification

Information processing apparatus, operation mode control program, and computer-readable recording medium storing the program

Technical field

The present invention relates to a technique for suppressing the occurrence of a coiling phenomenon in an information processing apparatus such as a personal computer.

Background art

In recent years, information processing apparatuses such as home appliances and personal computers (hereinafter referred to as PCs) have various mechanisms for suppressing power consumption. For example, on a PC, when a task that requires high processing power is being executed, the processing power of the CPU (Central Processing Unit) must be maximized and the processing power required. However, when processing is performed, or when processing is performed! /, V, sometimes power consumption is reduced by keeping the execution frequency low.

[0003] Also, in the case of a notebook PC, when AC (Alternating Current) power supply is connected! /, The power that maximizes the brightness of the LCD screen should be removed. In this case, power consumption is reduced by reducing the brightness of the liquid crystal screen. However, the C :, A and PI ^ Advanced configuration and Power management Interface specifications define five states (operation modes) from C0 to C4 (states). For example, this ACPI specification is applied. In a PC, the CPU can operate in one of these five C0 to C4 states depending on the operating state of the CPU and cache memory.

[0004] The power consumption in these five states decreases in order toward the C1 to C4 states where the CO state is the highest, and the power consumption in the C4 state is the lowest.

Here, each of the C0 to C4 states will be described. The CO state is an operation mode in a normal operation state in which normal processing is executed, and power consumption is maximum. CP

When U executes the process, the PC takes this CO state.

[0005] It should be noted that any state force from the C1 state to the C4 state is restored to the CO state. This is the case when an external force operation is requested in addition to the case where an interrupt is issued to return to the CO state in any of the ~ C4 states.

The C1 state is an operation mode in the stop state, and the cache memory is usable while the CPU is stopped by the HLT (HALT) instruction which is a CPU instruction. The power consumption in this C1 state is almost the same as in the CO state.

[0006] The C2 state is a low power consumption state (hereinafter also simply referred to as a low power state), and a specific IZO

(Input / Output) The CPU is in a low power state by accessing the address. At this time, the cache memory can be used.

The C3 state is a lower power state than the C2 state, and is a state where the CPU is put into a low power state by accessing a specific IZO address. At this time, the cache memory can be used. The C3 state takes more time to return to the CO state than the C2 state.

[0007] The C4 state is a lower power state than the C3 state, that is, the lowest power consumption state among the C0 to C4 states. The CPU is put into a low power state by accessing a specific IZO address. It is in the state. The C4 state is a state in which the cache memory is turned off, and it takes more time to return to the CO state than the C3 state.

In the PC, the operating system (OS) has the authority to control the transition to the C0 to C4 state, and the operating system causes the CPU to perform the transition to the C0 to C4 state as necessary. .

[0008] At this time, the BIOS (Basic Input / Output System) notifies the operating system of the address of the IZO port used to transition to the low power state of the C2 to C4 states.

When the operating system needs to transition the CPU to any of the C2 to C4 states, the operating system accesses the address that is also informed of the BIOS power to enter a powerful state. Transition.

[0009] For example, as shown in FIG. 10, in order to transition the CPU to the C4 state, first, the operating system power IZO on the chipset (Chipset) for transitioning to the C4 state informed by the BIOS Access the port address (see arrow S 100).

Then, an instruction to make the CPU C4 state from the chipset to the CPU (here "DPRS LP # "is asserted (see arrow S101) and the CPU transitions to the C4 state (see S102).

[0010] By the way, in a PC to which the ACPI specification is applied, it is checked whether necessary work has occurred when it enters the C2 to C4 state, which is a low power state, that is, enters the power saving mode. Therefore, for example, the CPU is returned to the CO state every few ms and operated.

As a result, in the power saving mode, for example, as shown in FIG. 11, when the CPU enters the C4 state, the operating system changes the CPU to the CO state to confirm that it is effective after a certain period of time. Periodic return to the CO state and transition to the C4 state are repeated periodically at short time intervals.

[0011] That is, the power saving mode starts when the operating system transitions the operation mode to the C4 state when the CPU load is low, and when the C4 state passes for a certain period of time, an event that requires processing by the CPU In order to check if an error occurs, the operating system transitions the operating mode to the CO state.

In the power saving mode, this operation mode switching (repetition) is periodically executed at very short time intervals.

[0012] At this time, a constant voltage change continuously occurs in the circuit in a short cycle, and a magnetic flux is generated by a large power fluctuation in this short cycle. On the circuit, a coil is mounted in the vicinity of the power supply and supply circuit to stabilize the operation, but this coil vibrates due to the magnetic flux generated by the voltage change, and this vibration resonates. As a result, especially when the period of this vibration coincides with the human audible range, it may be heard by the PC user as an unpleasant high frequency (noise; coil noise).

For this reason, in order to reduce coil squealing, for example, there is a technique of changing the sleep state (low power state) of the transition destination so that the fluctuation range of the operating voltage becomes small (for example, Patent Document 1 below) reference).

In addition, in home appliances such as televisions, there is a technique for structurally reducing coil noise by devising a device for attaching a resonating coil (see, for example, Patent Document 2).

Patent Document 1: Japanese Patent Laid-Open No. 2004-246400

Patent Document 2: JP-A-8-241680 Disclosure of the invention

Problems to be solved by the invention

However, in the technique of Patent Document 1 described above, the transition destination (the state of the low power state) is changed so that the fluctuation range of the operating voltage becomes small, that is, the transition destination has high power consumption. By changing to, the difference in power consumption between the transition source and the transition destination is reduced, so even if coil squealing can be reduced, the power saving effect is also reduced at the same time.

In circuits where various parts such as PCs and notebook PCs are mounted at high density, it is extremely difficult to reduce coil noise with a structural device such as the technique of Patent Document 2 above. .

[0015] The present invention was devised in view of such a problem, and the coil squeal phenomenon that occurs when the operation modes with different power consumption are alternately switched in the power saving mode, and the power saving effect is impaired. The purpose is to enable deterrence.

Means for solving the problem

In order to achieve the above object, an information processing apparatus according to the present invention includes a processing unit that can operate by switching a plurality of operation modes with different power consumptions, the processing unit including the first operation mode, A switching instruction unit for instructing the processing unit to switch the operation mode is configured to operate while switching the first operation mode and the second operation mode having different power consumption aperiodically. It has been characterized by

[0017] It should be noted that the switching instruction unit can issue a switching instruction between the first operation mode and the second operation mode to the processing unit, and issuing the switching instruction by the issuing unit. A control unit for controlling the issuance timing output unit for periodically outputting the issuance timing of the switching instruction by the issuing unit to the control unit, and the control unit force of the switching instruction unit issuance timing output unit It is preferable to control the issuing of the switching instruction by the issuing unit so that the issuing of the switching instruction from the issuing unit is aperiodic based on the output timing of the force output.

[0018] Further, the control unit of the switching instruction unit executes at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. Is preferably stopped at irregular frequency. Further, the control unit of the switching instruction unit executes at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit at a predetermined frequency. It is preferable to stop.

[0019] Note that the control unit of the switching instruction unit performs at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. Preferably, the control unit of the switching instruction unit issues the switching instruction to the first operation mode by the issuing unit or It is preferable that at least one of issuing the switching instruction to the second operation mode is changed at a predetermined frequency to issuing the switching instruction to the third operation mode.

[0020] Further, the control unit of the switching instruction unit performs an execution timing of at least one of issuing the switching instruction to the first operation mode or issuing the switching instruction to the second operation mode by the issuing unit. Is preferably delayed at random.

The first operation mode is an operation mode in which the processing unit performs normal processing, and the second operation mode is an operation mode in which power consumption is lower than that in the first operation mode. It is preferable.

[0021] In order to achieve the above object, the operation mode control program of the present invention provides an information processing apparatus including a processing unit that can operate by switching a plurality of operation modes having different power consumptions. An operation mode control program for causing a computer to realize the function of controlling the switching of the operation mode of the first processing mode, wherein the processing unit includes a first operation mode and a second power consumption different from that of the first operation mode. The computer is caused to function as a switching instruction unit that instructs the processing unit to switch the operation mode so that the operation mode is switched aperiodically.

[0022] Note that the operation mode control program is capable of issuing a switching instruction between the first operation mode and the second operation mode to the processing unit when the computer functions as the switching instruction unit. And a control unit that controls issuance of the switching instruction by the issuing unit, and an issue timing output unit that periodically outputs the issuing timing of the switching instruction by the issuing unit to the control unit. Together with the control The issuing unit controls the issuance of the switching instruction by the issuing unit so that the issuing of the switching instruction from the issuing unit is aperiodic based on the issuance timing output. Thus, it is preferable to make the computer function.

[0023] Further, in the operation mode control program, the control unit may issue at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. Preferably, the computer is made to function so that execution is aborted at an irregular frequency.

Further, in the operation mode control program, the control unit executes at least one of the issuing of a switching instruction to the first operation mode by the issuing unit or the issuing of the switching instruction to the second operation mode. It is preferable to allow the computer to function so as to stop at a predetermined frequency.

[0024] In the operation mode control program, the control unit issues at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. Preferably, the computer is made to function so as to change at an irregular frequency to issue a switching instruction to the third mode of operation.

In the operation mode control program, the control unit issues at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit to the third mode. It is preferable to cause the computer to function so as to change at a predetermined frequency to issue an instruction to switch to an operation mode.

[0025] Further, in the operation mode control program, the control unit causes the issuing unit to issue at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode. It is preferable to cause the computer to function so as to randomly delay the execution timing.

In order to achieve the above object, a computer-readable recording medium of the present invention records the above-described operation mode control program.

The invention's effect

[0026] Thus, according to the present invention, the switching instruction unit performs the first operation so that the processing unit operates while aperiodically switching between the first operation mode and the second operation mode. Mode and second operating mode Switching to the processing unit is instructed to the processing unit, so that the switching of the operation mode between the first operation mode and the second operation mode of the processing unit becomes aperiodic, and a constant voltage change occurs in a short period. As a result, it is possible to suppress the occurrence of a coiling phenomenon that does not reduce the power saving effect.

Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration of an information processing apparatus as first to third embodiments of the present invention.

FIG. 2 is a block diagram showing a configuration of a switching instruction unit of the information processing apparatus as the first to third embodiments of the present invention.

FIG. 3 is a sequence diagram for explaining the control procedure and contents of the CPU operation mode by the information processing apparatus as the first embodiment of the present invention.

FIG. 4 is a diagram showing a switching example of the operation mode of the CPU controlled so that the switching of the operation mode becomes aperiodic by the information processing apparatus as the first embodiment of the present invention.

FIG. 5 is a diagram for explaining an operation procedure of a control unit of the information processing apparatus as the first embodiment of the present invention.

FIG. 6 is a diagram for explaining an operation procedure of a control unit of the information processing apparatus as the second embodiment of the present invention.

FIG. 7 is a diagram showing an example of switching of the operation mode of a CPU controlled so that the operation mode is switched non-periodically by the information processing apparatus as the second embodiment of the present invention.

FIG. 8 is a diagram for explaining an operation procedure of a control unit of the information processing apparatus as the third embodiment of the present invention.

FIG. 9 is a diagram showing a switching example of the operation mode of the CPU controlled so that the operation mode is switched aperiodically by the information processing apparatus as the third embodiment of the present invention.

FIG. 10 is a sequence diagram for explaining the control procedure and contents of a conventional CPU operation mode.

FIG. 11 is a diagram showing a switching example of a cyclic operation state of the CPU controlled by the control procedure and contents shown in FIG.

Explanation of symbols [0028] la ~ lc Information processing device

2 Power supply unit

3 CPU (Processor)

4 memory

5 display

6 Display controller

7 discs

8 Disk controller

9 Keyboard

10 mouse

11 Keyboard controller

12 FDD

13 Serial interface

14 Parallel interface

15 I / O controller

16a-16c BIOS -ROM

17 chipsets

17a North Bridge

17b South Bridge

18 Operating system (OS)

20a to 20c switching indicator

21 Issuing timing output section

22 Issuing Department

23a-23c control unit

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[1] About the first embodiment of the present invention

First, referring to the block diagram shown in FIG. 1, information processing as the first embodiment of the present invention is performed. The configuration of the logical device la will be described.

As shown in Fig. 1, this information processing device la has a power supply unit 2, a CPU (Central Processing Unit) 3, a memory 4, a display 5, a display controller 6, a disk 7, a disk controller 8, Keyboard 9, Mouse 10, Keyboard Controller 11, FDD (Flexible Disk Drive) 12, Serial Interface 13, Parallel Interface 14, I / O (Input / Output) Controller 15, BIOS (Basic Input / Output System) System) -ROM (Read Only Memory) 16a and chip set (Chip Set) 17 are provided.

[0030] The power supply unit 2 supplies power to each device of the information processing apparatus la.

The CPU 3 operates (executes processing) by switching a plurality of operation modes with different power consumption.

The memory 4 functions as the main memory of the information processing apparatus la, the display controller 6 controls the display 5, and the disk controller 8 controls the disk 7 as a storage device. Yes, the IZO controller 15 controls the FDD 12, serial interface 13, and parallel interface 14 that are external I / O interfaces, and the keyboard controller 11 is the keyboard 9 and the external input interface. The mouse 10 is controlled.

[0031] The BIOS-ROM 16a is a storage unit in which the BIOS is mounted (that is, written). In the information processing apparatus la, the operating system 18 (OS: 0 perating System; described later) of the information processing apparatus la In cooperation with the chip set 17 and the chip set 17, the BIOS functions as a switching instruction unit 20a (see FIG. 2 described later). In the following explanation, BIOS-ROM16a is simply referred to as BIOS 16a!

[0032] The chipset 17 is a device of the information processing apparatus la, that is, power supply unit 2, CPU 3, memory 4, display 5, display controller 6, disk 7, disk controller 8, keyboard 9, mouse 10, keyboard Controller 11, FDD12, Syranolane interface 13, Parallel interface 14, IZO controller 15, and BIOS16a are connected via a bus to control data communication between devices 2-16a, etc. It is. [0033] The chip set 17 includes a North Bridge 17a and a South Bridge 17b.

The north bridge 17a is in charge of the CPU3, memory 4, and display 5 (display controller 6), and the south bridge 17b is the disk 7 (disk controller 8) and keyboard 9 and mouse 10 (keyboard controller) that are external interfaces. 11), and FD D12, serial interface 13, and parallel interface 14 (I / O controller 15).

By the way, this information processing apparatus la adopts the specification of ACPI (Advanced Configuration and Power Management Interface), and operates in the above-described C0 to C4 states. In other words, the CPU 3 of the information processing apparatus la operates in the C0 to C4 state of operation with different power consumption.

[0035] As described above, the CO state (first operation mode) is an operation mode during normal processing, and power consumption is maximum.

The C1 state is an operation mode in the stop state, and the power consumption is substantially the same as the CO state. The C2 to C4 states (second operation mode) are low power consumption states (hereinafter also simply referred to as low power states), and the power consumption in the C4 state is the lowest.

[0036] In the information processing apparatus la, when the state transitions to the C2 to C4 state, which is the low power state, that is, when the power saving mode is followed, the CPU 3 is in the low power state. To confirm whether or not the necessary processing has occurred! /, Return the operation mode to the CO state, and if necessary processing has occurred! /, If it does not occur, transition CPU3 to the low power state again. At this time, in this information processing apparatus la, the operating system 18 simply executes the transition of the operation state of the CPU 3 to any one of the C0 to C4 states as in the conventional technique with reference to FIG. As shown in Figure 2, the operating system 18, BIOS 16a, and chipset 17 cooperate to function as the switching instruction unit 20a. Switch to the state aperiodically.

[0037] That is, in this information processing apparatus la, the operating state 18, BIOS 16a, and chipset 17 cooperate to cause the CPU 3 to perform normal processing in the CO state (first operation mode ) And a low power state that consumes less power than this CO state (second operation mode; any one of the C2 to C4 states) In order to operate, it functions as a switching instruction unit 20a that instructs the CPU 3 to switch the operation mode (here, switching between the CO state and the low power state) aperiodically.

Here, the switching instruction unit 20a realized by the operating system 18, the BIOS 16a, and the chipset 17 of the information processing apparatus la will be described in more detail with reference to FIG. 2 and FIG. Figure 3 shows the operation contents and procedure when the operating system 18, BIOS 16a, and chipset 17 transition the operation mode of the CPU 3 to the low power state (here, the C4 state) during the power saving mode of the CPU 3. FIG.

[0039] When the operating system 18 transits to the low power state (here, the C4 state) and enters the power saving mode, the operating system 18 determines whether an event requiring processing by the CPU 3 has occurred after a predetermined time has elapsed. To return to CO status. Then, if it is determined that an energetic event has not occurred, as shown in FIG. 3, the CPU 3 is again transferred to the low power state (here, the C4 state) (returned) to the predetermined IZO port of the veg chipset 17. Access (see arrow S10).

[0040] If a strong event has occurred, the operating system 18 controls the CPU 3 to take the normal operation mode (CO state) without ending the power saving mode and returning to the C4 state.

In addition, the operating system 18 in the power saving mode 18 returns to the CO state in the C4 state force periodically at a predetermined time interval, and is in the power saving mode unless an event requiring processing by the CPU 3 occurs. The access process (arrow S10) by the operating system 18 is periodically executed.

[0041] Here, the address of the predetermined IZO port accessed by the operating system 18 is the one notified to the operating system 18 by the BIOS 16a. In this information processing apparatus la, the BIOS 16a Notify the address of the IZO port for transitioning to the C4 state. Notify the address of the I / O port that generates SMI (System Management Interrupt). [0042] In other words, the BIOS 16a is configured so that the chipset 17 generates an SMI (Trap SMI) when an access is made to a predetermined I / O port of the chipset 17. The BIOS 16a notifies the operating system 18 of the IZO port address that is set to generate SMI as the I / O port address for transitioning (returning) to the low power state (C4 state here). Keep it.

[0043] Thus, when a predetermined I / O port is accessed from the operating system 18 (see arrow S10), the chipset 17 generates an SMI for the BIOS 16a (see arrow S11).

As described above, in the information processing apparatus la, the SMI is periodically output to the BIOS 16a at the timing of issuing the switching instruction to the C4 state to the operating system 18, the chipset 17, and the power CPU3.

That is, in the information processing apparatus la, the operating system 18 and the chipset 17 are

It functions as an issue timing output unit 21 (see Fig. 2) that periodically outputs SMI as the issue timing of the instruction to switch to the C4 state.

Then, as shown in FIG. 3, when the BIOS 16a receives the SMI issued from the chipset 17, the BIOS 16a makes a timing determination as to whether or not it is actually capable of executing the transition to the C4 state at this timing (reference numeral “S”). 12 ").

That is, the BIOS 16a calls an SMI handler that does not always change (return) the CPU 3 to the C4 state when receiving the SMI, and controls the chipset 17 so that the CPU 3 randomly changes to the C4 state.

That is, the BIOS 16a functions as a control unit 23a (see FIG. 2) that controls the issuance of the switching instruction to the CPU 3 by the chipset 17 as the issuing unit 22 (see FIG. 2) that can issue the switching instruction to the CPU 3. Based on the SMI from the chipset 17 (that is, the issuance timing issued from the issuance timing output unit 21), control is performed so that the issuance of the instruction to switch to the C4 state to the CPU3 by the chipset 17 is aperiodic. To do.

[0046] Specifically, the BIOS 16a controls the switching instruction from the chipset 17 to be issued aperiodically by canceling the switching instruction to the C4 state at an irregular frequency or a predetermined frequency. To do. A more specific control example using the BIOS 16a will be described later. This will be described in detail with reference to FIG.

As shown in FIG. 3, when the BIOS 16a determines that the transition of the operation mode to the C4 state is to be stopped as a result of the timing determination (symbol “S12”) (when there is no transition; see broken line arrow S1 3a) Then, without causing the chipset 17 to execute the transition to the C4 state, do nothing and complete the processing and return the processing to the operating system 18 (see the broken arrow S13b).

[0047] On the other hand, if the BIOS 16a determines that the operation mode transition to the C4 state is to be executed (when transitioning; see the dashed line arrow S14a), the chip set 17 is instructed to switch to the C4 state. To be issued, the chip set 17 accesses a predetermined IZO port that issues a switching instruction to the C4 state (see the dashed line arrow S14b).

As a result, chipset 17 issues an instruction to CPU 3 to switch to C4 state (indicated as “DPRS LP #” in the figure) (see arrow S15), and CPU 3 that has received this switching instruction changes the operation mode to the CO state. Transition (return) from C4 to C4 state (see code "S 16").

[0048] After this, after a predetermined time has elapsed, the operating system 18 changes the CPU 3 to the CO state again in order to confirm whether or not an event that requires processing by the CPU 3 has occurred. If no significant event has occurred, the process shown in Fig. 3 is executed again, and this series of processes is repeated during the power saving mode.

Therefore, in the information processing apparatus la, the transition to the C4 state is randomly canceled by the BIOS 16a as the control unit 23a, and the C0 state and the C4 state of the CPU 3 in the power saving mode as illustrated in FIG. The switching of the operation mode is aperiodic (not periodic).

That is, during the power saving mode, a constant voltage change (here, a change between the voltage in the CO state and the voltage in the C4 state) is short and does not occur continuously in a cycle.

Here, when the BIOS 16a receives the SMI as the issuance timing, the chip set 17 is instructed to execute the switching instruction to the C4 state so that the chip setting 17 force switching instruction is issued aperiodically. A specific method of timing judgment (ie

A specific control method of the issuing unit 22 by the control unit 23a) will be described.

[0050] As described above, the BIOS 16a performs control so that the instruction to switch to the C4 state by the chipset 17 is canceled at an irregular frequency or a predetermined frequency.

If it is arranged, the BIOS 16a displays the flowchart (steps S20 to S22, S23a, S24) in FIG. In the procedure shown, control using a timer (here, a power management timer) provided in advance in the information processing apparatus la is performed.

[0051] It should be noted that this power management timer is conventionally provided in the chip set 17 in the information processing apparatus la, and continuously measures the passage of a predetermined time, and is originally used for a completely different application. Is.

First, when the SMI is issued by the operating system 18 and the chipset 17 as the issue timing output unit 21 and the BIOS 16a starts the SMI controller that performs timing determination (step S20), the value of the power management timer is read (step S20). S2 Do

Here, the BIOS 16a determines whether or not the value read from the power management timer is equal to or greater than a predetermined value set in advance (step S22).

If the value to be applied is smaller than the predetermined value (No route in step S22), the BIOS 16a determines that the transition of the operation mode to the C4 state is to be stopped, and the processing without causing the chipset 17 to execute the transition to the C4 state. And the process is returned to the operating system 18 (step S23a), and the process is terminated.

[0053] On the other hand, if the value to be applied is equal to or greater than the predetermined value (Yes route in step S22), the BIOS 16a determines that the operation mode transition to the C4 state is to be executed, and the chipset 17 switches to the C4 state. The veg chipset 17 that issues an instruction issues an instruction to switch to the C4 state, that is, executes access to a predetermined IZO port for transitioning to the C4 state (step S24), and the process ends.

[0054] In order for the BIOS 16a to determine whether to stop the transition to the C4 state based on whether or not the value of the power management timer is equal to or greater than a predetermined value, the power management timer is required to measure the elapsed time. It is preferable that the time (that is, the measurement cycle of the predetermined time by the power management timer) and the switching cycle of the CO state and the C4 state of the CPU 3 in the power saving mode are substantially equal.

As described above, according to the information processing apparatus la as the first embodiment of the present invention, the switching instruction unit 20a realized by the cooperation of the operating system 18, the BIOS 16a, and the chip set 17 includes the CPU 3 The normal state of CO execution and low power C4 state Since the CPU 3 is instructed to switch the operation mode between the CO state and the C4 state aperiodically so that it operates in the power saving mode that operates alternately and non-periodically, Switching of the operation mode between the CO3 and C4 states of CPU3 is aperiodic, and a constant voltage change (here, the change between the voltage in the CO state and the voltage in the C4 state) continues in a short period. As a result, it is possible to suppress the occurrence of a coiling phenomenon that does not reduce the power saving effect.

[0056] Further, according to the information processing apparatus la, the function of suppressing the occurrence of the coil squealing phenomenon is realized mainly by changing or adding the software configuration of the BIOS 16a without adding a new hardware configuration. Therefore, it is possible to add a function to suppress the occurrence of coil squealing to existing PCs at a low cost.

Specifically, the BIOS 16a is changed to notify the operating system 18 of the address of the port that the chipset 17 generates SMI as an IZO port for transitioning to the low power state (C4 state). The operating system 18 and the chipset 17 function as the generation timing output unit 21 and the function as the control unit 23a in the BIOS 16a (that is, the function that makes the timing judgment and issues the switching instruction aperiodically). Just add).

[0057] It should be noted that the BIOS 16a performs timing determination based on the SMI (issue timing) issued by the operating system 18 and the chipset 17, so that the issue of the switching instruction by the chipset 17 becomes aperiodic. Therefore, the switching of the operation mode between the CO 3 and C4 states of the CPU 3 during the power saving mode can be surely aperiodic, and as a result, the occurrence of the coil squealing phenomenon can be more reliably suppressed.

[0058] In addition, since the BIOS 16a cancels the issuance of the instruction to switch to the C4 state during the power saving mode at an irregular frequency or a predetermined frequency, the power saving effect of the CPU 3 is not reduced. The operation mode can be switched between the CO and C4 states more reliably and non-periodically, and the BIOS 16a can be used in combination with an existing shared management timer that is originally used for a completely different purpose. Since it is determined to make a profitable stop, the coil squealing phenomenon can be suppressed at a low cost without adding a new hardware configuration. [0059] As a modification of the present embodiment, the BIOS 16a determines whether to stop the transition to the C4 state based on whether the value of the power management timer is an even number or an odd number. It may be configured to control the issuance of the switching instruction by the chipset 17 so that the transition to the C4 state is stopped if the value is even, while the transition to the C4 state is performed if the value is odd.

In addition, as another modification, the BIOS 16a controls to stop the transition to the C4 state at a predetermined frequency, for example, randomly stops twice in 10 times, for example, the switching instruction by the chipset 17 Publish may be configured to randomly stop a predetermined number of times during a predetermined number of times

Furthermore, as another modification, the BIOS 16a may be configured to cancel the issuance of the switching instruction by the chipset 17 every predetermined number of times, for example, to stop once every three times.

[2] Second embodiment of the present invention

Next, the configuration of the information processing device lb as the second embodiment of the present invention will be described with reference to the block diagram shown in FIG. 1. As shown in FIG. 1, the information processing device lb includes the BIOS 16b. However, as in the BIOS 16a of the information processing apparatus la of the first embodiment described above, a timing judgment is performed that does not stop the instruction to switch to the C4 state, and the instruction to switch to the C4 state is issued as the C2 state or the C3 state. The information processing device la is the same as the information processing device la of the first embodiment described above except that it is changed to an instruction to switch to another low power state (third operation mode). Therefore, the description of the same parts as those of the first embodiment described above is omitted here.

That is, as shown in FIG. 2, in the information processing apparatus lb, when the BIOS 16b functions as the control unit 23b of the switching instruction unit 20b, the issuing unit 22 (that is, the chipset 17) in the power saving mode is used. ) Is changed at an irregular frequency or at a predetermined frequency to issue a switching instruction other than the C4 state (in this case, either C2 or C3 state). .

[0062] It should be noted that, in other operation modes that work, it is preferable to be in a low-power state, whereby the power-saving effect of the power-saving mode can be maintained.

Specifically, for example, BIOS 16b issues an instruction to switch to the C4 state at an irregular frequency to another When changing to the operation mode switching instruction, the control using the power management timer provided in advance in this information processing device lb is performed according to the procedure shown in the flowchart of FIG. 6 (steps S20 to S22 2, S23b, S24). To do. In FIG. 6, the same reference numerals as those described above indicate the same processing or substantially the same processing, and detailed description thereof is omitted here.

[0063] That is, when the BIOS16b force SMI controller is activated (step S20), the value of the power management timer force is also read (step S21), and it is determined whether or not this value is equal to or greater than a predetermined value (step S21). Step S22).

If the power value is smaller than the predetermined value (No route in step S22), BIOS 16b

It is determined that the transition of the operation mode to the C4 state is changed to another operation mode, the switching instruction to the C4 state is changed to the switching instruction to the C3 state, and the chipset 17 is issued a switching instruction of the C3 state ( In step S23b), the process ends.

[0064] That is, the BIOS 16b has a predetermined I in which the chipset 17 issues an instruction to switch to the C4 state.

At the ZO port Access the IZO port that issues the instruction to switch to the C3 state (step S23b).

Therefore, the chip set 17 as the issuing unit 22 changes to the instruction to switch to the C4 state and issues the instruction to switch to the C3 state to the CPU3. As shown in FIG. 7, the CPU3 in the power saving mode is issued. The operation mode switching between the CO state and the C4 state becomes aperiodic.

[0065] Thus, according to the information processing device lb as the second embodiment of the present invention, it is possible to obtain the same operational effects as those of the first embodiment described above, and the C4 in which the BIOS 16b is in the power saving mode. Issuing instructions for switching to the state is changed to issuing instructions for switching to the C3 state at irregular or predetermined frequency, so that the power saving effect of the power saving mode is not reduced. The operation mode can be switched more aperiodically, and as a result, the occurrence of the coil squealing phenomenon can be reliably suppressed.

[0066] As a modification of the present embodiment, the BIOS 16b determines a change in the transition to the C4 state based on whether the value of the power management timer is an even number or an odd number. If the value is an even number, the transition to the C4 state is changed to the transition to the C3 state. Configure it to control.

[0067] Further, as another modification, the BIOS 16b controls to change the transition to the C4 state to the transition to the C3 state at a predetermined frequency, for example, randomly changing twice in 10 times, etc. The issuance of the switching instruction by the chip set 17 may be changed randomly at a predetermined number of times within a predetermined number of times.

As yet another modification, the BIOS 16b may change the issuance of the switching instruction by the chipset 17 every predetermined number of times, such as changing once every three times.

[0068] [3] Third embodiment of the present invention

Next, the configuration of the information processing device lc as the third embodiment of the present invention will be described with reference to the block diagram shown in FIG. 1. As shown in FIG. 1, the information processing device lc includes a BIOS 16C. However, as in the BIOS 16a of the information processing apparatus la of the first embodiment described above, a timing judgment is performed that does not stop the switching instruction to the C4 state, and the switching instruction to the C4 state is randomly delayed. Except for this, it is the same as the information processing apparatus la of the first embodiment described above. Therefore, the description of the same parts as those in the first embodiment described above is omitted here.

That is, as shown in FIG. 2, in the information processing apparatus lc, when the BIOS 16c functions as the control unit 23c of the switching instruction unit 20c, the issuing unit 22 in the power saving mode (that is, the chipset 17) Controls the issuance of instructions to switch to the C4 state at random by.

Specifically, using the power management timer provided in advance in this information processing device lc, following the procedure shown in the flowchart of FIG. 8 (steps S20, S21, S23c, S24). Delay control is performed. In FIG. 8, the same reference numerals as those described above indicate the same processing or substantially the same processing, and detailed description thereof is omitted here.

That is, the BIOS 16c reads the value of the power management timer force by starting the SMI controller (step S20) (step S21).

Then, the BIOS 16c executes a delay process by randomly determining the delay time of the transition of the operation mode to the C4 state based on the timer value read in step S21 (step S23c).

That is, the BIOS 16c determines that the delay time determined in accordance with the read value of the timer force has elapsed. Until chipset 17 waits for chipset 17 without issuing a command to switch to C4 state by chipset 17, and when the delay time elapses, chipset 17 accesses the IZO port that issues a command to switch to C4 state. (Step S23c).

Therefore, the issue power of the instruction to switch to the C4 state by the chip set 17 as the issuing unit 22 is randomly delayed every time it is issued, and is issued to the CPU 3, as shown in FIG. The operation mode switching between the CO3 and C4 states of CPU3 becomes aperiodic. The broken lines xl to x3 shown in FIG. 9 indicate the transition timing to the normal CO state force C4 state when the delay process is not performed.

[0072] Also, as shown by the solid line yl to y3 in FIG. 9, the operating system 18 is not informed that the BIOS 16c has delayed the issuance of the instruction to switch to the C4 state by the chipset 17, so When the transition timing to the C4 state is delayed, the C4 state force also transitions to the CO state at the normal predetermined timing (that is, after a predetermined time has elapsed since the transition to the C4 state without delay processing). Let it run.

[0073] Thus, according to the information processing device lc as the third embodiment of the present invention, it is possible to obtain the same functions and effects as those of the first embodiment described above, and the C4 when the BIOS 16C is in the power saving mode. Since the execution timing of issuing the switch instruction to the state is randomly delayed, the operation mode switching between the CO3 and C4 states of the CPU3 can be more reliably aperiodic without reducing the power saving effect of the power saving mode. As a result, the occurrence of coil squealing can be reliably suppressed.

Further, as a modification of the present embodiment, the BIOS 16c is configured to determine the delay time based on the even / odd value of the timer. For example, if the timer value is an even number, the first delay time is set as the delay time, while if the timer value is an odd number, the second delay time different from the first delay time is set as the delay time. Oh ,.

As yet another modification, the BIOS 16c may be configured to generate a random number without using a timer value and determine the delay time according to the generated random number.

[0075] [4] Other

Note that the present invention is not limited to the above-described embodiment, and various modifications and combinations can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the operating system 18, BIOS 16a to 16c, and the chipset 17 functioning as the switching instruction units 20a to 20c have aperiodic switching between the CO state and the C4 state in the power saving mode. However, the present invention is not limited to this, but the instruction to switch to the CO state is applied to the above-described embodiment. Similarly to the control (change) of the switching instruction to the C4 state, the control (change) makes the alternating switching between the CO state and the C4 state in the power saving mode non-periodic. Furthermore, it may be configured to control (change) both the instruction to switch to the C4 state and the instruction to switch to the CO state.

That is, according to the present invention, it is only necessary to control (change) at least one of the issuance of the switching instruction to the CO state or the issuance of the switching instruction to the C4 state. The alternate switching with the state can be made aperiodic, and the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, the case where the low power state is changed to the C4 state has been described as an example. However, the present invention is not limited to this, and the power consumption is higher than the CO state during the normal operation. Low C2, C3 states or other modes of operation may be used.

Furthermore, in the above-described embodiment, the BIOS 16a to 16c uses the value of the power management timer to control the issuing of the switching instruction according to this value. However, the present invention is not limited to this. For example, a mechanism for generating a random number may be provided, and the generated random number value may be handled in the same manner as the timer value in the above-described embodiment to control the issuing of the switching instruction. Also by this, it is possible to obtain the same effect as the above-described embodiment.

In the above-described embodiment, the switching of the operation mode when the CPU 3 of the information processing device la˜: Lc is in the power saving mode is described as an example. However, the present invention is not limited to this. In addition to the power saving mode, the CPU 3 can also be applied to a case where the CPU 3 operates by switching a plurality of operation modes having different power consumptions. Furthermore, the present invention can be applied to home appliances that operate while switching between a plurality of operation modes with different power consumption, in addition to the information processing devices la to lc as in the above-described embodiments.

[0079] Note that the above-described switching instruction units 20a to 20c, that is, the issue timing output unit 21, the issue unit 22 and the functions of the control units 23a to 23c may be realized by a computer (including a CPU, an information processing device, and various terminals) executing a predetermined application program (operation mode control program). .

The program is, for example, a flexible disk, CD (CD-ROM, CD-R, CD — RW, etc.), DVD (DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, etc.) ) And the like are provided in a form recorded in a computer-readable recording medium.

In this case, the computer reads the recording medium force operation mode control program, transfers it to the internal storage device or the external storage device, and uses it.

The program may be recorded in a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and the storage device power may be provided to the computer via a communication line.

[0081] Here, the computer means hardware, OS (operating system), and BIO.

This concept includes S and means hardware that operates under the control of the OS and BIOS.If the OS is not required and the hardware is operated by an application program alone, the hardware itself It corresponds to a computer.

[0082] The hardware includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium.

The application program as the operation mode control program includes a program code for realizing the functions as the switching instruction units 20a to 20c in the computer as described above. In addition, some of the functions may be realized by the OS and BIOS instead of the application program.

Note that the recording medium according to the present embodiment includes the above-mentioned flexible disk, CD, DVD, magnetic disk, optical disk, magneto-optical disk, IC card, ROM cartridge, magnetic tape, punch card, computer Various computer-readable media such as internal storage devices (memory such as RAM and ROM), external storage devices, and printed matter on which codes such as bar codes are printed can also be used.

Claims

The scope of the claims

[1] A processing unit that can operate by switching a plurality of operation modes having different power consumptions;

The processing unit is configured to operate with respect to the processing unit so that the processing unit operates while aperiodically switching between the first operation mode and the second operation mode in which power consumption is different from the first operation mode. An information processing apparatus comprising a switching instruction section for instructing switching.

[2] The switching instruction section is

An issuing unit that issues a switching instruction between the first operation mode and the second operation mode to the processing unit;

A control unit that controls the issuing of the switching instruction by the issuing unit;

An issuing timing output unit that periodically outputs the issuing timing of the switching instruction by the issuing unit to the control unit;

The control unit of the switching instruction unit causes the issuing unit to issue the switching instruction non-periodically based on the issuance timing output by the issuing timing output unit force. 2. The information processing apparatus according to claim 1, wherein issue of a switching instruction is controlled.

[3] The control unit of the switching instruction unit does not execute execution of at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. The information processing device according to claim 2, wherein the information processing device is stopped at a regular frequency.

[4] The control unit of the switching instruction unit executes at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. The information processing device according to claim 2, wherein the information processing device is stopped at a frequency.

[5] The control unit of the switching instruction unit issues at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit to the third 3. The information processing apparatus according to claim 2, wherein the information is changed at an irregular frequency to issue an instruction to switch to an operation mode.

[6] The control unit of the switching instruction unit issues at least one of issuing a switching instruction to the first operation mode by the issuing unit or issuing a switching instruction to the second operation mode. 3. The information processing apparatus according to claim 2, wherein a change is made at a predetermined frequency to issue an instruction to switch to an operation mode.

[7] The control unit of the switching instruction unit determines an execution timing of at least one of issuing the switching instruction to the first operation mode or issuing the switching instruction to the second operation mode by the issuing unit. 3. The information processing device according to claim 2, wherein the information processing device is delayed at random.

[8] The first operation mode is an operation mode in which the processing unit performs normal processing, and the second operation mode is an operation mode with lower power consumption than the first operation mode. The information processing device according to claim 1, wherein the force is any one of claims 1 to 7.

[9] An information processing apparatus having a processing unit that can be operated by switching a plurality of operation modes with different power consumptions, in order for a computer to realize a function for controlling switching of the operation mode of the processing unit. The operation mode control program of

The processing unit operates with respect to the processing unit so as to operate while aperiodically switching between the first operation mode and the second operation mode in which power consumption differs from the first operation mode. An operation mode control program characterized by causing the computer to function as a switching instruction unit for instructing such switching.

[10] When causing the computer to function as the switching instruction unit,

A control unit for controlling the issuing of the switching instruction by the issuing unit; and

As the issue timing output unit that periodically outputs the issue timing of the switching instruction by the issue unit to the control unit, the computer functions.

Based on the issuance timing output by the issuance timing output unit force, the issuance unit issues the switching instruction so that the issuance of the switching instruction from the issuing unit is aperiodic. Functioning the computer to control The operation mode control program according to claim 9, characterized in that it is a feature.

[11] The control unit performs an irregular frequency of issuing at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. 11. The operation mode control program according to claim 10, wherein the computer is caused to function so as to be stopped at a step.

[12] The control unit stops execution of at least one of the issuing of the switching instruction to the first operation mode or the issuing of the switching instruction to the second operation mode by the issuing unit at a predetermined frequency. The operation mode control program according to claim 10, which causes the computer to function as described above.

[13] The control unit issues at least one of the issuing of the switching instruction to the first operation mode by the issuing unit or the issuing of the switching instruction to the second operation mode to the third operation mode. 11. The operation mode control program according to claim 10, wherein said computer is caused to function so as to change at an irregular frequency in issuing a switching instruction.

[14] The control unit issues at least one of the issuing of the switching instruction to the first operation mode by the issuing unit or the issuing of the switching instruction to the second operation mode to the third operation mode. 11. The operation mode control program according to claim 10, wherein said computer is caused to function so as to change to issuing a switching instruction at a predetermined frequency.

[15] The control unit randomly delays the execution timing of at least one of issuing the switching instruction to the first operation mode or issuing the switching instruction to the second operation mode by the issuing unit. The operation mode control program according to claim 10, wherein the computer is caused to function so as to cause the computer to function.

[16] An information processing apparatus having a processing unit that can be operated by switching a plurality of operation modes with different power consumptions, in order for a computer to realize a function for controlling switching of the operation modes of the processing unit. A computer-readable recording medium storing the operation mode control program of

The operation mode control program is

An operation mode for the processing unit so that the processing unit operates while aperiodically switching between the first operation mode and the second operation mode that consumes less power than the first operation mode. A computer-readable recording medium having an operation mode control program recorded thereon, wherein the computer is caused to function as a switching instruction unit for instructing switching.

[17] When the operation mode control program causes the computer to function as the switching instruction unit, an issuance that can issue a switching instruction between the first operation mode and the second operation mode to the processing unit The computer functions as a control unit that controls the issuing of the switching instruction by the issuing unit, and an issue timing output unit that periodically outputs the issuing timing of the switching instruction by the issuing unit to the control unit. With

Based on the issuance timing output by the issuance timing output unit force, the issuance unit issues the switching instruction so that the issuance of the switching instruction from the issuing unit is aperiodic. 17. The computer-readable recording medium recording the operation mode control program according to claim 16, wherein the computer is caused to function so as to control.

[18] The control unit has an irregular frequency of issuing at least one of issuing a switching instruction to the first operation mode or issuing a switching instruction to the second operation mode by the issuing unit. 18. The computer-readable recording medium storing the operation mode control program according to claim 17, wherein the operation mode control program causes the computer to function so as to be stopped at step S18.

[19] The control unit stops execution of at least one of the issuing of the switching instruction to the first operation mode or the issuing of the switching instruction to the second operation mode by the issuing unit at a predetermined frequency. 18. The computer-readable recording medium recording the operation mode control program according to claim 17, wherein the operation mode control program causes the computer to function.

[20] The control unit issues at least one of the issuing of a switching instruction to the first operation mode by the issuing unit or the issuing of the switching instruction to the second operation mode to the third operation mode. 18. The computer-readable recording of an operation mode control program according to claim 17, wherein the operation mode control program causes the computer to function so as to change at an irregular frequency in issuing a switching instruction. Possible recording media.

[21] The control unit may issue an instruction to switch to the first operation mode by the issuing unit. The operation mode control program causes the computer to function so that at least one of the issuance of the switching instruction to the second operation mode is changed to the issuance of the switching instruction to the third operation mode at a predetermined frequency. 18. A computer-readable recording medium on which the operation mode control program according to claim 17 is recorded.

The control unit randomly delays the execution timing of at least one of issuing the switch instruction to the first operation mode or issuing the switch instruction to the second operation mode by the issuing unit. 18. The computer-readable recording medium recorded with the operation mode control program according to claim 17, wherein the operation mode control program causes the computer to function.