WO2007091210A3 - Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement - Google Patents

Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement Download PDF

Info

Publication number
WO2007091210A3
WO2007091210A3 PCT/IB2007/050382 IB2007050382W WO2007091210A3 WO 2007091210 A3 WO2007091210 A3 WO 2007091210A3 IB 2007050382 W IB2007050382 W IB 2007050382W WO 2007091210 A3 WO2007091210 A3 WO 2007091210A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit arrangement
test data
data
identifying
attack
Prior art date
Application number
PCT/IB2007/050382
Other languages
French (fr)
Other versions
WO2007091210A2 (en
Inventor
Giancarlo Cutrignelli
Ralf Malzahn
Original Assignee
Nxp Bv
Giancarlo Cutrignelli
Ralf Malzahn
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Giancarlo Cutrignelli, Ralf Malzahn filed Critical Nxp Bv
Priority to US12/162,832 priority Critical patent/US20090024890A1/en
Priority to EP07705797A priority patent/EP1984871A2/en
Priority to JP2008553870A priority patent/JP2009526395A/en
Publication of WO2007091210A2 publication Critical patent/WO2007091210A2/en
Publication of WO2007091210A3 publication Critical patent/WO2007091210A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Storage Device Security (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

In order to further develop a circuit arrangement (100;), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100;), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100;) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.
PCT/IB2007/050382 2006-02-09 2007-02-05 Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement WO2007091210A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/162,832 US20090024890A1 (en) 2006-02-09 2007-02-05 Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement
EP07705797A EP1984871A2 (en) 2006-02-09 2007-02-05 Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement
JP2008553870A JP2009526395A (en) 2006-02-09 2007-02-05 Circuit device, data processing device having such a circuit device, and method for identifying an attack on such a circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06101486.6 2006-02-09
EP06101486 2006-02-09

Publications (2)

Publication Number Publication Date
WO2007091210A2 WO2007091210A2 (en) 2007-08-16
WO2007091210A3 true WO2007091210A3 (en) 2007-11-22

Family

ID=38234908

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/050382 WO2007091210A2 (en) 2006-02-09 2007-02-05 Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement

Country Status (5)

Country Link
US (1) US20090024890A1 (en)
EP (1) EP1984871A2 (en)
JP (1) JP2009526395A (en)
CN (1) CN101379517A (en)
WO (1) WO2007091210A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101299602B1 (en) * 2007-03-27 2013-08-26 삼성전자주식회사 Integrated circuit protecting reverse engineering
EP2191342B1 (en) * 2007-09-13 2018-11-14 Avago Technologies General IP (Singapore) Pte. Ltd. Mesh grid protection
WO2009073231A1 (en) 2007-12-06 2009-06-11 Broadcom Corporation Embedded package security tamper mesh
US8327272B2 (en) 2008-01-06 2012-12-04 Apple Inc. Portable multifunction device, method, and graphical user interface for viewing and managing electronic calendars
US8195995B2 (en) 2008-07-02 2012-06-05 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part of an integrated circuit
EP2211289A1 (en) * 2009-01-22 2010-07-28 Robert Bosch GmbH Method and control device for protecting a sensor against manipulation
WO2011106308A2 (en) * 2010-02-23 2011-09-01 Navia Systems, Inc. Configurable circuitry for solving stochastic problems
WO2012176360A1 (en) * 2011-06-23 2012-12-27 パナソニック株式会社 Communication device, communication system
EP2780938B1 (en) 2011-11-18 2015-09-30 Tubitak Active shield with electrically configurable interconnections
FR2983990B1 (en) * 2011-12-12 2014-06-20 Oberthur Technologies CHIP CARD READER
US8776260B2 (en) 2012-09-25 2014-07-08 Broadcom Corporation Mesh grid protection system
CN103779334B (en) * 2012-10-23 2016-12-21 北京同方微电子有限公司 A kind of active preventer for smart card
US8896086B1 (en) * 2013-05-30 2014-11-25 Freescale Semiconductor, Inc. System for preventing tampering with integrated circuit
EP3147830B1 (en) * 2015-09-23 2020-11-18 Nxp B.V. Protecting an integrated circuit
WO2017138774A1 (en) * 2016-02-12 2017-08-17 한양대학교 산학협력단 Security semiconductor chip and method for operating same
US10972460B2 (en) * 2016-02-12 2021-04-06 Industry-University Cooperation Foundation Hanyang University Secure semiconductor chip and operating method thereof
KR102413790B1 (en) * 2020-11-27 2022-06-28 연세대학교 산학협력단 Security circuit of a chip

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117457A (en) * 1986-11-05 1992-05-26 International Business Machines Corp. Tamper resistant packaging for information protection in electronic circuitry
US6496119B1 (en) * 1998-11-05 2002-12-17 Infineon Technologies Ag Protection circuit for an integrated circuit
US6798234B2 (en) * 2000-08-21 2004-09-28 Infineon Technologies Ag Apparatus for protecting an integrated circuit formed in a substrate and method for protecting the circuit against reverse engineering
US20050047047A1 (en) * 2003-08-28 2005-03-03 Matsushita Electric Industrial Co., Ltd. Protection circuit for semiconductor device and semiconductor device including the same
US20050092848A1 (en) * 2002-05-24 2005-05-05 Infineon Technologies Ag Integrated circuit having an active shield
EP1538666A1 (en) * 2003-02-04 2005-06-08 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002536727A (en) * 1999-01-29 2002-10-29 インフィネオン テクノロジース アクチエンゲゼルシャフト Integrated circuit
JP2002110258A (en) * 2000-10-03 2002-04-12 Alps Electric Co Ltd Battery with protection circuit
JP2003296680A (en) * 2002-03-29 2003-10-17 Hitachi Ltd Data processor
JP4758621B2 (en) * 2003-08-28 2011-08-31 パナソニック株式会社 Basic cell, end cell, wiring shape, wiring method, shield wire wiring structure
US7281667B2 (en) * 2005-04-14 2007-10-16 International Business Machines Corporation Method and structure for implementing secure multichip modules for encryption applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117457A (en) * 1986-11-05 1992-05-26 International Business Machines Corp. Tamper resistant packaging for information protection in electronic circuitry
US6496119B1 (en) * 1998-11-05 2002-12-17 Infineon Technologies Ag Protection circuit for an integrated circuit
US6798234B2 (en) * 2000-08-21 2004-09-28 Infineon Technologies Ag Apparatus for protecting an integrated circuit formed in a substrate and method for protecting the circuit against reverse engineering
US20050092848A1 (en) * 2002-05-24 2005-05-05 Infineon Technologies Ag Integrated circuit having an active shield
EP1538666A1 (en) * 2003-02-04 2005-06-08 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device
US20050047047A1 (en) * 2003-08-28 2005-03-03 Matsushita Electric Industrial Co., Ltd. Protection circuit for semiconductor device and semiconductor device including the same

Also Published As

Publication number Publication date
CN101379517A (en) 2009-03-04
EP1984871A2 (en) 2008-10-29
JP2009526395A (en) 2009-07-16
US20090024890A1 (en) 2009-01-22
WO2007091210A2 (en) 2007-08-16

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