WO2007082044A3 - Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems - Google Patents

Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems Download PDF

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Publication number
WO2007082044A3
WO2007082044A3 PCT/US2007/000773 US2007000773W WO2007082044A3 WO 2007082044 A3 WO2007082044 A3 WO 2007082044A3 US 2007000773 W US2007000773 W US 2007000773W WO 2007082044 A3 WO2007082044 A3 WO 2007082044A3
Authority
WO
WIPO (PCT)
Prior art keywords
parallel
computing elements
multimedia data
algorithm steps
algorithm
Prior art date
Application number
PCT/US2007/000773
Other languages
French (fr)
Other versions
WO2007082044A2 (en
Inventor
Lazar Bivolarski
Bogdan Mitu
Original Assignee
Brightscale Inc
Lazar Bivolarski
Bogdan Mitu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brightscale Inc, Lazar Bivolarski, Bogdan Mitu filed Critical Brightscale Inc
Priority to EP07716563A priority Critical patent/EP1971958A2/en
Priority to JP2008550415A priority patent/JP2009523293A/en
Publication of WO2007082044A2 publication Critical patent/WO2007082044A2/en
Publication of WO2007082044A3 publication Critical patent/WO2007082044A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Computing Systems (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)

Abstract

An efficient method and device for the parallel processing of data variables. A parallel processing array has computing elements configured to process data variables in parallel. An algorithm for a plurality of computing elements of a parallel processor is loaded. The algorithm includes a plurality of processing steps. Each of the plurality of computing elements is configured to process a data variable associated with the computing element. Selection codes for the plurality of computing elements of the parallel processor are loaded, wherein the selection codes identify which of the algorithm steps are to be applied by the computing elements to the data variables. The algorithm processing steps are applied to the data variables by the computing elements, wherein for each computing element, only those processing steps identified by the selection codes are applied to the data variable.
PCT/US2007/000773 2006-01-10 2007-01-10 Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems WO2007082044A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07716563A EP1971958A2 (en) 2006-01-10 2007-01-10 Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems
JP2008550415A JP2009523293A (en) 2006-01-10 2007-01-10 Method and apparatus for processing algorithmic steps of multimedia data in a parallel processing system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75806506P 2006-01-10 2006-01-10
US60/758,065 2006-01-10

Publications (2)

Publication Number Publication Date
WO2007082044A2 WO2007082044A2 (en) 2007-07-19
WO2007082044A3 true WO2007082044A3 (en) 2008-04-17

Family

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Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2007/000771 WO2007082042A2 (en) 2006-01-10 2007-01-10 Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems
PCT/US2007/000773 WO2007082044A2 (en) 2006-01-10 2007-01-10 Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems
PCT/US2007/000772 WO2007082043A2 (en) 2006-01-10 2007-01-10 Method and apparatus for scheduling the processing of multimedia data in parallel processing systems

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2007/000771 WO2007082042A2 (en) 2006-01-10 2007-01-10 Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2007/000772 WO2007082043A2 (en) 2006-01-10 2007-01-10 Method and apparatus for scheduling the processing of multimedia data in parallel processing systems

Country Status (7)

Country Link
US (4) US20070189618A1 (en)
EP (3) EP1971958A2 (en)
JP (3) JP2009523291A (en)
KR (3) KR20080085189A (en)
CN (3) CN101371262A (en)
TW (3) TW200737983A (en)
WO (3) WO2007082042A2 (en)

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