WO2007081806A2 - Interdigitated conductive lead frame or laminate lead frame for gan die - Google Patents

Interdigitated conductive lead frame or laminate lead frame for gan die Download PDF

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Publication number
WO2007081806A2
WO2007081806A2 PCT/US2007/000282 US2007000282W WO2007081806A2 WO 2007081806 A2 WO2007081806 A2 WO 2007081806A2 US 2007000282 W US2007000282 W US 2007000282W WO 2007081806 A2 WO2007081806 A2 WO 2007081806A2
Authority
WO
WIPO (PCT)
Prior art keywords
die
source
drain
pads
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/000282
Other languages
French (fr)
Other versions
WO2007081806A3 (en
Inventor
Kunzhong Hu
Chuan Cheah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of WO2007081806A2 publication Critical patent/WO2007081806A2/en
Publication of WO2007081806A3 publication Critical patent/WO2007081806A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements

Definitions

  • This invention relates to a novel conductive support structure for GaN die and assemblies of GaN die with other die connected thereto.
  • GaN die Hi-Nitride heteroj unction die
  • GaN die for other semiconductor die connected in various circuit configurations with the GaN die.
  • coplanar conductive lead frames or laminates with conductive pad surfaces are conventionally used to support semiconductor die.
  • the connection to GaN die, which are commonly bidirectional lateral conduction die, is complicated by the electrode pattern of the GaN die which commonly is a pattern of alternating thin closely spaced drain and source pads in a ladder-like configuration.
  • a conductive support for GaN die is provided with enlarged area conductor surfaces having spaced parallel sides with laterally projecting and coplanar spaced interdigitated fingers which align with and receive respective ones of the source and drain strips of a lateral conduction GaN based die thus forming an enlarged contact surface for wire bond or other connection to the GaN device source and drain electrodes.
  • enlarged area is meant an area equal to or greater than the area of the top surface of the die.
  • At least two further enlarged gate areas are disposed adjacent edges of one or both of the source and drain connection area and are provided with respective coplanar projecting fingers to align with and contact the gate electrodes of the GaN die.
  • Other die for example, silicon based diodes and vertical conduction MOSFETs or other MOSgated devices may also be surface mounted on one or both of the enlarged source and drain pads and wire bonded in any desired circuit configuration with the GaN die.
  • Figure 1 is a top plan view of a GaN die having laterally disposed and alternating drain electrode strips and end gate electrodes.
  • Figure 2a shows a lead frame constructed in accordance with the invention for receiving the die of Figure 1.
  • Figure 2b schematically shows the die of Figure 1 mounted on the interdigitated fingers of the lead frame of Figure 2a.
  • Figure 3a shows a second embodiment of the lead frame of Figure 2a with a modified gate pad arrangement.
  • Figure 3b shows the die of Figure 1 on the interdigitated fingers of the lead frame of Figure 3a.
  • Figure 4a shows a third embodiment of the invention with a further modified gate pad arrangement.
  • Figure 4b shows the die of Figure 1 on the interdigitated fingers of the lead frame of Figure 4a.
  • Figure l is a top view of a bidirectional conduction GaN die 10 having alternately spaced source electrodes S and drain electrodes D and gate electrodes Gl and G2.
  • Such die are shown in detail in U.S. Patent Publication No. 2005/0139891 filed December 3, 2004 entitled ⁇ I-N ⁇ RIDE DEVICE WITH IMPROVED LAYOUT GEOMETRY in the names of Beach and Bridger (IR-2616) and in U.S. Patent Publication No. 2006/0131760 filed September 13, 2005 entitled POWER SEMICONDUCTOR PACKAGE in the names of Standing and Clark (IR-2742), which are incorporated entirely herein by reference.
  • Figure 2a is a top view of a conductive lead frame which has been patterned and stamped in accordance with the invention to receive the die of Figure 1.
  • the lead frame has an enlarged source pad 11 and an enlarged drain pad 12 which each have sets of comb-like extending fingers S and D respectively which correspond to the locations and width of the electrodes S and D respectively on die 10. All of Fingers S and D are in a common plane.
  • Two gate pads 13 and 14 are also provided as shown; having respective extending lead frame fingers Gl and G2 for connection to electrodes Gl and G2 of die 10.
  • Lead frame fingers Gl and G2 are also coplanar with fingers S and D.
  • Figure 2b shows the die 10 laid over the various drain, source and gate fingers of the lead frame, and connected thereto as by soldering or by other conductive adhesives, or the like.
  • the enlarged source and drain pads 11 and 12 respectively will act as excellent heat sinks for die 10.
  • the source and drain pads 11 and 12 can also receive diverse die or other components to be connected in circuit relation with die 10.
  • a diode die 20 has one electrode conductively secured or bonded to the source pad 11 and its upper surface wire bonded to the lower gate pad 12 by wire bonds 15.
  • a plastic housing can enclose die 10 and the lead frame, with portions of the lead frame extending through the housing for external circuit connection.
  • Figures 3a and 3b show a second embodiment of the invention.
  • the lead frame of Figure 3a is modified from that of Figure 2a to have gate pads 30 and 31 on opposite sides of the source pad 11.
  • a projection 32 extends from the drain pad in Figure 3a for connection to gate G2 of die 10.
  • GaN device 10 is assembled to the lead frame of Figure 3a in
  • a vertical conduction silicon based MOSFET 40 has its bottom drain electrode secured to and connected to the source pad 11 in Figure 3a, and its gate and source electrodes 41 and 42 respectively are wire bonded to gate pads 30 and 31 respectively as shown.
  • Figures 4a and 4b show a further embodiment of the invention.
  • the lead frame of Figure 4a is like that of Figure 2a but two additional gate pads 60 and 61 are added above the source pad 11 and below the drain pad 12 respectively.
  • Vertical conduction MOSFET die 62 and 63 then have their drain electrodes bonded to the source and drain pads 11 and 12 respectively.
  • the source electrodes and gate electrodes of MOSFETs 62 and 63 are then wire bonded as shown to form a circuit with die 10.
  • the lead frames in Figure 2a, 3a and 4a can be replaced by any other desired conductive substrate such as a laminated substrate with plural layers containing other circuit components, or an IMS substrate or the like.

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Description

INTERDIGITATED CONDUCTIVE LEAD FRAME OR LAMINATE LEAD FRAME FOR GaN DIE
RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No.
60/757,797, filed January 10, 2006, the entire disclosure of which is incorporated by reference herein.
FDSLD OF THE INVENTION
[0002] This invention relates to a novel conductive support structure for GaN die and assemblies of GaN die with other die connected thereto.
BACKGROUND OF THE INVENTION
[0003] It is necessary to provide a conductive support for the packaging of
GaN die (Hi-Nitride heteroj unction die) and for other semiconductor die connected in various circuit configurations with the GaN die. Thus, coplanar conductive lead frames or laminates with conductive pad surfaces are conventionally used to support semiconductor die. The connection to GaN die, which are commonly bidirectional lateral conduction die, is complicated by the electrode pattern of the GaN die which commonly is a pattern of alternating thin closely spaced drain and source pads in a ladder-like configuration.
[0004] It would be desirable to provide a conductive support which would provide connectors to the closely spaced source and drain strips of a GaN die and to provide an effective heat sink for these electrodes and to provide a mounting area for other die such as silicon-based diodes and MOSFETs to be connected in various circuit arrangements with the GaN die. SUMMARY OF THE INVENTION
[0005] In accordance with the invention, a conductive support for GaN die is provided with enlarged area conductor surfaces having spaced parallel sides with laterally projecting and coplanar spaced interdigitated fingers which align with and receive respective ones of the source and drain strips of a lateral conduction GaN based die thus forming an enlarged contact surface for wire bond or other connection to the GaN device source and drain electrodes. By "enlarged area" is meant an area equal to or greater than the area of the top surface of the die. At least two further enlarged gate areas are disposed adjacent edges of one or both of the source and drain connection area and are provided with respective coplanar projecting fingers to align with and contact the gate electrodes of the GaN die. Other die, for example, silicon based diodes and vertical conduction MOSFETs or other MOSgated devices may also be surface mounted on one or both of the enlarged source and drain pads and wire bonded in any desired circuit configuration with the GaN die.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a top plan view of a GaN die having laterally disposed and alternating drain electrode strips and end gate electrodes.
[0007] Figure 2a shows a lead frame constructed in accordance with the invention for receiving the die of Figure 1.
[0008] Figure 2b schematically shows the die of Figure 1 mounted on the interdigitated fingers of the lead frame of Figure 2a.
[0009] Figure 3a shows a second embodiment of the lead frame of Figure 2a with a modified gate pad arrangement.
[0010] Figure 3b shows the die of Figure 1 on the interdigitated fingers of the lead frame of Figure 3a. [0011] Figure 4a shows a third embodiment of the invention with a further modified gate pad arrangement.
[0012] Figure 4b shows the die of Figure 1 on the interdigitated fingers of the lead frame of Figure 4a.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013] Figure l is a top view of a bidirectional conduction GaN die 10 having alternately spaced source electrodes S and drain electrodes D and gate electrodes Gl and G2. Such die are shown in detail in U.S. Patent Publication No. 2005/0139891 filed December 3, 2004 entitled ΠI-NΓΓRIDE DEVICE WITH IMPROVED LAYOUT GEOMETRY in the names of Beach and Bridger (IR-2616) and in U.S. Patent Publication No. 2006/0131760 filed September 13, 2005 entitled POWER SEMICONDUCTOR PACKAGE in the names of Standing and Clark (IR-2742), which are incorporated entirely herein by reference.
[0014] Figure 2a is a top view of a conductive lead frame which has been patterned and stamped in accordance with the invention to receive the die of Figure 1. Thus, the lead frame has an enlarged source pad 11 and an enlarged drain pad 12 which each have sets of comb-like extending fingers S and D respectively which correspond to the locations and width of the electrodes S and D respectively on die 10. All of Fingers S and D are in a common plane. Two gate pads 13 and 14 are also provided as shown; having respective extending lead frame fingers Gl and G2 for connection to electrodes Gl and G2 of die 10. Lead frame fingers Gl and G2 are also coplanar with fingers S and D.
[0015] Figure 2b shows the die 10 laid over the various drain, source and gate fingers of the lead frame, and connected thereto as by soldering or by other conductive adhesives, or the like. The enlarged source and drain pads 11 and 12 respectively will act as excellent heat sinks for die 10. [0016] The source and drain pads 11 and 12 can also receive diverse die or other components to be connected in circuit relation with die 10. Thus, in Figure 2b, a diode die 20 has one electrode conductively secured or bonded to the source pad 11 and its upper surface wire bonded to the lower gate pad 12 by wire bonds 15.
[0017] A plastic housing, not shown, can enclose die 10 and the lead frame, with portions of the lead frame extending through the housing for external circuit connection.
[0018] Figures 3a and 3b show a second embodiment of the invention.
[0019] The lead frame of Figure 3a is modified from that of Figure 2a to have gate pads 30 and 31 on opposite sides of the source pad 11. A projection 32 extends from the drain pad in Figure 3a for connection to gate G2 of die 10.
[0020] The GaN device 10 is assembled to the lead frame of Figure 3a in
Figure 3b. A vertical conduction silicon based MOSFET 40 has its bottom drain electrode secured to and connected to the source pad 11 in Figure 3a, and its gate and source electrodes 41 and 42 respectively are wire bonded to gate pads 30 and 31 respectively as shown.
[0021] Figures 4a and 4b show a further embodiment of the invention. The lead frame of Figure 4a is like that of Figure 2a but two additional gate pads 60 and 61 are added above the source pad 11 and below the drain pad 12 respectively. Vertical conduction MOSFET die 62 and 63 then have their drain electrodes bonded to the source and drain pads 11 and 12 respectively. The source electrodes and gate electrodes of MOSFETs 62 and 63 are then wire bonded as shown to form a circuit with die 10.
[0022] The lead frames in Figure 2a, 3a and 4a can be replaced by any other desired conductive substrate such as a laminated substrate with plural layers containing other circuit components, or an IMS substrate or the like.
[0023] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.

Claims

WHAT IS CLAIMED IS:
1. A conductive support for a GaN semiconductor die having a plurality of parallel spaced and interleaved source and gate electrode strips on a surface of said die; said conductive support having an enlarged source pad and a coplanar, spaced enlarged drain pad; the facing edges of said source and drain pads each having a plurality of integral extending spaced parallel fingers; said fingers of said source and drain pads being interdigitated and parallel to one another and spaced from one another; the alternate source and drain fingers being disposed in alignment with and in contact with respective ones of said source and gate electrode strips.
2. The conductive support of claim 1, which further includes at least one gate pad spaced from and coplanar with said source pad; said GaN die having at least one gate electrode at one edge region of said die; said at least one gate pad having an edge in alignment with said edge of said source pad; and a gate contact finger extending from said at least one gate pad edge and in alignment with and in contact with said gate electrode.
3. The support of claim 1, wherein said source and drain pads are components of a thin conductive lead frame.
4. The support of claim 2, wherein said source, drain and gate pads are components of a thin conductive lead frame.
5. The support of claim 1, wherein said source and drain pads are supported on an insulation support surface.
6. The support of claim 2, wherein said source, drain and gate pads are supported on an insulation support surface.
7. The support of claim 2, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
8. The support of claim 4, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
9. The support of claim 6, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
10. The support of claim 7, wherein said second semiconductor die is a silicon based diode or MOSgated device.
11. The support of claim 2, which further includes a second gate electrode at the opposite edge region from said one edge region of said GaN die and a second gate pad spaced from and coplanar with said drain pad and having an edge in alignment with said edge of said drain pad; and a second gate contact finger extending from said edge of said second gate pad and in alignment with and in contact with said second gate electrode.
12. The support of claim 11, wherein said source, drain and gate pads are components of a thin conductive lead frame.
13. The support of claim 11, wherein said source, drain and gate pads are supported on an insulation support surface.
14. The support of claim 11, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
15. A semiconductor device comprising a GaN die and a conductive support therefore which provides improved contact to the electrodes of said GaN die; said GaN die having an elongated rectangular shape; one surface of said die comprising a ladder of parallel coplanar contact strips which are, alternately, source and drain electrode strips, and at least one gate strip at one end of said ladder; said conductive support comprising an enlarged area source pad, an enlarged area drain pad and an enlarged area gate pad; all of said pads being spaced from one another; one edge of each of said source and drain pads having combs of parallel spaced contact fingers; said contact fingers of said source and drain pads being interdigitated and coplanar and disposed over and in contact with respective ones of said source and drain contact strips; said gate pad having a gate contact finger spaced from and coplanar with said contact fingers and extending therefrom and in contact with said gate strip on said die.
16. The device of claim 15, wherein said source, drain and gate contacts are connected to their respective contact strips by solder or a conductive adhesive.
17. The device of claim 15, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
18. The device of claim 16, which further includes a second semiconductor die having top and bottom electrodes; said bottom electrode of said die being conductively fixed to the surface of one of said source or drain pads, the top electrode of said die being connected to another of said pads.
PCT/US2007/000282 2006-01-10 2007-01-08 Interdigitated conductive lead frame or laminate lead frame for gan die Ceased WO2007081806A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US75779706P 2006-01-10 2006-01-10
US60/757,797 2006-01-10
US11/650,152 US7994632B2 (en) 2006-01-10 2007-01-05 Interdigitated conductive lead frame or laminate lead frame for GaN die
US11/650,152 2007-01-05

Publications (2)

Publication Number Publication Date
WO2007081806A2 true WO2007081806A2 (en) 2007-07-19
WO2007081806A3 WO2007081806A3 (en) 2008-06-19

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WO (1) WO2007081806A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2330622A1 (en) * 2009-12-07 2011-06-08 Hamilton Sundstrand Corporation Solid state switch arrangement
EP3321960A1 (en) * 2016-11-15 2018-05-16 Rohm Co., Ltd. Semiconductor device

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7994632B2 (en) * 2006-01-10 2011-08-09 International Rectifier Corporation Interdigitated conductive lead frame or laminate lead frame for GaN die
JP5608322B2 (en) * 2008-10-21 2014-10-15 パナソニック株式会社 Bidirectional switch
JP2012084743A (en) 2010-10-13 2012-04-26 Fujitsu Semiconductor Ltd Semiconductor device and power supply device
US8847408B2 (en) * 2011-03-02 2014-09-30 International Rectifier Corporation III-nitride transistor stacked with FET in a package
KR20130013189A (en) 2011-07-27 2013-02-06 삼성전자주식회사 Power semiconductor device
JP2013153027A (en) * 2012-01-24 2013-08-08 Fujitsu Ltd Semiconductor device and power supply device
JP5985282B2 (en) * 2012-07-12 2016-09-06 ルネサスエレクトロニクス株式会社 Semiconductor device
USD774477S1 (en) * 2014-03-28 2016-12-20 Osram Sylvania Inc. Conductor pads
US9484471B2 (en) * 2014-09-12 2016-11-01 Qorvo Us, Inc. Compound varactor
US9385657B1 (en) 2015-03-31 2016-07-05 Northrop Grumman Systems Corporation Triple balanced, interleaved mixer
US10074597B2 (en) 2017-01-20 2018-09-11 Infineon Technologies Austria Ag Interdigit device on leadframe for evenly distributed current flow
US10312167B2 (en) * 2017-02-15 2019-06-04 Infineon Technologies Ag Semiconductor package, assembly and module arrangements for measuring gate-to-emitter/source voltage
US10692801B2 (en) 2018-05-31 2020-06-23 Infineon Technologies Austria Ag Bond pad and clip configuration for packaged semiconductor device
TWI715497B (en) * 2020-05-14 2021-01-01 劉台徽 Tandem connection power electronic device packaging method and packaging structure thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473512A (en) * 1993-12-16 1995-12-05 At&T Corp. Electronic device package having electronic device boonded, at a localized region thereof, to circuit board
US5915164A (en) * 1995-12-28 1999-06-22 U.S. Philips Corporation Methods of making high voltage GaN-A1N based semiconductor devices
JP2778587B2 (en) * 1996-07-04 1998-07-23 日本電気株式会社 Semiconductor device
FR2759493B1 (en) * 1997-02-12 2001-01-26 Motorola Semiconducteurs SEMICONDUCTOR POWER DEVICE
JP2000138262A (en) * 1998-10-31 2000-05-16 Anam Semiconductor Inc Chip-scale semiconductor package and method of manufacturing the same
US6740969B1 (en) * 1999-08-25 2004-05-25 Renesas Technology Corp. Electronic device
US6278264B1 (en) * 2000-02-04 2001-08-21 Volterra Semiconductor Corporation Flip-chip switching regulator
JP2003258179A (en) * 2002-02-28 2003-09-12 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP4142922B2 (en) * 2002-09-12 2008-09-03 株式会社ルネサステクノロジ Strobe control circuit, IGBT device, semiconductor device and electronic equipment
US6740907B2 (en) * 2002-10-04 2004-05-25 Rohm Co., Ltd. Junction field-effect transistor
US6896976B2 (en) * 2003-04-09 2005-05-24 International Rectifier Corporation Tin antimony solder for MOSFET with TiNiAg back metal
US7166867B2 (en) * 2003-12-05 2007-01-23 International Rectifier Corporation III-nitride device with improved layout geometry
JP4426955B2 (en) * 2004-11-30 2010-03-03 株式会社ルネサステクノロジ Semiconductor device
US7994632B2 (en) * 2006-01-10 2011-08-09 International Rectifier Corporation Interdigitated conductive lead frame or laminate lead frame for GaN die

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2330622A1 (en) * 2009-12-07 2011-06-08 Hamilton Sundstrand Corporation Solid state switch arrangement
EP3321960A1 (en) * 2016-11-15 2018-05-16 Rohm Co., Ltd. Semiconductor device
US10600744B2 (en) 2016-11-15 2020-03-24 Rohm Co., Ltd. Semiconductor device
US11342290B2 (en) 2016-11-15 2022-05-24 Rohm Co., Ltd. Semiconductor device
US11901316B2 (en) 2016-11-15 2024-02-13 Rohm Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
WO2007081806A3 (en) 2008-06-19
US7994632B2 (en) 2011-08-09
US8791560B2 (en) 2014-07-29
US20110272705A1 (en) 2011-11-10
US20070181934A1 (en) 2007-08-09

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