WO2007080031A1

WO2007080031A1 - Method and apparatus for recording high-speed input data into a matrix of memory devices

Info

Publication number: WO2007080031A1
Application number: PCT/EP2006/069265
Authority: WO
Inventors: Thomas Brune; Jens Peter Wittenburg
Original assignee: Thomson Licensing
Priority date: 2006-01-16
Filing date: 2006-12-04
Publication date: 2007-07-19
Also published as: TW200739341A; AU2006334660A1; JP2009524127A; EP1974354A1; RU2417461C2; ATE430364T1; JP5160448B2; TWI403896B; CA2636237C; CA2636237A1; KR20080092364A; US20090083591A1; CN101361137A; CN101361137B; EP1808863A1; AU2006334660B2; RU2008133604A; DE602006006600D1; KR101261671B1; US7802152B2

Abstract

For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.

Description

Method and Apparatus for recording high-speed input data into a matrix of memory devices

The invention relates to a method and to an apparatus for recording high-speed input data into a matrix of memory devices .

Background

For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based sys- terns could be used. Flash memory devices are physically accessed in a page oriented mode, whereby one 'page' includes e.g. 1024 data words and related error correction code (ecc) . Erase operations on a specific flash memory can be carried out on certain-size data blocks only. These data blocks are denoted by the term ^Λflash block' in the following. A flash block consists of e.g. 64 pages. NAND flash memories have two basic disadvantages:

- the write access is rather slow;

- they have unmasked production defects and acquire even more defects during their lifetime. The required error handling is under user responsibility. This is also true for equivalent memory types.

Since a detection of defects in flash memory devices (e.g. NAND devices) takes place for instance during an erase op- eration, a defect in a page makes an entire flash block unusable. Such defect flash blocks must not be used by the file system. The handling of such defects is fully under user responsibility. It is known to use redundancy codes like Reed-Solomon for such error processing, but that has other disadvantages like high dynamic time consumption versus real-time behaviour. For example, the following NAND flash memories are on the market: Samsung K9K2G16U0M-YCBOOO (2Gbit, lβbit oriented), K9W4G08U0M-YCBOOO (4Gbit, 8bit oriented), Toshiba TH58NVG2S3BFT00 (4Gbit, 8bit oriented), MICRON MT29G08AAxxx (2Gbit, 8bit oriented), MT29G16AAxxx (2Gbit, lβbit oriented), Samsung K9K4G08 (4Gbit, 8bit oriented).

Invention

The invention can be used for real-time recording of high definition streaming video data on NAND flash memory based devices. Using flash devices while recording in real-time at high data throughput will result in big files or takes, re- spectively. It is important to have a resource and performance efficient processing for dynamical defect remapping from faulty flash blocks towards free flash blocks. Today's most NAND flash applications are Reed-Solomon error protected and not real-time capable.

A problem to be solved by the invention is to provide a resource and performance efficient algorithm for remapping defects in FLASH devices that occur while in operation, to support low power consumption, short operation time and real-time capability. This problem is solved by the method disclosed in claim 1. An apparatus that utilises this method is disclosed in claim 2.

According to the invention, high-speed input data are writ- ten in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data con- tent for the current flash device page of all flash devices of the matrix is also copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.

In principle, the inventive method is suited for recording high-speed input data into a matrix of memory devices of a first type, said matrix including at least two memory de^¬ vices per row and at least two memory devices per column, wherein the memory devices of a row are connected to a com^¬ mon bus and to each row of said matrix a separate common bus is assigned, and wherein said memory devices each are inter^¬ nally arranged in multiple pages to which pages input data can be written in a sequential manner, and wherein when writing into said first type memory devices defects may oc^¬ cur at different locations in said memory devices, said method including the steps:

A) writing a first section of input data in a multiplexed manner, using said common buses, in the same current page of the memory devices, starting with the first column of memory devices, column by column, and writing this first section of input data also in a corresponding section of an additional memory device of a second type different from said first type;

B) checking whether or not at least one defect in at least one memory device has occurred while writing said first sec- tion of input data into said current page of the memory de^¬ vices;

C) writing the following section of input data in a multiplexed manner, using said common buses, in the following page of the memory devices, starting with the first column of memory devices, column by column, and if no defect has been found in the foregoing step, also writing this following section of input data in the same section of said additional memory device, and if a defect has been found in the foregoing step, also writing this following section of input data in a following corresponding section of said additional memory device;

D) checking whether or not at least one defect in at least one memory device has occurred while writing said following section of input data into said following page;

E) continuing with steps C) and D) until all sections of in- put data have been written into said matrix of memory devices and into said additional memory device;

F) copying input data stored in corresponding sets of pages of said matrix of memory devices, which sets include per set at least one defect in at least one memory device, to corre- sponding sets of pages in said matrix of memory devices which are not yet occupied with said input data, thereby taking input data of defect single pages not from said matrix of memory devices but from corresponding single page data stored in said additional memory device.

In principle the inventive apparatus is suited for recording high-speed input data into a matrix of memory devices of a first type, said matrix including at least two memory devices per row and at least two memory devices per column, wherein the memory devices of a row are connected to a common bus and to each row of said matrix a separate common bus is assigned, and wherein said memory devices each are internally arranged in multiple pages to which pages input data can be written in a sequential manner, and wherein when writing into said first type memory devices defects may occur at different locations in said memory devices, said apparatus including an additional memory device of a second type different from said first type and means being adapted for carrying out the following functions: A) writing a first section of input data in a multiplexed manner, using said common buses, in the same current page of the memory devices, starting with the first column of memory devices, column by column, and writing this first section of input data also in a corresponding section of said addi^¬ tional memory device; B) checking whether or not at least one defect in at least one memory device has occurred while writing said first sec^¬ tion of input data into said current page of the memory de^¬ vices; C) writing the following section of input data in a multi- plexed manner, using said common buses, in the following page of the memory devices, starting with the first column of memory devices, column by column, and if no defect has been found in the foregoing function, also writing this following section of input data in the same section of said additional memory device, and if a defect has been found in the foregoing function, also writing this following section of input data in a following corresponding section of said additional memory device; D) checking whether or not at least one defect in at least one memory device has occurred while writing said following section of input data into said following page;

E) continuing with functions C) and D) until all sections of input data have been written into said matrix of memory de- vices and into said additional memory device;

F) copying input data stored in corresponding sets of pages of said matrix of memory devices, which sets include per set at least one defect in at least one memory device, to corre^¬ sponding sets of pages in said matrix of memory devices which are not yet occupied with said input data, thereby taking input data of defect single pages not from said ma^¬ trix of memory devices but from corresponding single page data stored in said additional memory device.

Advantageous additional embodiments of the invention are disclosed in the respective dependent claims. Drawings

Exemplary embodiments of the invention are described with reference to the accompanying drawings, which show in: Fig. 1 matrix of flash devices;

Fig. 2 extra buffer containing non-faulty data copies of faulty flash pages; Fig. 3 entry of a defects list; Fig. 4 example defects list; Fig. 5 page register array; Fig. 6 bitmap register; Fig. 7 page replacement sequence.

Exemplary embodiments

It is advantageous for real-time recording to have the flash devices organised within a matrix that is connected by several busses BSO, BSl, BS2, ... to a controller unit CTRLU as depicted in Fig. 1. Several flash devices are sharing the same data bus, for example devices DEVO to DEV2 share bus BSO. More generally, the number of flash devices sharing the same data bus is M. There are several such flash device/ common bus rows in the matrix, their number is N. The matrix includes at least two memory devices per row and at least two memory devices per column. The controller unit CTRLU may receive the high-speed input data to be stored or recorded. Regarding an ^Λerase' operation, the smallest addressable unit in a NAND flash memory like device 1 is a flash block 2 (depicted with a bold surrounding, i.e. in the figure device 1 has four flash blocks) .

Regarding a ^Λwrite' operation, the smallest addressable unit in a NAND flash memory is a flash page 3 (in the figure each flash block contains four flash pages) . In one implementation, the total number of flash blocks in the matrix is e.g. 4096. Each block may contain 64 pages. The input data to be stored are multiplexed and are written via the N parallel buses into the same current page in each of the flash devices in the first column of the matrix, i.e. into device DEVO and the devices arranged below it. After this current page is full, the following input data are written into the same current page in the second column of the matrix, i.e. into device DEVI and the devices arranged below it. This write processing is continued M times until the current page of all flash devices of the matrix is filled with input data. This status is depicted by the diagonal hatching of the second page in the flash devices. Thereafter the write processing is continued with the next (i.e. the third) page in the flash devices, which third page is marked in Fig. 1 by a vertical hatching. These pages form a set of pages SOP.

For achieving a high-speed real-time recording and defect recovery, the data content for the current flash page of all flash devices of the matrix is in each case copied in a sequential manner to an additional memory buffer AMB (e.g. an SRAM) which can be connected to controller unit CTRLU or to the buses, and these data will remain in buffer AMB if one or more defects have occurred in the current page in one or more of the flash devices of the matrix.

The extra buffer AMB is shown in Fig. 2 in more detail. The matrix depicted in Fig. 1 includes nine flash devices. The first column of devices in the matrix is related to the first column in memory AMB, the second column in the matrix is related to the second column in memory AMB, and so on. A line in memory AMB is related to a page in a row of devices in the matrix.

When writing into the third page (marked by vertical hatching) in the flash devices of the matrix an error or defect 5 has occurred. Therefore the original input data content of these pages is kept stored in the corresponding area (marked by vertical hatching) in memory AMB, i.e. it is kept stored in AMB without defect 5. Therefore, when the next series of pages (i.e. the fourth page) is written in the flash devices, the original input data are written into the following section in memory AMB (i.e. lines 3 to 6 in Fig. 2) . In case no defect has occurred in any of the fourth pages, this section (lines 3 to 6) in memory AMB is overwritten by the next series of pages (i.e. the fifth page) . Because three defects 5a, 5b and 5c occur in the tenth page (i.e. in block three of the flash devices) , the original input data content of these pages is kept stored in the corresponding area

(lines 3 to 6) in memory AMB without defects at corresponding locations 5A, 5B and 5C.

In effect, under the control of controller unit CTRLU, buffer AMB stores non-faulty data copies of faulty flash pages but its capacity is significantly smaller than that of the flash matrix. For example, RAM memory AMB can have a capacity such that the data content of up to 15 different pages of each device of the matrix can be stored therein.

The page errors (e.g. 5, 5a, 5b and 5c) which occurred during real-time recording are marked in a defects list, an entry of which defects list is shown in Fig. 3. That entry may contain the block number BLNO (0 ... B) , the page number PGNO (0 ... P), and the device column number DEVO, ..., DEVm in the FLASH matrix. The bits BTO, BTl, ..., BTn in the column number indicate in which row number (= bus number BSO, BSl, ..., BSn) of the matrix a defect or multiple defects have occurred in a flash page. It is not necessary to store the location within a page of a defect.

An example defects list for the nine flash devices depicted in Fig. 1 is shown in Fig. 4. This list can be stored in controller unit CTRLU. This example defects list defines the defect pages in the Fig. 1 matrix. A first defect 5 is located in block number BLNO=O in page number PGNO=2, and according to the bitmap part BTMP in the third device column DEV2 with respect to the second bus BSl.

A second defect 5a is located in block number BLNO=2 in page number PGNO=I in the first device column DEVO with respect to the second bus BSl. A third defect 5b is located in block number BLNO=2 in page number PGNO=I in the second device column DEVI with respect to the second bus BSl.

A fourth defect 5c is located in block number BLNO=2 in page number PGNO=I in the second device column DEVI with respect to the third bus BS2.

Further defects are located in block number BLNO=2 in page number PGNO=3 in the first device column DEVO with respect to the third bus BS2 and in the second device column DEVI with respect to the second bus BSl. Upon or while writing the input data into the flash devices, the flash devices report any defects via the buses BSO to

BS2 to controller unit CTRLU.

The respective flash page copies have to remain buffered. When recovering the defects, it is advantageous that the defects list is analysed in a resource and time efficient manner, to support low power consumption, short operation time and real-time behaviour. Target is that the content of a flash block that contains one or more faulty flash pages is copied to corresponding sets FSOP of free flash pages in a free flash block within the same flash device. At last the faulty flash block has to be logically re-mapped by the new flash block in e.g. a file system. Hereby the task of analysing the defects list that contains information about the flash block, the flash page, device and bus of every defect is described in detail below. During analysing processing, the appropriate defect flash page within a block is to be copied from the buffer to the new flash block. All other flash pages within a block are to be copied from the faulty flash block to the new flash block. Determining defect flash pages of a flash block: a) Initialise a register array for ^Λpage' values with invalid values (Fig. 5 shows a corresponding page register array containing defect pages for flash block BLNO=2, which page register contains the corresponding page number values from column PGNO for the rows concerning BLNO=2 ) ; b) Make the first valid ^Λblock' value BLNO out of the defects list a 'reference block' value; c) Copy the corresponding ^Λpage' value from the defects list into the appropriate field in the page register array; d) Analyse the next defects list entry; e) If the current 'block' value BLNO equals the 'reference block' value go to step c) else go to step d) ; f) Loop steps c) to e) until the end of the defects list is reached.

Fig. 6 shows a bitmap register for storing the bitmaps for the page entries processed in step c) . The bitmaps for these pages are processed in a sequential processing order PRO

(every N bits) . The bitmap register is used to shortcut non- defect flash devices: g) Initialise a pointer for the bitmap and for a 'device counter' ; h) Initialise a pointer for the page register array. Initialise the bitmap register with zeroes; i) Address a single cell in the page register array; j) If its entry is valid go to step k) else go to step 1) ; k) Load N bits from the corresponding bitmap (stored in the defects list) and logically OR that with the corresponding bitmap register values (N=number of busses) ; 1) Increment the page register array pointer and go to step i) until the end of the page register array is reached; m) If the bitmap register value equals zero then increment the bitmap pointer and the 'device counter' and go to step h) until the end of the bitmap is reached. If the bitmap register value not equals zero then start the following steps n) to u) .

Fig. 7 explains a page replacement sequence according to a bitmap register and bitmap analysis. The goal is to determine the bus for a defect block in a defect flash device and to copy corresponding flash pages: n) Initialise a ^Λbus count' and the pointer for the page register array; o) Read the page register array (Fig. 5) for a valid value; p) Analyse the bit in the bitmap register where ^Λbus count' is pointing to: if that bit equals zero, increment ^Λbus count' and go to step o) , if that bit equals one, go to step q) ; q) For all page values between zero and the value read in step o) minus one, copy flash pages from the faulty flash block to a new flash block. The reference flash device number corresponds to value ^Λdevice counter' , the reference bus number corresponds to value ^Λbus count' ; r) For the page value read in step o) , copy the corresponding flash page data from the additional memory buffer AMB to the new flash block. The reference flash device number corresponds to value ^Λdevice counter' , the reference bus number corresponds to value ^Λbus count' ; s) Increment the pointer for the page register array and go to step o) until the end of the page register array is reached; t) Update a ^Λblock remap table' for the appropriate device and mark the corresponding block entry in the defects list as invalid; u) Go to step a) .

The above registers, pointers, list and table can be controlled by controller unit CTRLU.

The invention can be used in any block oriented storage that can be affected with defects during lifetime.

Claims

Cl aims

1. Method for recording high-speed input data into a matrix of memory devices of a first type, said matrix including at least two memory devices per row and at least two mem^¬ ory devices per column, wherein the memory devices (DEVO, DEVI, DEV2 ) of a row are connected to a common bus (BSO) and to each row of said matrix a separate common bus (BSO, BSl, BS2) is assigned, and wherein said memory de- vices each are internally arranged in multiple pages to which pages input data can be written in a sequential manner, and wherein when writing into said first type memory devices defects (5, 5a, 5b, 5c) may occur at dif^¬ ferent locations in said memory devices, said method be- ing characterised by the steps:

A) writing a first section of input data in a multiplexed manner, using said common buses, in the same current page of the memory devices, starting with the first column (DEVO) of memory devices, column by column, and writing this first section of input data also in a corresponding section of an additional memory device (AMB) of a second type different from said first type;

B) checking (CTRLU) whether or not at least one defect (5, 5a, 5b, 5c) in at least one memory device has occurred while writing said first section of input data into said current page of the memory devices;

C) writing the following section of input data in a multiplexed manner, using said common buses, in the following page of the memory devices, starting with the first col- umn (DEVO) of memory devices, column by column, and if no defect has been found in the foregoing step, also writing this following section of input data in the same section of said additional memory device, and if a defect has been found in the foregoing step, also writing this following section of input data in a following corresponding section of said additional memory device ;

D) checking (CTRLU) whether or not at least one defect (5, 5a, 5b, 5c) in at least one memory device has occurred while writing said following section of input data into said following page;

E) continuing with steps C) and D) until all sections of input data have been written into said matrix of memory devices and into said additional memory device (AMB) ;

F) copying input data stored in corresponding sets of pages (SOP) of said matrix of memory devices, which sets include per set at least one defect in at least one memory device, to corresponding sets of pages (FSOP) in said matrix of memory devices which are not yet occupied with said input data, thereby taking input data of defect sin- gle pages not from said matrix of memory devices but from corresponding single page data stored in said additional memory device (AMB) .

2. Apparatus for recording high-speed input data into a ma- trix of memory devices of a first type, said matrix including at least two memory devices per row and at least two memory devices per column, wherein the memory devices (DEVO, DEVI, DEV2 ) of a row are connected to a common bus (BSO) and to each row of said matrix a separate common bus (BSO, BSl, BS2) is assigned, and wherein said memory devices each are internally arranged in multiple pages to which pages input data can be written in a sequential manner, and wherein when writing into said first type memory devices defects (5, 5a, 5b, 5c) may occur at dif- ferent locations in said memory devices, said apparatus including an additional memory device (AMB) of a second type different from said first type and means (CTRLU, BSO, BSl, BS2) being adapted for carrying out the following functions: A) writing a first section of input data in a multiplexed manner, using said common buses, in the same current page of the memory devices, starting with the first column of memory devices (DEVO), column by column, and writing this first section of input data also in a corresponding section of said additional memory device (AMB) ; B) checking whether or not at least one defect (5, 5a, 5b, 5c) in at least one memory device has occurred while writing said first section of input data into said current page of the memory devices; C) writing the following section of input data in a multi- plexed manner, using said common buses, in the following page of the memory devices, starting with the first column of memory devices (DEVO), column by column, and if no defect has been found in the foregoing function, also writing this following section of input data in the same section of said additional memory device, and if a defect has been found in the foregoing function, also writing this following section of input data in a following corresponding section of said additional memory device; D) checking whether or not at least one defect (5, 5a, 5b, 5c) in at least one memory device has occurred while writing said following section of input data into said following page;

E) continuing with functions C) and D) until all sections of input data have been written into said matrix of memory devices and into said additional memory device (AMB) ;

F) copying input data stored in corresponding sets of pages (SOP) of said matrix of memory devices, which sets include per set at least one defect in at least one memory device, to corresponding sets of pages (FSOP) in said matrix of memory devices which are not yet occupied with said input data, thereby taking input data of defect single pages not from said matrix of memory devices but from corresponding single page data stored in said additional memory device (AMB) .

3. Method according to claim 1, or apparatus according to claim 2, wherein said first type memory devices are FLASH memories .

4. Method according to claim 1, or apparatus according to claim 2, wherein said defects are stored in a defects list that contains information items about the corresponding page, the corresponding memory device and the corresponding bus for each defect.

5. Method or apparatus according to claim 3, wherein said defects are stored in a defects list that contains information items about the corresponding block, the corresponding page, the corresponding memory device and the corresponding bus for each defect.

6. Method or apparatus according to claim 5, wherein defect flash pages of a flash block are determined as follows: a) initialising a register array for ^Λpage' values with in- valid values; b) making the first valid 'block' value BLNO out of the defects list a 'reference block' value; c) copying the corresponding ^Λpage' value from the defects list into the appropriate field in said page register ar- ray; d) analysing the next defects list entry; e) if the current 'block' value BLNO equals the 'reference block' value, continuing with step c) else continuing with step d) ; f) continuing steps c) to e) until the end of said defects list is reached.

7. Method or apparatus according to claim 6, wherein a bitmap register for storing the bitmaps for the page entries processed in step c) is generated and every N bits of the bitmaps for these pages are processed in a sequential processing order (PRO) and said bitmap register is used to shortcut non-defect flash devices, said bitmap register being generated as follows: g) initialising a pointer for the bitmap and for a ^Λdevice counter' ; h) initialising a pointer for said page register array and initialising said bitmap register with zeroes; i) addressing a single cell in said page register array; j) if its entry is valid, continuing with step k) else con- tinuing with step 1) ; k) loading N bits from the corresponding bitmap stored in said defects list and logically ORing that with the corresponding bitmap register values;

1) incrementing the page register array pointer and continu- ing with step i) until the end of said page register array is reached; m) if the bitmap register value equals zero, incrementing the bitmap pointer and said ^Λdevice counter' and continuing with step h) until the end of the bitmap is reached.

8. Method or apparatus according to claim 7 wherein, if in step m) said bitmap register value not equals zero, the following steps are carried out in order to determine the bus for a defect block in a defect flash device and to copy corresponding flash pages: n) initialising a ^Λbus count' and the pointer for said page register array; o) reading said page register array for a valid value; p) analysing the bit in said bitmap register where ^Λbus count' is pointing to: if that bit equals zero, incrementing ^Λbus count' and continuing with step o) , if that bit equals one, continuing with step q) ; q) for all page values between zero and the value read in step o) minus one, copying flash pages from the faulty flash block to a new flash block, whereby the reference flash device number corresponds to value ^Λdevice counter' and the reference bus number corresponds to value ^Λbus count' ; r) for the page value read in step o) , copying the corresponding flash page data from said additional memory buffer (AMB) to the new flash block, whereby the reference flash device number corresponds to value ^Λdevice counter' and the reference bus number corresponds to value ^Λbus count' ; s) incrementing the pointer for said page register array and continuing with step o) until the end of said page register array is reached; t) updating a ^Λblock remap table' for the appropriate device and marking the corresponding block entry in said defects list as invalid; u) continuing with step a) in claim 6.