WO2007077059A1

WO2007077059A1 - Ring oscillator arrangement having time quanta which are shortened in comparison with gate operating times

Info

Publication number: WO2007077059A1
Application number: PCT/EP2006/068893
Authority: WO
Inventors: Siegbert Steinlechner; Andreas Tritschler
Original assignee: Robert Bosch Gmbh
Priority date: 2005-12-30
Filing date: 2006-11-24
Publication date: 2007-07-12
Also published as: DE102006010906A1

Abstract

In a ring oscillator arrangement having at least three first oscillator elements (200-210) forming an oscillator ring, provision is made in particular for at least one of the at least three first oscillator elements (200-210) to be connected to a delay chain formed from second oscillator elements (215-235, 240-270, 275-300), wherein, by means of the outputs of at least one of the at least three first oscillator elements (200-210), not only the respectively following first oscillator element (205, 210, 200) but also the respectively associated delay chain (215-235, 240-270, 275-300) are excited, and, by means of suitable taps (,1'-,2<SUP>n'</SUP>) at the oscillator ring (200-210) and at the delay chains (215-235, 240-270, 275-300), a temporal resolution capacity is provided which corresponds to fractions of the gate operating times.

Description

description

title

Ring oscillator arrangement with respect to the gate transit times shortened time quanta

State of the art

The invention relates generally to the technical field of analog / digital converters and, more particularly, to a ring oscillator arrangement particularly for use in such converters according to the preamble of claim 1.

In analog-to-digital converters (ADCs) and digital time-measuring methods (time-to-digital converters), ring oscillators consisting of digital basic components (inverters, NAND, NOR, etc.) are used.

The underlying conversion processes in both cases are based on one

Timing principle and use the duration of the gates as Zeitquantum. The gate transit time of the basic digital components therefore determines the temporal resolution of the converter.

It is therefore desirable to improve a ring oscillator arrangement mentioned at the beginning in such a way that time quants shortened in comparison to the prior art are made possible, wherein the minimum time quantum is in particular no longer limited by the propagation delay of the gates used in the ring oscillator. In other words, it should be achieved that the gate transit time no longer determines the temporal resolution of the respective underlying converter. This results in a refinement of the temporal resolution of the respective converter over the prior art.

The ideal case is a scalable temporal resolution. In addition, a ring oscillator arrangement according to the invention should preferably use only functionally similar circuit elements in order to ensure or improve the linearity of the respective converter. In addition, a minimal effort in the calculation of the duration of the measurement from the counter value of a circulation counter and the ring oscillator state is to be made possible.

Disclosure of the invention

Advantages of the invention

According to the invention, both the respective follower element in the oscillator ring and an additionally arranged delay chain are excited by means of the outputs of each oscillator element of a conventional ring oscillator. Therefore, a respective signal edge propagates both in the oscillator ring and in the delay chains and allows a temporal by means of suitable taps in the oscillator ring and in the delay chains

Resolution, which corresponds to fractions of the usual gate transit times.

Technologically limited minimum gate delays thus no longer limit the temporal resolving power of the ring oscillator according to the invention or of a converter formed therefrom. The temporal resolution capability is also arbitrarily finely scalable, wherein the scalability is limited only by the respectively achievable temporal precision of the gate modules. In addition, identical delay elements (gates) can be used, whereby they have a matching delay and drift behavior and thus improve the linearity of the converter.

The ring oscillator arrangement according to the invention can preferably be implemented in a converter as described above, thereby enabling the realization of improved A / D converters or time measuring methods compared to the prior art. It should be noted, however, that the field of application is not limited in principle to the aforementioned converter and also all other possible electronic as well as non-electronic

Applications in which signals or time intervals are to be converted by means of a ring oscillator. Short description of the drawing

The invention will be explained in more detail below with reference to the accompanying drawings, with reference to embodiments.

In the drawing show

1 shows a basic electronic circuit of logic elements of a ring oscillator with circulation counter according to the prior art;

FIG. 2 shows a first exemplary embodiment of the ring oscillator according to the invention with N _R = 3 and 2 ⁿ = 8, with possible state transitions; FIG.

Fig. 3 shows a second embodiment of the ring oscillator according to the invention for differential

Logic with N _R = 2 and 2 ⁿ = 8, also with possible state transitions.

Embodiments of the invention

A ring oscillator according to the prior art serving as the starting point, equipped with three inverters 100-110 and one circulating counter 115, is shown in FIG. If, at the input of one of the three inverters 100-110, a change in the logic level occurs, e.g. from logic "low" to "high", this edge causes the respective inverter 100-110 to switch its output from logic "high" to "low". After passing through all the inverters 100-110, the edge again occurs at the input of the first inverter 100.

Due to the odd number of inverters 100-110 and the associated odd number of inverses, the edge profile after a passage of the three inverters 100-110 is now from logic "high" to "low" and thus vice versa to the edge described in the previous paragraph. The edge thus propagates infinitely long through the inverter ring 100.

110, causing the ring oscillator to oscillate. The said characteristic of the edge inversion after one revolution is even necessary so that the ring 100-110 is not in a stable state - A -

Condition falls. For a ring of an even number of inverters, after one revolution, the edge would not cause an inversion at the input of the first inverter 100, thereby keeping the inputs and outputs of all inverters at their logic levels. An odd number of inversions is thus necessary to maintain oscillation. In the case of an oscillation, the sequence repeats after two edge revolutions. The period of

Oscillation is consequently formed by two flank rounds.

In a time measurement, the edge is started by triggering mechanisms (NAND or NOR elements). The outputs of the logic gates are sampled at a stop signal. Due to the sampled outputs of the logic gates, the phase of the oscillation for

Sampling time to be determined. Here, a quantization (decision) of the analog sampled signal level of the inverter outputs either to "high" or to "low". The resulting logic levels of the inverter outputs form the state of the ring oscillator at the instant of sampling. Since one period consists of two edge revolutions, the number of possible states of the ring oscillator corresponds to twice the number of gates. These states divide the period of the oscillator into time quanta corresponding to the gate delay.

As can be seen from FIG. 1, the number of cycles passed through is counted by means of the circulation counter 115. Also, the circulation counter 115 is scanned at a stop signal. Therefore, one multiplies the current count (i.e., value) of the circulating counter

115 with twice the number of gates and adds the ring condition corresponding number of additional switched gate in the ring, the result is the total number of gates that have switched during the measurement. Finally, the quantized time period results from the multiplication of this total number with the gate transit time (time quantum).

The following numerical example is intended to further clarify these relationships. It is assumed that the edge has already completely passed through the oscillator ring 100-110 during a measurement, whereby the circulation counter 115 has the value '2'. At the time of sampling the oscillator ring 100-110, the edge has already traversed three additional gates. Further, the gate delay of a single gate is 2 ns. These assumptions result in:

Total number of gates crossed = 2 6 + 3 = 15 gates

Quantized time = 15 2 ns = 30 ns

When used in ADCs, the runtime of the gates is current or voltage dependent. By the number of gates connected during a known period of time, the applied voltage can be determined. The procedure in this application is based on the time measurement method.

The edge states of ring 100-110 subdivide one round of finer one. The ring state can therefore be interpreted as the fractional part of the count value of the circulation counter. Since the binary number system is usually used in digital technology, it is advantageous if the number of states of the ring oscillator corresponds to a power of two (2 ⁿ ). In this case, the binary representation of the ring state can be attached directly to the binary value of the circulation counter, whereby a complex calculation is omitted, because it applies in this embodiment:

Total number of gates crossed = circulating counter value 2 ⁿ + ring condition;

0 <= ring condition <= 2 ⁿ -l.

The resulting requirement for an even number of ring states can be fulfilled, for example, by the two-edge systems known per se. In a two-flank system, two flanks with mutually inverse flank sense are simultaneously in circulation. If one edge causes the gate to switch from logic "high" to "low", the other edge forces this element from logic "low" to "high". Oscillation can thus be maintained with an even number of gates. Since ring oscillators consist exclusively of combinatorial elements, the two can be used in a two-flank system Extinguish flanks. This occurs, for example, when the rising edge rotates faster than the falling edge and thus catches up after a certain time. As a result, the system would assume a stable, non-oscillating state. In order to maintain an oscillation, there exist methods which prevent extinction by synchronizing the edges. In all arrangements must be ensured that each

Delay element as possible causes the same time delay, so that the refinement of a period is approximately equidistant (linearity of the characteristic). An additional wiring for the synchronization increases the implementation effort. Furthermore, the delay behavior of individual gates is affected, which affects the linearity.

A first embodiment of the ring oscillator arrangement according to the invention is shown in FIG. 2 and, for the reasons mentioned above, preferably also consists of an odd number N _R of inverters (NAND, NOR if initialization required). The arrangement according to the invention therefore fulfills the above-described oscillation condition for

Einflankensysteme.

The outputs of each oscillator ring element 200-210 excite respectively the corresponding follower element 205, 210 and 200 in the oscillator ring 200, 205, 210 and a respective delay chain 215-235, 240-270 and 275-300

Oscillator ring 200-210 and in delay chains 215-300.

In FIG. 2, the numbers '1' to '8' (generally 2 ⁿ ) represent the signal taps relevant for the evaluation of the oscillator state. The duration of the individual chain elements T _κ of the three delay chains 215-300 is the time difference _Δ t = T _κ T _R is greater than in the

Ring elements 200 - 210 selected. Relative to the time of an edge change at the position '1' in the ring, after the time interval _Δt an edge change takes place at position '2' in the second delay chain 240-270.

At the other marked positions, 3 'to, 8' occurs successively in time, as by the

Arrows indicated, after multiples of _Δ t also an edge change. The interval _.DELTA.t is chosen in the embodiment so that 2 ⁿ intervals a flank circulation T _F of Match ring. By the time points of the edge changes at the positions, 1 'to, 2 ⁿ , a flank circulation is divided equidistantly into 2 ⁿ intervals.

The type of edge change (rising or falling) is identical within a flank revolution at all positions, 1 'to 2 ⁿ . As a result, when scanning the signal taps to this

Positions, 1 'to, 2 ⁿ ' the corresponding interval are identified by simple decoding and converted into a binary number representation. Since there are 2 ⁿ intervals in total, the resulting result can be directly appended to the binary value of the circular counter 115 (not shown in FIG. 2) (see FIG. 1). This composite binary value represents the total number of time quanta _Δt elapsed during the measurement period.

After two edge revolutions of the ring, the ring oscillator arrangement shown in FIG. 2 is again in the same state.

The following chronological relationships apply accordingly:

For the period: T _P = 2 T _F = 2 N _R T _R = 2 T _Δ t = 2 T (T _K - T _R )

It follows that 2 ⁿ T _κ = (2 ⁿ + N _R ) T _R

This relationship is used in the present embodiment for setting the

Run-time difference _Δ t used. If one selects another ring inverter output for the position '1', ie the output of the inverter 200 or 205, this results in turn in other positions '2' to '2 ⁿ ', by which a flank rotation shifted by T _{R is} subdivided. Overall, there are N _R possibilities which are shifted from each other by T _R.

Throughout the ring oscillator 200 - a edge change 300 on each - 300 Thus the length _{Δ Ϊ} / N _R occurs after each interval to an output of the inverter 200th However, to divide an edge round into a power of two of sub-intervals, only every N _R -th output is used. The temporal resolution can theoretically be arbitrarily fine adjusted by the choice of the transit time difference. It is sufficient to use one of the N _R options to achieve a desired temporal resolution. The exemplary embodiment of the ring oscillator according to the invention shown in FIG. 2 can be dimensioned arbitrarily by the choice of the parameters N _R and n. Thus, further variants of the ring oscillator shown in FIG. 2 are possible. If one of the three delay chains 215-300 is lengthened, the result is sufficient if the length is sufficient

Edge change in the rear part of this extended delay chain and in the front part of a different delay chain. It can be shown that a correspondingly long delay chain alone is sufficient to cover all times of the edge changes of the ring oscillator 200-300 shown in FIG. 2, which results in a further variant of the ring oscillator arrangement according to the invention.

The second embodiment relates to ring oscillators with differential logic. The circuit elements of such oscillators each have two inputs and outputs. The logic signal (above-described "edge signal") is interpreted by the formation of the difference signal of the two outputs. By interchanging the nodes in the difference formation, an inversion of the signal can be achieved without a modification of the respective circuit element being necessary.

This makes it possible to construct a ring oscillator according to the invention with an even number of identical circuit elements. In order to be able to resolve fractions of gate delays in this exemplary embodiment, the above-described delay chains are used even more efficiently in the case of the differential ring oscillators than in the first exemplary embodiment. For this purpose, instead of an edge rotation, the gate transit time of the ring elements is subdivided into 2 ⁿ intermediate intervals. The quotient of T _R and _Δ t thus results in 2 ⁿ .

The following temporal relationships result from this arrangement:

For the gate transit time of the ring elements: T _R = 2 ⁿ _Δ t = 2 ⁿ (T _{k -T} _R )

From this follows: 2 ⁿ T _κ = (2 ⁿ + 1) T _R Also in this exemplary embodiment, the transit time difference is adjusted on the basis of this relationship. A concrete embodiment of this arrangement for dimensioning the ring oscillator in differential logic is shown in FIG.

Also in FIG. 3, the sequence of state transitions during a gate transit time T _{R is} indicated by means of arrows. In contrast to the conventional digital logic, due to the refinement of the gate delay time, each gate output of an oscillator ring formed from four oscillator elements 400-415 for connection to a respective one of seven delay elements, and preferably from the functionally identical oscillator elements (such as 400-415). formed delay chain 420 -

450, 455-485, 490-520 and 525-555. This further improves the temporal resolving power. This ring oscillator arrangement can also be scaled arbitrarily by means of the variables N _R and n. Likewise, the times of the edge changes of other delay chains can be covered by a corresponding extension of a single delay chain.

The dimensioning provisions of the above-described arrangements lead to time quanta _Δt , which represent integer multiples of the gate transit time T _R divided by a power of two (see following equations). When determining the quantized time span, the number of elapsed time quanta _{Δt is} determined instead of the number of elapsed gate transit times. Characteristic for the use of this principle is that the quantization of the measurement duration is smaller than the technologically achievable gate running time T _R. As soon as the above-mentioned dimensioning rules are applied, the temporal quantization results according to the following equations:

Conventional digital logic: _Δt / T _R = N _R / 2 ⁿ

Differential logic: _Δ t / T _R = 1/2 ⁿ The ring oscillator arrangements shown in FIGS. 2 and 3 can be used for time measurements in the sub-nanosecond range with start and stop signals. The limit of temporal resolving power is determined by the technologically achievable precision of the described delay difference. The erfϊndungsgemäße ring oscillator is particularly suitable for radar applications, since the presented ring oscillator arrangements

Allow or support time measurements with one start and several stop times. As a result, reflections can be detected at several objects within a measuring cycle and can be deduced from the measured transit times at their distances.

In principle, the ring oscillator arrangement according to the invention can also be used in AD converters which are based on the time measurement principle or based. Here, however, the appropriate voltage dependence of the two maturities must be ensured, to which, however, will not be discussed here. It should only be noted that the conversion rate can be increased with the same bit width due to the finer time resolution compared to the prior art.

Claims

claims

A ring oscillator arrangement comprising at least three first oscillator elements (200 - 210, 400 - 415) forming an oscillator ring, characterized in that at least one of the first three oscillator elements (200 - 210, 400 - 415) is connected to one of second oscillator elements (215 - 235 , 240-270, 275-300, 420-450, 455-485, 490-520 and 525

- 555) is formed, wherein by means of the outputs of at least one of the at least three first oscillator elements (200 - 210, 400 - 415) the respective subsequent first oscillator element (205, 210, 200, 405, 410, 415, 400) and the respectively associated delay chain (215-235, 240-270, 275-300, 420-450, 455-485, 490-520, and 525-555) are energized, and wherein by means of suitable taps (, V-, ²ⁿ ') on the

Oscillator ring (200-210, 400-415) and to the delay chains (215-235, 240-270, 275-300, 420-450, 455-485, 490-520 and 525-555) a temporal resolving power is provided which Fractions of the gate transit times.

2. Ring oscillator arrangement according to claim 1, characterized in that the first

Oscillator elements (200-210, 400-415) and the second oscillator elements (215-235, 240-270, 275-300, 420-450, 455-485, 490-520 and 525-555) are formed of functionally similar circuit elements.

3. ring oscillator arrangement according to one of the preceding claims, characterized in that the duration of the second oscillator elements of the delay chains (215

- 300, 420 - 555) by a time difference _.DELTA.t = T _κ -T _{R is} greater than the single-term of the at least three first oscillator elements of the oscillator ring (200 - 210, 400 - 415) is selected.

4. ring oscillator arrangement according to claim 3, characterized in that the interval _.DELTA.t is selected so that 2 ⁿ intervals corresponding to a flank rotation T _F of the oscillator ring circulating signal.

5. ring oscillator arrangement according to claim 4, characterized in that the positions, 1 'to, 2 ⁿ are chosen so that by the times of the edge change at the positions, 1' to, 2 ⁿ a flank circulation equidistantly divided into 2 ⁿ intervals.

6. ring oscillator arrangement according to one of the preceding claims, characterized in that by sampling the signal taps at the positions, 1 'to, 2 ⁿ ' the corresponding interval is identified by decoding and converted into a binary number representation.

7. ring oscillator arrangement according to one of the preceding claims, in particular under

Use of conventional digital logic, characterized in that only every N _R -th output of the delay elements (200-300) is used for sampling.

8. ring oscillator arrangement according to one of the preceding claims, in particular using differential logic, characterized in that the first

Oscillator elements (400-415) and the second oscillator elements (420-555) operate with differential logic and each have two inputs and outputs, wherein each of the difference signal of the two outputs is formed and wherein by interchanging nodes in the difference formation, an inversion of the signal he follows.

9. ring oscillator arrangement according to claim 8, characterized by functionally similar circuit elements (400 - 555), wherein the gate delays of the first oscillator elements are divided into every 2 ⁿ intermediate intervals.

10. converter, characterized by at least one ring oscillator arrangement according to one of the preceding claims.