WO2007071556A1 - Multiple quantum well devices - Google Patents

Multiple quantum well devices Download PDF

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Publication number
WO2007071556A1
WO2007071556A1 PCT/EP2006/069342 EP2006069342W WO2007071556A1 WO 2007071556 A1 WO2007071556 A1 WO 2007071556A1 EP 2006069342 W EP2006069342 W EP 2006069342W WO 2007071556 A1 WO2007071556 A1 WO 2007071556A1
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WIPO (PCT)
Prior art keywords
layer
conducting
pit
layers
conducting layer
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PCT/EP2006/069342
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French (fr)
Inventor
Yasunao Katayama
Dennis Newns
Chang Chyi Tsuei
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International Business Machines Corporation
Ibm United Kingdom Limited
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Application filed by International Business Machines Corporation, Ibm United Kingdom Limited filed Critical International Business Machines Corporation
Priority to JP2008546350A priority Critical patent/JP5203963B2/en
Priority to EP06830388A priority patent/EP1974388B1/en
Priority to CN200680042099.5A priority patent/CN101305467B/en
Publication of WO2007071556A1 publication Critical patent/WO2007071556A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/937—Single electron transistor

Definitions

  • the present invention relates to semiconductor devices and methods of fabricating the same. More particularly, the present invention relates to multiple quantum well devices, eg coupled quantum well devices (CQWD) containing two or more direct and selective contacts, and methods of fabricating such devices.
  • CQWD coupled quantum well devices
  • Coupled quantum well devices such as those described, for example, in A. Palevski, et al . "Resistance Resonance in Coupled Potential Wells", Physical Review Letters, Vol. 65, No. 15, pg. 1929 (1990), Y. Katayama, et al . "Lumped Circuit Model of Two-Dimensional Tunneling Transistors,” Appl . Phys. Lett. Vol. 62, No. 20, pg. 2563 (1993), J.A. Simmons, et al .
  • CQWD Coupled quantum well devices
  • a CQWD contains two quantum well layers that are separated by a thin barrier layer.
  • Each quantum well layer includes a very thin sheet of 2-dimensional electron gas (2DEG) that lies in the xy plane.
  • 2DEG 2-dimensional electron gas
  • the two 2DEG sheets are superimposed at different positions along the z axis, with a narrow tunneling gap between them.
  • the energy levels in these two 2DEG sheets are degenerate (i.e., their quantum states share the same quantum numbers) , they are coupled strongly due to the mter-sheet tunneling effect.
  • tunneling coupling falls off, and the energy difference becomes comparable with the mter-sheet matrix element, forming a simple switching device.
  • CQWDs which use quantization of single particle states locally, constitute a preliminary step towards computing with quantum systems.
  • the multiple quantum well layers are typically connected in parallel, i.e., by the same set of electrodes that simultaneously contact all the quantum well layers, due to difficulties in making selective contact to the individual quantum wells.
  • the quantum wells are either operated in parallel, or series operation can be indirectly achieved by using additional top and bottom turn-off electrodes .
  • Figure IA illustrates a prior art CQWD structure 10 with two quantum well layers 12 and 14, which are spaced apart by a very thin barrier layer 16. Suitable doping is provided to establish a 2DEG sheet in each well. Standard diffused-in contacts 18 and 20 are provided, each of which contacts both quantum well layers 12 and 14 simultaneously. Additional turn-off electrodes 22 and 24 are respectively fabricated on the top and bottom surfaces of the CQWD structure. Application of a negative bias potential Vt to the top turn-off electrode 22 will result in depletion of the electrons within the quantum well regions that are underneath the electrode 22. For small -Vt, the depletion only occurs within a region in the upper quantum well layer 12.
  • top turn-off bias voltages exists in which the two ohmic contacts 18 and 20 are electrically connected together only via the lower quantum well layer 14.
  • the bottom turn-off electrode 24 can be negatively biased by a voltage -Vb, so that the lower quantum well layer 14 above it is fully depleted but the upper quantum well layer 12 is not.
  • the top and bottom turn-off electrodes 22 and 24 can be suitably biased to provide a condition in which the contacts 18 and 20 are electrically disconnected from each other by the depleted regions in the upper and lower quantum well layers 12 and 14, as shown in Figure IB.
  • the contacts 18 and 20 are not selectively contacted with the individual quantum well layers 12 and 14. Instead, they are simultaneously contacted with both quantum wells, and the top and bottom turn-off electrodes 22 and 24 must be employed to selectively deplete regions in the quantum well layers 12 and 14, in order to indirectly establish selective electrical connection between contacts 18 and 20 and quantum well layers 14 and 12, respectively.
  • top and bottom turn-off electrodes of the prior art CQWD are functionally and structurally clumsy. Further, they are limited to 2- layer structures, which is not suitable for computer applications.
  • the present invention provides direct and selective contacts for individual quantum wells in device structures that contain multiple quantum wells, such as CQWDs.
  • the present invention relates to a device structure that contains: (i) two or more conducting layers; (ii) two peripheral insulating layers; (in) one or more intermediate insulating layers; and (iv) two or more conductive contacts.
  • the two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers .
  • the conducting layers form quantum wells for quantum-mechanical confinement of free electrons therein, and each of the two or more conductive contacts is directly and selectively connected with one of the conducting layers.
  • the device structure of the present invention does not contain any top or bottom turn-off electrode, and is therefore particularly suitable for uses in computer circuits.
  • the device structure of the present invention has a first surface and a second, opposite surface, and the conductive contacts in the device structure each have a terminal that is located on the first surface, but not the second surface, of the device structure.
  • the quantum wells embedded in the device structure can be directly and selectively accessed from one side of the device structure, which further reduces the amount of interconnects required for integrating such a device structure into a computer circuit and simplifies the overall structure .
  • the device structure of the present invention may be a two-layer structure that comprises two conducting layers separated by one intermediate insulating layer, with two conductive contacts that each directly and selectively connects with one of the two conducting layers.
  • the device structure of the present invention may be a three-layer structure that comprises three conducting layers separated by two intermediate insulating layers, with three conductive contacts that each directly and selectively connects with one of the three conducting layers.
  • the device structure may comprise four, five, six, or even a greater number of conducting layers, which are separated by a plurality of intermediate insulating layers. The exact number of conducting layers in the device structure of the present invention is determined by its specific application.
  • the device structure of the present invention preferably comprises a CQWD, but alternatively, it may comprise any other quantum-well-based structure that contains multiple quantum well layers, including, but not limited to: quantum well lasers, quantum well photodetectors, quantum well solar cells, light-emitting diodes containing multiple quantum wells, quantum well micro-resonators, etc. More preferably, the device structure comprises a static memory cell, which uses alternatively coupled quantum wells for information storage, which will be described in greater details hereinafter.
  • the present invention relates to a method for forming a device structure as described hereinabove by: providing a precursor structure that contains: (i) two or more conducting layers, (ii) two peripheral insulating layers, and (in) one or more intermediate insulating layers, where the two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers, forming two or more quantum wells for quantum-mechanical confinement of free electrons; and fabricating two or more conductive contacts in the precursor structure, wherein each of the conductive contacts is directly and selectively connected with one of the two or more conducting layers, thereby forming a device structure having direct and selective contacts for quantum wells.
  • a process that includes a combination of lithography, ion millmg/reactive ion etching (RIE) , selective wet etching, and oblique angle thin-film deposition steps is employed for fabricating conductive contacts in a precursor structure that contains GaAs/GaAlAs-based quantum wells.
  • RIE reactive ion etching
  • a process that includes a combination of lithography, ion milling/RIE, and thin-film regrowth steps is employed for fabricating conductive contacts in a precursor structure that contains CdF2/CaF2-based quantum wells.
  • the present invention relates to a coupled quantum well structure that contains: (i) two or more quantum wells that are arranged and constructed for tunneling coupling at degenerate energy levels, and (ii) two or more conductive contacts, each of which is directly and selectively connected with one of the quantum wells.
  • the present invention relates to a memory cell that contains: a plurality of insulating layers; at least first, second and third conducting layers spaced apart by the insulating layers, wherein quantum-mechanical confinement of free electrons exists in each of the first, second and third conducting layers; at least first, second and third electrodes, which are directly and selectively contacted with the first, second and third conducting layers respectively; a first voltage applicator for applying a predetermined voltage between the first and third conducting layers through the first and third electrodes, in such a manner that no tunneling current flows directly between the first and third conducting layers; and a second voltage applicator for applying a variable voltage to the second conducting layer through the second electrode, in such a manner that a tunneling current can flow either between the first and second conducting layers, defining a first memory state, or between the second and third conducting layers, defining a second, different memory state.
  • Figures IA and IB shows an exemplary prior art CQWD structure that contains top and bottom turn-off electrodes for selective depletion of quantum wells.
  • Figures 2A-2I illustrates the processing steps for fabricating a conductive contact that is directly and selectively connected with a bottom quantum well layer of a two-layer CQWD structure, according to one embodiment of the present invention.
  • Figures 3A-3E illustrates the processing steps for fabricating a conductive contact that is directly and selectively connected with a top quantum well layer of a two-layer CQWD structure, according to one embodiment of the present invention.
  • Figure 4A shows the cross-sectional view of an exemplary two-layer CQWD structure, according to one embodiment of the present invention.
  • Figure 4B shows the top view of the two-layer CQWD structure of Figure 4A.
  • Figure 5 shows a prior art static memory cell that contains three quantum well layers, as described in U.S. Patent No. 5,625,589.
  • Figure 6 shows the cross-sectional view of an exemplary three-layer structure that contains three quantum well layers with a direct and selective contact to each quantum well layer, according to one embodiment of the present invention.
  • Figures 7A and 7B show schematic views of contact configurations with enlarged contact areas, according to one embodiment of the present invention.
  • Figures 8A-8K illustrates the processing steps for fabricating conductive contacts that are directly and selectively connected with respective top and bottom quantum well layers of a two-layer CQWD structure, according to one embodiment of the present invention.
  • Figure 9 shows the cross-sectional view of an exemplary three-layer structure that contains three quantum well layers with a direct and selective contact to each quantum well layer, according to one embodiment of the present invention.
  • direct and selective contact refers to an electrode or an electric conductor that is in direct, physical contact with a specific conducting layer, but is completely isolated from, and does not in any manner touch, or make any physical contact with, any other conducting layer or any portion thereof.
  • substantially aligned refers to alignment of two layers or two surfaces along a specific direction, with an offset of less than ⁇ 30 A along the specific direction.
  • the device structure contains two or more conducting layers sandwiched between two peripheral insulating layers and further spaced apart from one another by one or more intermediate insulating layers .
  • Each conducting layer forms a quantum well, i.e., it is arranged and constructed in conjunction with its adjacent insulating layers for quantum-mechanically confining free electrons in one dimension, forcing them to occupy a planar region within or near the conducting layer.
  • the width of this region is on the order of the de Broglie wavelength of the electrons, leading to quantized sub-bands.
  • conducting and insulating are used herein in a relative sense, i.e., insulating layers or insulating materials are characterized by wider band gaps than those of the conducting layers or conducting materials. Therefore, in the present invention, what is normally considered a semiconductor can be referred to herein as either a conducting layer or a conducting material, if it is adjacent to a material layer of a wider band gap, or an insulating layer or an insulating material, if it is adjacent to a material layer of a narrower band gap.
  • the conducting layers and the insulating layers may comprise any suitable materials, such as group IV semiconductors (which include, but are not limited to: Si, Ge, C, SiGe, SiC, etc.), groups IH-V, H-VI, and IV-V compound semiconductors (which include, but are not limited to: GaAs, GaAlAs, GaAlAsSb, GaAsSb, GaAlPSb, GaAlSb, GaAlInSb, GaSb, InAs, InAlAs, InGaAs, InGaP, InP, InAsP, InAlAsSb, InAlSb, InAsSb, InSb, AlAs, AlAsSb, AlSb, TlInP, TlInGaP, TlInGaAs, AfInAs, AfInAsSb, GaN, AlGaN, and InGaN, InGaAlN, InN, AlN, CdS, C
  • the conducting/insulating layers preferably comprise materials selected from the group IH-V compound semiconductor family which consists of: GaAs/AlGaAs, GaAs/GalnP, GaAs/AlAs, GaInAs/AlGaAs (AlAs, GaInP), InAsP/AHnAs, InAsP/AlGaAsSb, GaInAs/AlInAs (AlAsSb, AlInAsSb, AlGaAsSb, InP), TlInP(TlGaInP, TlGaInAs) /AlInAs (AlAsSb, AlInAsSb, AlGaAsSb, InP, AlGaPSb) , GaAsSb/InP (AlInAs, AlAsSb, AfInAsSb, AlGaAsSb, AlGaPSb), InAs/AlGaAsSb (A
  • the device structure of the present invention comprises GaAs-based conducting layers and GaAlAs-based insulating layers.
  • a preferred embodiment of the present invention provides a device structure that contains multiple CdF2-based conducting layers that are isolated by CaF2- based insulating layers.
  • the device structure is supported by a suitable substrate, which may comprise a substrate material such as Si, GaAs, InP, GaN, AIN, SiC and sapphire.
  • a substrate material such as Si, GaAs, InP, GaN, AIN, SiC and sapphire.
  • the substrate contains semi-insulatmg GaAs for supporting GaAs/GaAlAs-based quantum well structures.
  • the substrate contains Si for supporting CdF2/CaF2-based quantum well structures.
  • the conducting and the peripheral insulating layers have an average thickness of from about 5 A to about 500 A, and the intermediate insulating layers have an average thickness of from about 5 A to about 200 A.
  • thickness of the conducting and insulating layers may differ significantly for the GaAs/GaAlAs-based structures and the CdF2/CaF2-based structures.
  • the conducting layers are preferably characterized by an average thickness from about 30 A to about 300 A, more preferably about 140 A.
  • the two peripheral insulating layers are preferably characterized by an average thickness from about 100 A to about 500 A, more preferably about 250 A.
  • each of the peripheral insulating layers preferably contains a thin layer of dopant for forming the 2DEG sheets.
  • the intermediate insulating layers are preferably characterized by an average thickness from about 20 A to about 100 A, more preferably about 40 A.
  • the conducting layers are preferably characterized by an average thickness from about 10 A to about 80 A, more preferably about 40 A.
  • the two peripheral insulating layers are preferably characterized by an average thickness from about 100 A to about 500 A, more preferably about 250 A.
  • the intermediate insulating layers are preferably characterized by an average thickness from about 5 A to about 20 A, more preferably about 9 A.
  • the device structure contains direct and selective contacts to the individual conducting layers.
  • Such contacts may comprise any suitable conductive material, including, but not limited to: Cu, Al, Au, Ag, Pt, Ni, Ti, Zn, Pd, and alloys thereof.
  • such contacts comprise GeAuNi alloy for n-type GaAs conducting layers.
  • Direct and selective contacts to the conducting layers should provide selective electrical access to each individual conducting layer, without disrupting its wave functions.
  • the present embodiment employ (s) a combination of lithography, ion milling/reactive ion etching (RIE) , selective wet etching, and oblique angle thin-film deposition process steps for fabricating conductive contacts in a precursor structure that contains GaAs/GaAlAs-based quantum wells or similar types of quantum well structures.
  • RIE reactive ion etching
  • Figure 2A shows an exemplary precursor structure, as supported by a substrate.
  • the precursor structure contains a top conducting layer 32 and a bottom conducting layer 34, which are sandwiched between, or flanked by, two peripheral insulating layers 30.
  • the top and bottom conducting layers 32 and 34 form two quantum wells for quantum-mechanical confinement of free electrons.
  • An intermediate insulating layer 36 forms a tunneling barrier between the top and bottom conducting layers 32 and 34.
  • the tunneling barrier 36 is sufficiently thin to allow electrons to flow therethrough via tunneling effect when the energy levels in the top and bottom conducting layers 32 and 34 are degenerate.
  • the two peripheral insulating layers 30 each contains a layer of dopant, as indicated by the dotted lines 38 and 39.
  • each of the top and bottom conducting layers 32 and 34 contains GaAs material and has a thickness of about 140 A.
  • the two peripheral insulating layers 30 each has a thickness of about 1750 A, and the intermediate insulating 36 has a thickness of about 40 A.
  • the peripheral and intermediate insulating layers 30 and 36 both contain GaxAlyAs, where 0 ⁇ x,y ⁇ 1, and more preferably x is about 0.7 and y is about 0.3.
  • the dopant layers 38 and 39 in the peripheral insulating layers 30 are respectively spaced apart from the adjacent conducting layers 34 and 32 by a distance of approximately 250 A, and more preferably, the dopant layers each has a silicon dopant concentration of about 7 ⁇ l011/cm2.
  • the substrate supporting such a GaAs/GaAlAs-based precursor structure preferably comprises semi-insulatmg GaAs.
  • the thickness of the GaAs conducting layers is about 80 A, and additional AlAs layers of about 12 A in thickness are added above and below the GaAs conducting layers, thus making the quantum confinement considerably stronger, because the level spacing from ground to first excited state is increased by more than 3 times.
  • the fabrication process starts with selective etching of the precursor structure to form a pit A in the precursor structure, by removing a portion of the upper peripheral insulating layer 30, the top conducting layer 32, and the intermediate peripheral insulating layer 36.
  • the bottom of pit A exposes an upper surface of the bottom conducting layer 34, and the sidewalls of pit A exposes the top conducting layer 32 and the intermediate peripheral insulating layer 36, as shown in Figure 2B.
  • pit A has a width in a range from about 500 A to about 1000 A.
  • the selective etching can be readily carried out by: (1) forming a patterned mask layer on a predetermined region of the precursor structure to protect this region from subsequent etching, while leaving the region where pit A is to formed unprotected, and (2) using dry etching techniques, such as ion milling or reactive ion etching (RIE) , to remove a portion of the upper peripheral insulating layer 30, the top conducting layer 32 and the intermediate peripheral insulating layer 36 in the unprotected region of the precursor structure, thereby forming pit A.
  • dry etching techniques such as ion milling or reactive ion etching (RIE)
  • the patterned mask layer can be formed by suitable lithographic techniques. Specifically, a photoresist layer is deposited on the upper surface of the precursor structure. A patterned electron beam is then impinged on the photoresist layer, in such a manner that a portion of the photoresist layer in the region where pit A is to be formed is exposed to the patterned electron beam and becomes soluble or etchable, while the remaining portion of the photoresist layer is not. By removing the soluble or etchable portion of the photoresist material with a suitable solvent or etchant, the region of the precursor structure where pit A is to be formed becomes exposed for subsequent etching. After pit A is formed, the patterned mask layer can then be removed from the precursor structure by utilizing a conventional resist stripping process.
  • the dry etching step as described heremabove is preferably coupled with a residue gas analyzer (RGA) .
  • RGA residue gas analyzer
  • the RGA analyzes the etched material during the dry etching process. Therefore, when an etching endpoint for the intermediate insulating layer 36 is reached, a sharp change in the RGA signal will be generated, which can be used in conjunction with an empirically determined etching time that is required for etching through the upper peripheral insulating layer 30, the top conducting layer 32 and the intermediate peripheral insulating layer 36, for precise control of the etching process.
  • the selective etching process can be carried out, without limitation, by any other dry etching technique, such as plasma etching or laser etching, or by a wet etching process in which a chemical etchant is employed, or by any combination thereof. Such selective etching may be performed utilizing a single etching process or multiple etching steps.
  • Ion milling or RIE may create disordered etching surfaces on the conducting layers. Therefore, a two-step selective etching process is subsequently carried out. Specifically, a first etching solution is used to first selectively remove the atomically disordered etching surfaces from the conducting layers 32 and 34, exposing the upper surface of the bottom peripheral insulating layer 30 and forming recesses in the atomically ordered conducting layers 32 and 34 (see Figure 2C) . Subsequently, a second etching solution is used to selective etch the intermediate insulating 36, thereby removing protrusions or shelves 35 as formed by the unetched edges of the intermediate insulating 36 (see Figure 2C) . Consequently, pit A is expanded and now contains a narrower, upper portion and a wider, lower portion separated by a projecting edge 33 therebetween, as shown in Figure 2D.
  • the first etching solution comprises buffered oxide etchant (BOE) , which selectively etches GaAs
  • the second etching solution comprises hydrogen fluoride, which selectively etches GaAlAs.
  • BOE buffered oxide etchant
  • Other etching solutions well known in the art can also be used for selective etching of the conducting and insulating layers, depending on the specific materials used for forming the conducting and insulating layers.
  • a thin layer of a contact material 42 is deposited over the bottom peripheral insulating layer 30 in pit A.
  • Any suitable contact material may be employed in the practice of the present invention, including, but not limited to: Cu, Al, Au, Ag, Pt, Ni, Ti, Zn, Pd, and alloys thereof.
  • GeAuNi alloy is used as the contact material for a GaAs/GaAlAs- based precursor structure.
  • the contact material layer 42 is formed by using oblique angle thin-film deposition techniques, in which an angled, collimated deposition beam or flux is used to deposit the contact material in pit A.
  • the projecting edges 33 between the narrower, upper portion and the wider, lower portion of pit A limits the reach of the angled deposition beam to levels below the upper surface of the bottom conducting layer 34, thereby providing an effective deposition stop for preventing excessive deposition of the contact material.
  • the complete contact material layer 42 can be deposited by using a top left to bottom right deposition 4OA, a top right to bottom left deposition beam 4OB, and a vertical deposition beam 4OC, as shown in Figures 2E-2G.
  • the contact material layer 42 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical contact between the contact material layer 42 and the bottom conducting layer 34 is established as long as the edges of these two layers are substantially aligned.
  • the average thickness of the contact material layer 42 ranges from about 50 A to about 150 A.
  • the contact material layer 42 has an average thickness that is substantially similar to that of the bottom conducting layer 34, so the contact material layer 42 can be substantially aligned with the bottom conducting layer 34, as shown in Figure 2G.
  • pit A is filled with a dielectric material, such as SiO2, to form a dielectric filling 44 that isolates the contact material layer 42 from the top conducting layer 32, as shown in Figure 2H.
  • the dielectric filling 44 is selectively etched, by using lithography and ion mill/RIE techniques or other selective etching techniques as described hereinabove for forming pit A, to form an isolated via opening in the dielectric filling 44 and to expose the upper surface of the contact material layer 42.
  • the isolated via opening is then filled with a contact material similar to that use for forming the contact material layer 42, thereby forming a T-shaped conductive contact 46 with an extended bottom portion 42, as shown in Figure 21.
  • Contact 46 is directly connected with the bottom conducting layer 34, but is isolated from the top conducting layer 32 by the dielectric filling 44. Therefore, contact 46 constitute a direct and selective contact to the bottom conducting layer 34.
  • a direct and selective contact to the top conducting layer 32 can be fabricated by using similar techniques as described hereinabove.
  • an extended pit B similar to the extended pit A in Figure 2D, can be formed in a precursor structure that contains a top conducting layer 52 and a bottom conducting layer 54, which are sandwiched between or flanked by two peripheral insulating layers 50.
  • the top and bottom conducting layers 52 and 54 form two quantum wells for quantum-mechanical confinement of free electrons, which are separated from each other by a thin intermediate insulating layer 56.
  • the extended pit B specifically contains a narrower, upper portion and a wider, lower portion, with projecting edges 53 therebetween, as shown in Figure 3A.
  • a dielectric material such as SiO2
  • using oblique angle thin-film deposition techniques as described hereinabove forms the dielectric material layer.
  • the projecting edges 53 between the narrower, upper portion and the wider, lower portion of pit B limits the reach of an angled, collimated deposition beam to levels below the lower surface of the top conducting layer 52, thereby providing an effective deposition stop for preventing excessive deposition of the dielectric material.
  • a complete contact material layer 62 can be deposited by using a top left to bottom right deposition 6OA, a top right to bottom left deposition beam 6OB, and a vertical deposition beam 6OC, as shown in Figures 3B-3D.
  • the dielectric material layer 62 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical insulation of the top conducting layer 52 is established as long as the edges of the dielectric material layer 52 is substantially aligned with the lower surface of the top conducting layer 52.
  • the average thickness of the dielectric material layer 62 is from about 60 A to about 300 A, more preferably from about 150 A.
  • the contact material layer 42 has an average thickness that is substantially similar to the total thickness of the bottom conducting layer 54 and and the intermediate insulating layer 56, so the dielectric material layer 62 can be substantially aligned with the the bottom conducting layer 54 and and the intermediate insulating layer 56, as shown in Figure 3D.
  • a wet etching solution is used to selectively remove a portion of the top peripheral insulating layer 50, to expand the narrower upper portion of the expanded pit B and form a further expanded pit with substantially straight sidewalls devoid of any projecting edge, as shown in Figure 3E.
  • the wet etching solution preferably comprises hydrogen fluoride, which selectively etches GaAlAs without damage the GaAs material.
  • Other etching solutions well known in the art can also be used for selective etching of the top peripheral insulating layer 50, depending on the specific materials used for forming the conducting and insulating layers.
  • the expanded pit B as shown in Figure 3E is then filled with a contact material as described hereinabove to form a conductive contact 66, as shown in Figure 3E.
  • Contact 66 is directly connected with the top conducting layer 52, but is isolated from the bottom conducting layer 54 by the dielectric material layer 62. Therefore, contact 66 constitute a direct and selective contact to the top conducting layer 52.
  • FIG. 4A shows the cross-sectional-view of a complete 2-layer device structure, which contains a top conducting layer 112 and a bottom conducting layer 114 as sandwiched between a top and bottom peripheral insulating layers 110 (with thin dopant layers 118 and 119 therein) and separated from each other by an intermediate insulating layer 116.
  • Conductive contacts 124 and 128 provide direct and selective connection to the bottom and top conducting layers 114 and 112, respectively. More importantly, contact 124 is isolated from the top conducting layer 112 by a dielectric filling 122, and contact 128 is isolated from the bottom conducting layer 114 by a dielectric material layer 126.
  • electrons can flow between the contacts 124 and 128 through the conducting layers 112 and 114 and across the thin intermediate insulating layer 116 via tunneling effect, when the energy levels of the top and bottom conducting layers 112 and 114 are degenerate.
  • isolation trench 130 can be formed around the 2-layer device structure.
  • the isolation trench 130 is formed utilizing processing steps that are well known to those skilled in the art including, for example, trench definition and etching, optionally lining the trench with a diffusion barrier, and filling the trench with a trench dielectric such as an oxide. After the trench fill, the structure may be plana ⁇ zed and an optional densification process step may be performed to densify the trench dielectric.
  • FIG 4B shows a top view of the 2-layer device structure of Figure 4A.
  • Rectangular region 140 between contacts 124 and 128 contains overlapping regions in the top conducting layer 112 and the bottom conducting layer 114, therefore defining the active region of the 2-layer device structure.
  • the active region 140 and the contacts 124 and 128 are about 500-2000 A long, more preferably about 1200-1800 A long, and most preferably about 1500 A.
  • the width of the active region 140 will depend on load matching.
  • both contacts 124 and 128 are on the upper surface of the 2-layer device structure, co-planar connectors or terminals for the nanoscopic contacts 124 and 128 can be easily fabricated by standard lithographic techniques. More importantly, device structures with co-planar connectors and terminals can be readily integrated into logic circuitry, with minimum amount of modification to the existing circuitry, and are particularly suitable for computer applications.
  • U.S. Patent No. 5,625,589 describes a static memory cell that comprises three conducting layers 2a, 2b, and 2c, which are spaced apart by insulating layers 1, as shown in Figure 5. Free electrons in these three conducting layers are quantum-mechamcally confined. Between the conducting layers 2a and 2c, a constant voltage is applied so that no tunneling effect occurs between these two layers. A variable voltage is applied to the conducting layer 2b through a transistor 8 for selection by a bit line BL 5. The transistor 8 is controlled by a word line WL 6.
  • variable voltage on the conducting layer 2b When the variable voltage on the conducting layer 2b is adjusted so that the quantum levels in the conducting layers 2a and 2b are the same, a tunneling current flows between conducting layers 2a and 2b, and the voltage differential between conducting layers 2a and 2b becomes zero, which represents a "0" in a binary state.
  • variable voltage on the conducting layer 2b is adjusted so that the quantum levels in the conducting layers 2a and 2c are the same, a tunneling current flows between conducting layers 2a and 2c, and the voltage differential between conducting layers 2a and 2c becomes zero, which represents a "1" in a binary state.
  • Figure 6 shows an exemplary three-layer device structure 150, which is preferably a static memory cell as described by U.S. Patent No. 5,625,589.
  • Device structure 150 contains three conducting layers 152, 154, and 156, as sandwiched between or flanked by a top and a bottom peripheral insulating layers 151 and separated from one another by two intermediate insulating layers 158 and 160.
  • a first conductive contact 162 is directly connected to the bottom conducting layer 156 and is isolated from the other two conducting layers 152 and 154 by a dielectric filling 172.
  • a second conductive contact 166 is directly connected to the top conducting layer 152 and is isolated from the other two conducting layers 154 and 156 by a dielectric material layer 176.
  • a third conductive contact 164 is directly connected to the intermediate conducting layer 154 and is isolated from the other two conducting layers 152 and 156 by a dielectric filling 173 and a dielectric material layer 174.
  • Contacts 162 and 166 can be fabricated using the same processing steps as illustrated by Figures 2A-2I and Figures 3A-3E.
  • the intermediate contact 164 can be fabricated using similar processing steps.
  • the dielectric material layer 174 can be formed by using the same process for forming the dielectric material layer 176, except that the upper layer of layer 174 should be substantially aligned with the lower surface of the intermediate conducting layer 154.
  • the expanded bottom portion of the T- shaped conductive contact 164 can be formed by using the same process for forming the expanded bottom portion of the T-shaped conductive contact 162, except that the expanded bottom portion of contact 164 should be substantially aligned with the intermediate conducting layer 154.
  • the dielectric filling 173 and the stem portion of the T-shaped conductive contact 164 can formed by using the same processes for forming the dielectric filling 172 and the stem portion of the T-shaped conductive contact 162. Therefore, contacts 162, 164, and 166 provide direct and selective connections to individual conducting layers 152, 154, and 156 respectively in the three-layer device structure 150.
  • FIG. 7A shows a dumbbell- shaped contact configuration, which provides increased contact area between the conducting material 182 and the contacts 184;
  • Figure 7B shows another contact configuration, in which contact 188 covers more than one surfaces of the conducting material 186. More complex contact configurations can be employed to further increase the contact area.
  • fluoride compounds such as CdF2 and CaF2 are promising materials for forming quantum well structures.
  • the higher energy barrier height of the fluo ⁇ te-based insulating layer can help achieving better on/off ratio of the device structure at higher temperatures.
  • the present invention provides a process particularly suitable for fabricating direct and selective contacts for a fluo ⁇ te-based quantum well device structure, by using lithography, selective etching, and film regrowth techniques.
  • Figure 8A shows a precursor structure formed on a substrate 200, where the precursor structure comprises two conducting layers 202 and 204 that are sandwiched between a top and a bottom peripheral insulating layers 208 and are isolated from each other by an intermediate insulating layer 206.
  • the top and bottom conducting layers 202 and 204 form two quantum wells for quantum-mechanical confinement of free electrons.
  • the intermediate insulating layer 206 form a tunneling barrier between the top and bottom conducting layers 202 and 204, while the tunneling barrier 206 is sufficiently thin to allow electrons to flow through via tunneling effect when and only when the energy levels in the top and bottom conducting layers 202 and 204 are degenerate.
  • the conducting and insulating layers 202, 204, 206, and 208 preferably comprise a material selected from the group consisting of CdF2 and CaF2. More preferably, the conducting layers 202 and 204 comprise CdF2, and the insulating layers 206 and 208 comprise CaF2.
  • a silicon substrate is particularly suitable for supporting the CdF2/CaF2-based quantum well structure .
  • a first pit, pit A is formed in the precursor structure, as shown in Figure 8B, by using processing steps similar to those described heremabove for forming pit A in Figure 2B.
  • Sequential film regrowth steps are then carried out for regrowmg, from bottom to top, a first insulating material layer 212, a conducting material layer 214, and a second insulating material layer 216 in pit A, as shown in Figures 8C-8E.
  • the regrown first and second insulating material layers 212 and 216 contain similar insulating material as that contained by the top and bottom peripheral insulating layers 208 and the intermediate insulating layer 206.
  • the regrown conducting material layer 214 contain similar conducting material as that contained by the top and bottom conducting layers 202 and 204.
  • the upper surface of the first regrown insulating material layer 212 is substantially aligned with the lower surface of the top conducting layer 202, and the upper surface of the regrown conducting material layer 214 is substantially aligned with the upper surface of the top conducting layer 202.
  • the regrown first insulating material layer 212 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical insulation of the top conducting layer 202 is established as long as the upper surface of the regrown first insulating material layer 212 is substantially aligned with the lower surface of the top conducting layer 202.
  • the regrown conducting material layer 214 does not have to have a perfectly even thickness throughout, and good electrical contact with the top conducting layer 202 is established as long as the upper surface of the regrown conducting material layer 214 is substantially aligned with the upper surface of the top conducting layer 202.
  • the average thickness of the regrown first insulating material layer 212 is from about 200 A to about 600 A.
  • the regrown first insulating material layer 212 has an average thickness that is substantially similar to the total thickness of the bottom peripheral insulating layer 208, plus the bottom conducting layer 204 plus the intermediate insulating layer 206, as shown in Figure 8C.
  • the average thickness of the regrown conducting material layer 214 is from about 10 A to about 80 A, more preferably about 40 A.
  • the regrown conducting material layer 214 has an average thickness that is substantially similar to the thickness of the top conducting layer 202, as shown in Figure 8D.
  • the regrown second insulating material layer 216 is selectively etched to form an isolation via opening 217 in layer 216, as shown in Figure 8F, by using processing steps similar to those described hereinabove for forming pit A. Subsequently, the isolated via opening 217 is filled with a contact material similar to those described hereinabove, thereby forming a conductive contact 218, as shown in Figure 8F.
  • the conductive contact 218 is directly contacted with the top conducting layer 202, which contains an original portion and a regrown portion 214, and it is isolated from the bottom conducting layer 204 by the regrown first insulating material layer 212.
  • a second pit, pit B can then be formed in the precursor structure by using processing steps similar to those described hereinabove for forming pit A.
  • the etching stops when the upper surface of the bottom conducting layer 204 is exposed, as shown in Figure 8H.
  • the etching may continue all the way down to the substrate 200, similar to pit A, and a conducting material layer substantially aligned with the bottom conducting layer 204 is regrown over the substrate 200.
  • An insulating material layer 222 is then regrown in pit B over the bottom conducting layer 204, as shown in Figure 81.
  • the regrown insulating material layer 222 contains similar insulating material as that contained by the top and bottom peripheral insulating layers 208 and the intermediate insulating layer 206.
  • the regrown insulating material layer 222 is selectively etched to form an isolation via opening 223 therein, as shown in Figure 8J, by using processing steps similar to those described hereinabove for forming isolation via opening 217.
  • the isolated via opening 223 is filled with a contact material similar to those described hereinabove, thereby forming a second conductive contact 224, as shown in Figure 8K.
  • the second conductive contact 224 is directly contacted with the bottom conducting layer 204, and it is isolated from the top conducting layer 224 by the regrown insulating material 222.
  • Figure 9 shows an exemplary three-layer device structure, which contains three conducting layers 302, 304, and 306, as sandwiched between or flanked by a top and a bottom peripheral insulating layers 312 and separated from one another by two intermediate insulating layers 308 and 310.
  • a first conductive contact 328 is directly connected to the top conducting layer 302, which contains an original portion and a regrown portion 324.
  • the first conductive contact 328 is isolated from the other two conducting layers 304 and 306 by a regrown first insulating layer 322 and a regrown second insulating layer 326.
  • a second conductive contact 338 is directly connected to the intermediate conducting layer 304, which contains an original portion and a regrown portion 334.
  • the second conductive contact 338 is isolated from the other two conducting layers 302 and 306 by a regrown first insulating layer 332 and a regrown second insulating layer 336.
  • a third conductive contact 348 is directly connected to the bottom conducting layer 306 and is isolated from the other two conducting layers 302 and 304 by a regrown insulating layer 342.
  • the first and third contacts 328 and 348 can be fabricated using the same processing steps as illustrated by Figures 8A-8K.
  • the second contact 338 can be fabricated using processing steps similar to that used for forming the first contact 328, expect that the upper surface of the regrown first insulating layer 332 is aligned with the lower surface of the intermediate conducting layer 304, and the upper surface of the regrown conducting layer 334 is aligned with the upper surface of the intermediate conducting layer 304.
  • contacts 328, 338, and 348 provide direct and selective connections to individual conducting layers 302, 304, and 306 respectively in the three-layer device structure shown in Figure 9.
  • CQWD structures are not limited to CQWD structures, but is broadly applicable to various other quantum-well based structures, such as quantum well lasers, quantum well photodetectors, quantum well solar cells, light-emitting diodes containing multiple quantum wells, quantum well micro-resonators, etc., with or without modifications and variations, as readily determmable by a person ordinarily skilled in the art according to the principles described herein.
  • the other quantum-well based structures as listed hereinabove can be readily prepared using conventional processing techniques that are well known to those skilled in the art, and therefore details concerning their fabrication are not provided herein.

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Abstract

A device structure contains two or more conducting layers (32,34), two peripheral insulating layers (30), one or more intermediate insulating layers (36), and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts . Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.

Description

MULTIPLE QUANTUM WELL DEVICES
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods of fabricating the same. More particularly, the present invention relates to multiple quantum well devices, eg coupled quantum well devices (CQWD) containing two or more direct and selective contacts, and methods of fabricating such devices.
BACKGROUND OF THE INVENTION
Coupled quantum well devices (CQWD) , such as those described, for example, in A. Palevski, et al . "Resistance Resonance in Coupled Potential Wells", Physical Review Letters, Vol. 65, No. 15, pg. 1929 (1990), Y. Katayama, et al . "Lumped Circuit Model of Two-Dimensional Tunneling Transistors," Appl . Phys. Lett. Vol. 62, No. 20, pg. 2563 (1993), J.A. Simmons, et al . "Unipolar Complementary Bistable Memories Using Gate-Controlled Negative Differential Resistance in a 2D-2D Quantum Tunneling Transistor, " International Electron Devices Meeting, 1997, Technical Digest, Dec. 7-10, 1997, pgs. 755-758, J. P. Eisenstein, et al . "Independently Contracted Two- Dimensional Electron Systems in Double Quantum Wells," Appl. Phys. Lett. Vol. 57, No. 26, p. 2324 (1990), and I. B. Spielman, et al . "Observation of a Linearly Dispersing Collective Mode in a Quantum Hall Ferromagnet, " Physical Review Letters, Vol. 87, No. 3, (2001), are tunneling devices that can operate at very low voltages (e.g., 0. IV to 0.3V), which yield ma] or advantages in terms of power consumption and are interesting to investigate in order to evaluate their potential.
In its simplest, two-layer form, a CQWD contains two quantum well layers that are separated by a thin barrier layer. Each quantum well layer includes a very thin sheet of 2-dimensional electron gas (2DEG) that lies in the xy plane. The two 2DEG sheets are superimposed at different positions along the z axis, with a narrow tunneling gap between them. When the energy levels in these two 2DEG sheets are degenerate (i.e., their quantum states share the same quantum numbers) , they are coupled strongly due to the mter-sheet tunneling effect. When the energy levels are not equal, tunneling coupling falls off, and the energy difference becomes comparable with the mter-sheet matrix element, forming a simple switching device. For more details relating to the two-layer CQWD structure, see the articles by Palevski, et al . , Katayama, et al and J.A. Simmons, et al . as mentioned heremabove.
Three-layer CQWD structures have been shown to constitute a latch, which can form the basis of logic and memory circuitry. This is described, for example, in U.S. Patent No. 5,625,589 issued to Katayama on April 29, 1997 for "Static Memory Cell with Spaced Apart Conducting Layers," and Y. Katayama "New Complementary Logic Circuits using Coupled Quantum Wells," IEEE Nano (2004) .
CQWDs, which use quantization of single particle states locally, constitute a preliminary step towards computing with quantum systems.
Further, it has been discovered that fundamental physics is involved at low temperature in CQWDs under appropriate conditions (see, the articles to I. B. Spielman, et al . and Eisenstein, et al . mentioned above), and this will be another promising field for future investigation.
However, in the prior art CQWD structure, the multiple quantum well layers are typically connected in parallel, i.e., by the same set of electrodes that simultaneously contact all the quantum well layers, due to difficulties in making selective contact to the individual quantum wells. The quantum wells are either operated in parallel, or series operation can be indirectly achieved by using additional top and bottom turn-off electrodes .
For example, Figure IA illustrates a prior art CQWD structure 10 with two quantum well layers 12 and 14, which are spaced apart by a very thin barrier layer 16. Suitable doping is provided to establish a 2DEG sheet in each well. Standard diffused-in contacts 18 and 20 are provided, each of which contacts both quantum well layers 12 and 14 simultaneously. Additional turn-off electrodes 22 and 24 are respectively fabricated on the top and bottom surfaces of the CQWD structure. Application of a negative bias potential Vt to the top turn-off electrode 22 will result in depletion of the electrons within the quantum well regions that are underneath the electrode 22. For small -Vt, the depletion only occurs within a region in the upper quantum well layer 12. Continued increase of -Vt can eventually fully deplete the upper quantum well layer 12 and begin depletion of the lower quantum well layer 14. Therefore, a range of top turn-off bias voltages exists in which the two ohmic contacts 18 and 20 are electrically connected together only via the lower quantum well layer 14. In exact analogy, the bottom turn-off electrode 24 can be negatively biased by a voltage -Vb, so that the lower quantum well layer 14 above it is fully depleted but the upper quantum well layer 12 is not. In such a manner, the top and bottom turn-off electrodes 22 and 24 can be suitably biased to provide a condition in which the contacts 18 and 20 are electrically disconnected from each other by the depleted regions in the upper and lower quantum well layers 12 and 14, as shown in Figure IB.
When the energy levels in the upper and lower quantum well layers 12 and 14 are degenerate, electrons can flow from contact 18 to contact 20, or vise versa, through un-depleted regions in the quantum well layers 12 and 14 and across the barrier layer 16 via tunneling effect, as indicated by the arrowheads in Figure IB.
In the prior art CQWD structure illustrated by Figures IA and IB, the contacts 18 and 20 are not selectively contacted with the individual quantum well layers 12 and 14. Instead, they are simultaneously contacted with both quantum wells, and the top and bottom turn-off electrodes 22 and 24 must be employed to selectively deplete regions in the quantum well layers 12 and 14, in order to indirectly establish selective electrical connection between contacts 18 and 20 and quantum well layers 14 and 12, respectively.
The top and bottom turn-off electrodes of the prior art CQWD are functionally and structurally clumsy. Further, they are limited to 2- layer structures, which is not suitable for computer applications.
SUMMARY OF THE INVENTION
The present invention provides direct and selective contacts for individual quantum wells in device structures that contain multiple quantum wells, such as CQWDs.
In one aspect, the present invention relates to a device structure that contains: (i) two or more conducting layers; (ii) two peripheral insulating layers; (in) one or more intermediate insulating layers; and (iv) two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers . The conducting layers form quantum wells for quantum-mechanical confinement of free electrons therein, and each of the two or more conductive contacts is directly and selectively connected with one of the conducting layers.
Unlike the prior art CQWD structure shown in Figures IA and IB, the device structure of the present invention does not contain any top or bottom turn-off electrode, and is therefore particularly suitable for uses in computer circuits.
Preferably, the device structure of the present invention has a first surface and a second, opposite surface, and the conductive contacts in the device structure each have a terminal that is located on the first surface, but not the second surface, of the device structure. In such an event, the quantum wells embedded in the device structure can be directly and selectively accessed from one side of the device structure, which further reduces the amount of interconnects required for integrating such a device structure into a computer circuit and simplifies the overall structure .
In its simplest form, the device structure of the present invention may be a two-layer structure that comprises two conducting layers separated by one intermediate insulating layer, with two conductive contacts that each directly and selectively connects with one of the two conducting layers. Alternatively, the device structure of the present invention may be a three-layer structure that comprises three conducting layers separated by two intermediate insulating layers, with three conductive contacts that each directly and selectively connects with one of the three conducting layers. Further, the device structure may comprise four, five, six, or even a greater number of conducting layers, which are separated by a plurality of intermediate insulating layers. The exact number of conducting layers in the device structure of the present invention is determined by its specific application.
The device structure of the present invention preferably comprises a CQWD, but alternatively, it may comprise any other quantum-well-based structure that contains multiple quantum well layers, including, but not limited to: quantum well lasers, quantum well photodetectors, quantum well solar cells, light-emitting diodes containing multiple quantum wells, quantum well micro-resonators, etc. More preferably, the device structure comprises a static memory cell, which uses alternatively coupled quantum wells for information storage, which will be described in greater details hereinafter.
In another aspect, the present invention relates to a method for forming a device structure as described hereinabove by: providing a precursor structure that contains: (i) two or more conducting layers, (ii) two peripheral insulating layers, and (in) one or more intermediate insulating layers, where the two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers, forming two or more quantum wells for quantum-mechanical confinement of free electrons; and fabricating two or more conductive contacts in the precursor structure, wherein each of the conductive contacts is directly and selectively connected with one of the two or more conducting layers, thereby forming a device structure having direct and selective contacts for quantum wells.
In a specific embodiment of the present invention, a process that includes a combination of lithography, ion millmg/reactive ion etching (RIE) , selective wet etching, and oblique angle thin-film deposition steps is employed for fabricating conductive contacts in a precursor structure that contains GaAs/GaAlAs-based quantum wells.
In another specific embodiment, a process that includes a combination of lithography, ion milling/RIE, and thin-film regrowth steps is employed for fabricating conductive contacts in a precursor structure that contains CdF2/CaF2-based quantum wells.
In a still further aspect, the present invention relates to a coupled quantum well structure that contains: (i) two or more quantum wells that are arranged and constructed for tunneling coupling at degenerate energy levels, and (ii) two or more conductive contacts, each of which is directly and selectively connected with one of the quantum wells.
In yet another aspect, the present invention relates to a memory cell that contains: a plurality of insulating layers; at least first, second and third conducting layers spaced apart by the insulating layers, wherein quantum-mechanical confinement of free electrons exists in each of the first, second and third conducting layers; at least first, second and third electrodes, which are directly and selectively contacted with the first, second and third conducting layers respectively; a first voltage applicator for applying a predetermined voltage between the first and third conducting layers through the first and third electrodes, in such a manner that no tunneling current flows directly between the first and third conducting layers; and a second voltage applicator for applying a variable voltage to the second conducting layer through the second electrode, in such a manner that a tunneling current can flow either between the first and second conducting layers, defining a first memory state, or between the second and third conducting layers, defining a second, different memory state.
Other aspects, features and advantages of the invention will be more fully apparent from the ensuing disclosure and appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will now be described by way of example only and with reference to the following drawings in which:
Figures IA and IB shows an exemplary prior art CQWD structure that contains top and bottom turn-off electrodes for selective depletion of quantum wells.
Figures 2A-2I illustrates the processing steps for fabricating a conductive contact that is directly and selectively connected with a bottom quantum well layer of a two-layer CQWD structure, according to one embodiment of the present invention.
Figures 3A-3E illustrates the processing steps for fabricating a conductive contact that is directly and selectively connected with a top quantum well layer of a two-layer CQWD structure, according to one embodiment of the present invention.
Figure 4A shows the cross-sectional view of an exemplary two-layer CQWD structure, according to one embodiment of the present invention. Figure 4B shows the top view of the two-layer CQWD structure of Figure 4A.
Figure 5 shows a prior art static memory cell that contains three quantum well layers, as described in U.S. Patent No. 5,625,589.
Figure 6 shows the cross-sectional view of an exemplary three-layer structure that contains three quantum well layers with a direct and selective contact to each quantum well layer, according to one embodiment of the present invention.
Figures 7A and 7B show schematic views of contact configurations with enlarged contact areas, according to one embodiment of the present invention.
Figures 8A-8K illustrates the processing steps for fabricating conductive contacts that are directly and selectively connected with respective top and bottom quantum well layers of a two-layer CQWD structure, according to one embodiment of the present invention.
Figure 9 shows the cross-sectional view of an exemplary three-layer structure that contains three quantum well layers with a direct and selective contact to each quantum well layer, according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
U.S. Patent No. 5,625,589 issued on April 29, 1997 to Katayama for "Static Memory Cell with Spaced Apart Conducting Layers" is incorporated herein by reference in its entirety for all purposes.
The phrase "direct and selective contact, " "direct and selective contacts," "directly and selectively contacted," or "directly and selectively contacted" as used herein refers to an electrode or an electric conductor that is in direct, physical contact with a specific conducting layer, but is completely isolated from, and does not in any manner touch, or make any physical contact with, any other conducting layer or any portion thereof. The term "substantially aligned" as used herein refers to alignment of two layers or two surfaces along a specific direction, with an offset of less than ±30 A along the specific direction.
The device structure contains two or more conducting layers sandwiched between two peripheral insulating layers and further spaced apart from one another by one or more intermediate insulating layers . Each conducting layer forms a quantum well, i.e., it is arranged and constructed in conjunction with its adjacent insulating layers for quantum-mechanically confining free electrons in one dimension, forcing them to occupy a planar region within or near the conducting layer. The width of this region is on the order of the de Broglie wavelength of the electrons, leading to quantized sub-bands. By doping an adjacent insulating layer with donor impurities, a 2DEG can be formed.
The term "conducting" and "insulating" are used herein in a relative sense, i.e., insulating layers or insulating materials are characterized by wider band gaps than those of the conducting layers or conducting materials. Therefore, in the present invention, what is normally considered a semiconductor can be referred to herein as either a conducting layer or a conducting material, if it is adjacent to a material layer of a wider band gap, or an insulating layer or an insulating material, if it is adjacent to a material layer of a narrower band gap.
The conducting layers and the insulating layers may comprise any suitable materials, such as group IV semiconductors (which include, but are not limited to: Si, Ge, C, SiGe, SiC, etc.), groups IH-V, H-VI, and IV-V compound semiconductors (which include, but are not limited to: GaAs, GaAlAs, GaAlAsSb, GaAsSb, GaAlPSb, GaAlSb, GaAlInSb, GaSb, InAs, InAlAs, InGaAs, InGaP, InP, InAsP, InAlAsSb, InAlSb, InAsSb, InSb, AlAs, AlAsSb, AlSb, TlInP, TlInGaP, TlInGaAs, AfInAs, AfInAsSb, GaN, AlGaN, and InGaN, InGaAlN, InN, AlN, CdS, CdTe, CdHgTe, ZnS, ZnSe, ZnSSe, PbSe, PbTe, PbSSe, etc.), and fluoride compounds (including, but not limited to CdF2 and CaF2) .
The conducting/insulating layers preferably comprise materials selected from the group IH-V compound semiconductor family which consists of: GaAs/AlGaAs, GaAs/GalnP, GaAs/AlAs, GaInAs/AlGaAs (AlAs, GaInP), InAsP/AHnAs, InAsP/AlGaAsSb, GaInAs/AlInAs (AlAsSb, AlInAsSb, AlGaAsSb, InP), TlInP(TlGaInP, TlGaInAs) /AlInAs (AlAsSb, AlInAsSb, AlGaAsSb, InP, AlGaPSb) , GaAsSb/InP (AlInAs, AlAsSb, AfInAsSb, AlGaAsSb, AlGaPSb), InAs/AlGaAsSb (AlSb, AlAsSb, AlGaSb), GaSb/AlGaAsSb (AlSb, AlAsSb, AlGaSb), InAsSb/AlGalnSb, InSb/AlInSb, GaN/AlGaN (AIN) , and GalnN/AlGaN (AIN) . Note that the materials for forming the conducting layers are identified herein before the forward slash, while the materials for forming the insulating layers are identified herein after the forward slash. More preferably, the device structure of the present invention comprises GaAs-based conducting layers and GaAlAs-based insulating layers.
Recent studies have shown that fluoride compounds such as CdF2 and CaF2 are promising materials for fabricating CdF2/CaF2-based quantum well and barrier structures on a Si substrate, which is described, for example, in M. Watanabe, et al . , "CaF2/CdF2 Double-Barrier Resonant Tunneling Diode with High Room-Temperature Peak-to-Valley Ratio," Japanese Journal of Appl , Phys., Vol. 39, Part 2, No. 7B, 716 (2000). Therefore, a preferred embodiment of the present invention provides a device structure that contains multiple CdF2-based conducting layers that are isolated by CaF2- based insulating layers.
The device structure is supported by a suitable substrate, which may comprise a substrate material such as Si, GaAs, InP, GaN, AIN, SiC and sapphire. In one embodiment of the present invention, the substrate contains semi-insulatmg GaAs for supporting GaAs/GaAlAs-based quantum well structures. In an alternative embodiment, the substrate contains Si for supporting CdF2/CaF2-based quantum well structures.
Typically, the conducting and the peripheral insulating layers have an average thickness of from about 5 A to about 500 A, and the intermediate insulating layers have an average thickness of from about 5 A to about 200 A. However, it is noted that thickness of the conducting and insulating layers may differ significantly for the GaAs/GaAlAs-based structures and the CdF2/CaF2-based structures.
For example, in the GAs/GaAlAs-based structures, the conducting layers are preferably characterized by an average thickness from about 30 A to about 300 A, more preferably about 140 A. The two peripheral insulating layers are preferably characterized by an average thickness from about 100 A to about 500 A, more preferably about 250 A. Moreover, each of the peripheral insulating layers preferably contains a thin layer of dopant for forming the 2DEG sheets. The intermediate insulating layers are preferably characterized by an average thickness from about 20 A to about 100 A, more preferably about 40 A.
In the CdF2/CaF2-based structures, the conducting layers are preferably characterized by an average thickness from about 10 A to about 80 A, more preferably about 40 A. The two peripheral insulating layers are preferably characterized by an average thickness from about 100 A to about 500 A, more preferably about 250 A. The intermediate insulating layers are preferably characterized by an average thickness from about 5 A to about 20 A, more preferably about 9 A.
The device structure contains direct and selective contacts to the individual conducting layers. Such contacts may comprise any suitable conductive material, including, but not limited to: Cu, Al, Au, Ag, Pt, Ni, Ti, Zn, Pd, and alloys thereof. In a preferred embodiment of the present invention, such contacts comprise GeAuNi alloy for n-type GaAs conducting layers.
Direct and selective contacts to the conducting layers (i.e., the quantum wells) should provide selective electrical access to each individual conducting layer, without disrupting its wave functions.
The present embodiment (s) employ (s) a combination of lithography, ion milling/reactive ion etching (RIE) , selective wet etching, and oblique angle thin-film deposition process steps for fabricating conductive contacts in a precursor structure that contains GaAs/GaAlAs-based quantum wells or similar types of quantum well structures.
Figure 2A shows an exemplary precursor structure, as supported by a substrate. The precursor structure contains a top conducting layer 32 and a bottom conducting layer 34, which are sandwiched between, or flanked by, two peripheral insulating layers 30. The top and bottom conducting layers 32 and 34 form two quantum wells for quantum-mechanical confinement of free electrons. An intermediate insulating layer 36 forms a tunneling barrier between the top and bottom conducting layers 32 and 34. The tunneling barrier 36 is sufficiently thin to allow electrons to flow therethrough via tunneling effect when the energy levels in the top and bottom conducting layers 32 and 34 are degenerate. Further, the two peripheral insulating layers 30 each contains a layer of dopant, as indicated by the dotted lines 38 and 39.
In a preferred embodiment, each of the top and bottom conducting layers 32 and 34 contains GaAs material and has a thickness of about 140 A. The two peripheral insulating layers 30 each has a thickness of about 1750 A, and the intermediate insulating 36 has a thickness of about 40 A. The peripheral and intermediate insulating layers 30 and 36 both contain GaxAlyAs, where 0 < x,y <1, and more preferably x is about 0.7 and y is about 0.3. The dopant layers 38 and 39 in the peripheral insulating layers 30 are respectively spaced apart from the adjacent conducting layers 34 and 32 by a distance of approximately 250 A, and more preferably, the dopant layers each has a silicon dopant concentration of about 7χl011/cm2. The substrate supporting such a GaAs/GaAlAs-based precursor structure preferably comprises semi-insulatmg GaAs.
In an alternative embodiment, the thickness of the GaAs conducting layers is about 80 A, and additional AlAs layers of about 12 A in thickness are added above and below the GaAs conducting layers, thus making the quantum confinement considerably stronger, because the level spacing from ground to first excited state is increased by more than 3 times.
The fabrication process starts with selective etching of the precursor structure to form a pit A in the precursor structure, by removing a portion of the upper peripheral insulating layer 30, the top conducting layer 32, and the intermediate peripheral insulating layer 36. The bottom of pit A exposes an upper surface of the bottom conducting layer 34, and the sidewalls of pit A exposes the top conducting layer 32 and the intermediate peripheral insulating layer 36, as shown in Figure 2B.
Preferably but not necessarily, pit A has a width in a range from about 500 A to about 1000 A.
The selective etching can be readily carried out by: (1) forming a patterned mask layer on a predetermined region of the precursor structure to protect this region from subsequent etching, while leaving the region where pit A is to formed unprotected, and (2) using dry etching techniques, such as ion milling or reactive ion etching (RIE) , to remove a portion of the upper peripheral insulating layer 30, the top conducting layer 32 and the intermediate peripheral insulating layer 36 in the unprotected region of the precursor structure, thereby forming pit A.
The patterned mask layer can be formed by suitable lithographic techniques. Specifically, a photoresist layer is deposited on the upper surface of the precursor structure. A patterned electron beam is then impinged on the photoresist layer, in such a manner that a portion of the photoresist layer in the region where pit A is to be formed is exposed to the patterned electron beam and becomes soluble or etchable, while the remaining portion of the photoresist layer is not. By removing the soluble or etchable portion of the photoresist material with a suitable solvent or etchant, the region of the precursor structure where pit A is to be formed becomes exposed for subsequent etching. After pit A is formed, the patterned mask layer can then be removed from the precursor structure by utilizing a conventional resist stripping process.
The dry etching step as described heremabove is preferably coupled with a residue gas analyzer (RGA) . The RGA analyzes the etched material during the dry etching process. Therefore, when an etching endpoint for the intermediate insulating layer 36 is reached, a sharp change in the RGA signal will be generated, which can be used in conjunction with an empirically determined etching time that is required for etching through the upper peripheral insulating layer 30, the top conducting layer 32 and the intermediate peripheral insulating layer 36, for precise control of the etching process.
Although ion milling and RIE are identified as the preferred techniques heremabove, the selective etching process can be carried out, without limitation, by any other dry etching technique, such as plasma etching or laser etching, or by a wet etching process in which a chemical etchant is employed, or by any combination thereof. Such selective etching may be performed utilizing a single etching process or multiple etching steps.
Ion milling or RIE may create disordered etching surfaces on the conducting layers. Therefore, a two-step selective etching process is subsequently carried out. Specifically, a first etching solution is used to first selectively remove the atomically disordered etching surfaces from the conducting layers 32 and 34, exposing the upper surface of the bottom peripheral insulating layer 30 and forming recesses in the atomically ordered conducting layers 32 and 34 (see Figure 2C) . Subsequently, a second etching solution is used to selective etch the intermediate insulating 36, thereby removing protrusions or shelves 35 as formed by the unetched edges of the intermediate insulating 36 (see Figure 2C) . Consequently, pit A is expanded and now contains a narrower, upper portion and a wider, lower portion separated by a projecting edge 33 therebetween, as shown in Figure 2D.
Preferably, when the conducting layers comprise GaAs, and the intermediate insulating layer comprises GaAlAs, the first etching solution comprises buffered oxide etchant (BOE) , which selectively etches GaAs, and the second etching solution comprises hydrogen fluoride, which selectively etches GaAlAs. Other etching solutions well known in the art can also be used for selective etching of the conducting and insulating layers, depending on the specific materials used for forming the conducting and insulating layers.
After formation of the expanded pit A, a thin layer of a contact material 42 is deposited over the bottom peripheral insulating layer 30 in pit A. Any suitable contact material may be employed in the practice of the present invention, including, but not limited to: Cu, Al, Au, Ag, Pt, Ni, Ti, Zn, Pd, and alloys thereof. In a preferred embodiment of the present invention, GeAuNi alloy is used as the contact material for a GaAs/GaAlAs- based precursor structure.
In a preferred embodiment, the contact material layer 42 is formed by using oblique angle thin-film deposition techniques, in which an angled, collimated deposition beam or flux is used to deposit the contact material in pit A. The projecting edges 33 between the narrower, upper portion and the wider, lower portion of pit A limits the reach of the angled deposition beam to levels below the upper surface of the bottom conducting layer 34, thereby providing an effective deposition stop for preventing excessive deposition of the contact material. The complete contact material layer 42 can be deposited by using a top left to bottom right deposition 4OA, a top right to bottom left deposition beam 4OB, and a vertical deposition beam 4OC, as shown in Figures 2E-2G.
Note that the contact material layer 42 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical contact between the contact material layer 42 and the bottom conducting layer 34 is established as long as the edges of these two layers are substantially aligned.
In the GaAs/GaAlAs embodiment, the average thickness of the contact material layer 42 ranges from about 50 A to about 150 A. Preferably, but not necessarily, the contact material layer 42 has an average thickness that is substantially similar to that of the bottom conducting layer 34, so the contact material layer 42 can be substantially aligned with the bottom conducting layer 34, as shown in Figure 2G.
After the contact material layer 42 is deposited, pit A is filled with a dielectric material, such as SiO2, to form a dielectric filling 44 that isolates the contact material layer 42 from the top conducting layer 32, as shown in Figure 2H. Subsequently, the dielectric filling 44 is selectively etched, by using lithography and ion mill/RIE techniques or other selective etching techniques as described hereinabove for forming pit A, to form an isolated via opening in the dielectric filling 44 and to expose the upper surface of the contact material layer 42. The isolated via opening is then filled with a contact material similar to that use for forming the contact material layer 42, thereby forming a T-shaped conductive contact 46 with an extended bottom portion 42, as shown in Figure 21.
Contact 46 is directly connected with the bottom conducting layer 34, but is isolated from the top conducting layer 32 by the dielectric filling 44. Therefore, contact 46 constitute a direct and selective contact to the bottom conducting layer 34.
A direct and selective contact to the top conducting layer 32 can be fabricated by using similar techniques as described hereinabove.
Specifically, an extended pit B, similar to the extended pit A in Figure 2D, can be formed in a precursor structure that contains a top conducting layer 52 and a bottom conducting layer 54, which are sandwiched between or flanked by two peripheral insulating layers 50. The top and bottom conducting layers 52 and 54 form two quantum wells for quantum-mechanical confinement of free electrons, which are separated from each other by a thin intermediate insulating layer 56. The extended pit B specifically contains a narrower, upper portion and a wider, lower portion, with projecting edges 53 therebetween, as shown in Figure 3A.
A thick layer of a dielectric material, such as SiO2, is deposited over the bottom peripheral insulating layer 50 in pit B. In a preferred embodiment of the present invention, using oblique angle thin-film deposition techniques as described hereinabove forms the dielectric material layer. Specifically, the projecting edges 53 between the narrower, upper portion and the wider, lower portion of pit B limits the reach of an angled, collimated deposition beam to levels below the lower surface of the top conducting layer 52, thereby providing an effective deposition stop for preventing excessive deposition of the dielectric material. A complete contact material layer 62 can be deposited by using a top left to bottom right deposition 6OA, a top right to bottom left deposition beam 6OB, and a vertical deposition beam 6OC, as shown in Figures 3B-3D.
Note that the dielectric material layer 62 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical insulation of the top conducting layer 52 is established as long as the edges of the dielectric material layer 52 is substantially aligned with the lower surface of the top conducting layer 52.
In the GaAs/GaAlAs embodiment the average thickness of the dielectric material layer 62 is from about 60 A to about 300 A, more preferably from about 150 A. Preferably, but not necessarily, the contact material layer 42 has an average thickness that is substantially similar to the total thickness of the bottom conducting layer 54 and and the intermediate insulating layer 56, so the dielectric material layer 62 can be substantially aligned with the the bottom conducting layer 54 and and the intermediate insulating layer 56, as shown in Figure 3D.
Subsequently, a wet etching solution is used to selectively remove a portion of the top peripheral insulating layer 50, to expand the narrower upper portion of the expanded pit B and form a further expanded pit with substantially straight sidewalls devoid of any projecting edge, as shown in Figure 3E. In a GaAs/GaAlAs-based system, the wet etching solution preferably comprises hydrogen fluoride, which selectively etches GaAlAs without damage the GaAs material. Other etching solutions well known in the art can also be used for selective etching of the top peripheral insulating layer 50, depending on the specific materials used for forming the conducting and insulating layers.
The expanded pit B as shown in Figure 3E is then filled with a contact material as described hereinabove to form a conductive contact 66, as shown in Figure 3E.
Contact 66 is directly connected with the top conducting layer 52, but is isolated from the bottom conducting layer 54 by the dielectric material layer 62. Therefore, contact 66 constitute a direct and selective contact to the top conducting layer 52.
The upper portion of Figure 4A shows the cross-sectional-view of a complete 2-layer device structure, which contains a top conducting layer 112 and a bottom conducting layer 114 as sandwiched between a top and bottom peripheral insulating layers 110 (with thin dopant layers 118 and 119 therein) and separated from each other by an intermediate insulating layer 116. Conductive contacts 124 and 128 provide direct and selective connection to the bottom and top conducting layers 114 and 112, respectively. More importantly, contact 124 is isolated from the top conducting layer 112 by a dielectric filling 122, and contact 128 is isolated from the bottom conducting layer 114 by a dielectric material layer 126.
As shown in the expanded view in the lower portion of Figure 4A, electrons can flow between the contacts 124 and 128 through the conducting layers 112 and 114 and across the thin intermediate insulating layer 116 via tunneling effect, when the energy levels of the top and bottom conducting layers 112 and 114 are degenerate.
Further, as shown in Figure 4A, isolation trench 130 can be formed around the 2-layer device structure. The isolation trench 130 is formed utilizing processing steps that are well known to those skilled in the art including, for example, trench definition and etching, optionally lining the trench with a diffusion barrier, and filling the trench with a trench dielectric such as an oxide. After the trench fill, the structure may be planaπzed and an optional densification process step may be performed to densify the trench dielectric.
Figure 4B shows a top view of the 2-layer device structure of Figure 4A. Rectangular region 140 between contacts 124 and 128 contains overlapping regions in the top conducting layer 112 and the bottom conducting layer 114, therefore defining the active region of the 2-layer device structure. Preferably, the active region 140 and the contacts 124 and 128 are about 500-2000 A long, more preferably about 1200-1800 A long, and most preferably about 1500 A. The width of the active region 140 will depend on load matching.
Because both contacts 124 and 128 are on the upper surface of the 2-layer device structure, co-planar connectors or terminals for the nanoscopic contacts 124 and 128 can be easily fabricated by standard lithographic techniques. More importantly, device structures with co-planar connectors and terminals can be readily integrated into logic circuitry, with minimum amount of modification to the existing circuitry, and are particularly suitable for computer applications.
The techniques as described hereinabove can be readily applied for fabricating three-, four-, five-, or six-layer device structures.
For example, U.S. Patent No. 5,625,589 describes a static memory cell that comprises three conducting layers 2a, 2b, and 2c, which are spaced apart by insulating layers 1, as shown in Figure 5. Free electrons in these three conducting layers are quantum-mechamcally confined. Between the conducting layers 2a and 2c, a constant voltage is applied so that no tunneling effect occurs between these two layers. A variable voltage is applied to the conducting layer 2b through a transistor 8 for selection by a bit line BL 5. The transistor 8 is controlled by a word line WL 6.
When the variable voltage on the conducting layer 2b is adjusted so that the quantum levels in the conducting layers 2a and 2b are the same, a tunneling current flows between conducting layers 2a and 2b, and the voltage differential between conducting layers 2a and 2b becomes zero, which represents a "0" in a binary state. On the other hand, when the variable voltage on the conducting layer 2b is adjusted so that the quantum levels in the conducting layers 2a and 2c are the same, a tunneling current flows between conducting layers 2a and 2c, and the voltage differential between conducting layers 2a and 2c becomes zero, which represents a "1" in a binary state.
The principles and techniques as described hereinabove can be readily applied to provide direct and selective contacts to the individual conducting layers in the three-layer static memory cell described by U.S. Patent No. 5, 625,589.
Figure 6 shows an exemplary three-layer device structure 150, which is preferably a static memory cell as described by U.S. Patent No. 5,625,589. Device structure 150 contains three conducting layers 152, 154, and 156, as sandwiched between or flanked by a top and a bottom peripheral insulating layers 151 and separated from one another by two intermediate insulating layers 158 and 160. A first conductive contact 162 is directly connected to the bottom conducting layer 156 and is isolated from the other two conducting layers 152 and 154 by a dielectric filling 172. A second conductive contact 166 is directly connected to the top conducting layer 152 and is isolated from the other two conducting layers 154 and 156 by a dielectric material layer 176. A third conductive contact 164 is directly connected to the intermediate conducting layer 154 and is isolated from the other two conducting layers 152 and 156 by a dielectric filling 173 and a dielectric material layer 174.
Contacts 162 and 166 can be fabricated using the same processing steps as illustrated by Figures 2A-2I and Figures 3A-3E. The intermediate contact 164 can be fabricated using similar processing steps. For example, the dielectric material layer 174 can be formed by using the same process for forming the dielectric material layer 176, except that the upper layer of layer 174 should be substantially aligned with the lower surface of the intermediate conducting layer 154. The expanded bottom portion of the T- shaped conductive contact 164 can be formed by using the same process for forming the expanded bottom portion of the T-shaped conductive contact 162, except that the expanded bottom portion of contact 164 should be substantially aligned with the intermediate conducting layer 154. Finally, the dielectric filling 173 and the stem portion of the T-shaped conductive contact 164 can formed by using the same processes for forming the dielectric filling 172 and the stem portion of the T-shaped conductive contact 162. Therefore, contacts 162, 164, and 166 provide direct and selective connections to individual conducting layers 152, 154, and 156 respectively in the three-layer device structure 150.
The contact resistance between the conductive contacts and the respective conducting layers may have impact on the tunneling current. In order to minimize the contact resistance to allow maximum tunneling effect, various contact configurations can be used to increase the contact area and to reduce the contact resistance. For example, Figure 7A shows a dumbbell- shaped contact configuration, which provides increased contact area between the conducting material 182 and the contacts 184; Figure 7B shows another contact configuration, in which contact 188 covers more than one surfaces of the conducting material 186. More complex contact configurations can be employed to further increase the contact area.
As mentioned heremabove, fluoride compounds, such as CdF2 and CaF2, are promising materials for forming quantum well structures. The higher energy barrier height of the fluoπte-based insulating layer can help achieving better on/off ratio of the device structure at higher temperatures.
The present invention provides a process particularly suitable for fabricating direct and selective contacts for a fluoπte-based quantum well device structure, by using lithography, selective etching, and film regrowth techniques.
Specifically, Figure 8A shows a precursor structure formed on a substrate 200, where the precursor structure comprises two conducting layers 202 and 204 that are sandwiched between a top and a bottom peripheral insulating layers 208 and are isolated from each other by an intermediate insulating layer 206. The top and bottom conducting layers 202 and 204 form two quantum wells for quantum-mechanical confinement of free electrons. The intermediate insulating layer 206 form a tunneling barrier between the top and bottom conducting layers 202 and 204, while the tunneling barrier 206 is sufficiently thin to allow electrons to flow through via tunneling effect when and only when the energy levels in the top and bottom conducting layers 202 and 204 are degenerate. The conducting and insulating layers 202, 204, 206, and 208 preferably comprise a material selected from the group consisting of CdF2 and CaF2. More preferably, the conducting layers 202 and 204 comprise CdF2, and the insulating layers 206 and 208 comprise CaF2. A silicon substrate is particularly suitable for supporting the CdF2/CaF2-based quantum well structure .
A first pit, pit A, is formed in the precursor structure, as shown in Figure 8B, by using processing steps similar to those described heremabove for forming pit A in Figure 2B.
Sequential film regrowth steps are then carried out for regrowmg, from bottom to top, a first insulating material layer 212, a conducting material layer 214, and a second insulating material layer 216 in pit A, as shown in Figures 8C-8E.
The regrown first and second insulating material layers 212 and 216 contain similar insulating material as that contained by the top and bottom peripheral insulating layers 208 and the intermediate insulating layer 206. The regrown conducting material layer 214 contain similar conducting material as that contained by the top and bottom conducting layers 202 and 204. The upper surface of the first regrown insulating material layer 212 is substantially aligned with the lower surface of the top conducting layer 202, and the upper surface of the regrown conducting material layer 214 is substantially aligned with the upper surface of the top conducting layer 202.
Note that the regrown first insulating material layer 212 does not have to have a perfectly even thickness throughout, and some areas of this layer can be significantly thicker than others. Good electrical insulation of the top conducting layer 202 is established as long as the upper surface of the regrown first insulating material layer 212 is substantially aligned with the lower surface of the top conducting layer 202.
Similarly, the regrown conducting material layer 214 does not have to have a perfectly even thickness throughout, and good electrical contact with the top conducting layer 202 is established as long as the upper surface of the regrown conducting material layer 214 is substantially aligned with the upper surface of the top conducting layer 202. In the CdF2/CaF2 embodiment, the average thickness of the regrown first insulating material layer 212 is from about 200 A to about 600 A. Preferably, but not necessarily, the regrown first insulating material layer 212 has an average thickness that is substantially similar to the total thickness of the bottom peripheral insulating layer 208, plus the bottom conducting layer 204 plus the intermediate insulating layer 206, as shown in Figure 8C.
In the CdF2/CaF2 embodiment, the average thickness of the regrown conducting material layer 214 is from about 10 A to about 80 A, more preferably about 40 A. Preferably, but not necessarily, the regrown conducting material layer 214 has an average thickness that is substantially similar to the thickness of the top conducting layer 202, as shown in Figure 8D.
After complete regrowth in pit A, the regrown second insulating material layer 216 is selectively etched to form an isolation via opening 217 in layer 216, as shown in Figure 8F, by using processing steps similar to those described hereinabove for forming pit A. Subsequently, the isolated via opening 217 is filled with a contact material similar to those described hereinabove, thereby forming a conductive contact 218, as shown in Figure 8F.
The conductive contact 218 is directly contacted with the top conducting layer 202, which contains an original portion and a regrown portion 214, and it is isolated from the bottom conducting layer 204 by the regrown first insulating material layer 212.
A second pit, pit B, can then be formed in the precursor structure by using processing steps similar to those described hereinabove for forming pit A. Preferably, the etching stops when the upper surface of the bottom conducting layer 204 is exposed, as shown in Figure 8H. Alternatively, the etching may continue all the way down to the substrate 200, similar to pit A, and a conducting material layer substantially aligned with the bottom conducting layer 204 is regrown over the substrate 200.
An insulating material layer 222 is then regrown in pit B over the bottom conducting layer 204, as shown in Figure 81. The regrown insulating material layer 222 contains similar insulating material as that contained by the top and bottom peripheral insulating layers 208 and the intermediate insulating layer 206.
Subsequently, the regrown insulating material layer 222 is selectively etched to form an isolation via opening 223 therein, as shown in Figure 8J, by using processing steps similar to those described hereinabove for forming isolation via opening 217. Subsequently, the isolated via opening 223 is filled with a contact material similar to those described hereinabove, thereby forming a second conductive contact 224, as shown in Figure 8K.
The second conductive contact 224 is directly contacted with the bottom conducting layer 204, and it is isolated from the top conducting layer 224 by the regrown insulating material 222.
The principles and techniques as described hereinabove can be readily applied to provide direct and selective contacts to the individual conducting layers in a fluoπte-based three-layer quantum well device structure .
Figure 9 shows an exemplary three-layer device structure, which contains three conducting layers 302, 304, and 306, as sandwiched between or flanked by a top and a bottom peripheral insulating layers 312 and separated from one another by two intermediate insulating layers 308 and 310. A first conductive contact 328 is directly connected to the top conducting layer 302, which contains an original portion and a regrown portion 324. The first conductive contact 328 is isolated from the other two conducting layers 304 and 306 by a regrown first insulating layer 322 and a regrown second insulating layer 326. A second conductive contact 338 is directly connected to the intermediate conducting layer 304, which contains an original portion and a regrown portion 334. The second conductive contact 338 is isolated from the other two conducting layers 302 and 306 by a regrown first insulating layer 332 and a regrown second insulating layer 336. A third conductive contact 348 is directly connected to the bottom conducting layer 306 and is isolated from the other two conducting layers 302 and 304 by a regrown insulating layer 342. The first and third contacts 328 and 348 can be fabricated using the same processing steps as illustrated by Figures 8A-8K. The second contact 338 can be fabricated using processing steps similar to that used for forming the first contact 328, expect that the upper surface of the regrown first insulating layer 332 is aligned with the lower surface of the intermediate conducting layer 304, and the upper surface of the regrown conducting layer 334 is aligned with the upper surface of the intermediate conducting layer 304.
Therefore, contacts 328, 338, and 348 provide direct and selective connections to individual conducting layers 302, 304, and 306 respectively in the three-layer device structure shown in Figure 9.
Although the above description is provided primarily in terms of CQWD structures, for simplicity and illustration purposes only, the present invention is not limited to CQWD structures, but is broadly applicable to various other quantum-well based structures, such as quantum well lasers, quantum well photodetectors, quantum well solar cells, light-emitting diodes containing multiple quantum wells, quantum well micro-resonators, etc., with or without modifications and variations, as readily determmable by a person ordinarily skilled in the art according to the principles described herein. The other quantum-well based structures as listed hereinabove can be readily prepared using conventional processing techniques that are well known to those skilled in the art, and therefore details concerning their fabrication are not provided herein.
It is noted that the drawings of the present invention are provided for illustrative purposes and are not drawn to scale.
While the invention has been described herein with reference to specific embodiments, features and aspects, it will be recognized that the invention is not thus limited, but rather extends in utility to other modifications, variations, applications, and embodiments, and accordingly all such other modifications, variations, applications, and embodiments are to be regarded as being within the invention, as defined by the appended claims.

Claims

1. A device structure comprising: two or more conducting layers; two peripheral insulating layers; one or more intermediate insulating layers; and two or more conductive contacts, wherein said two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers, forming two or more quantum wells for quantum-mechanical confinement of free electrons, and wherein each of the two or more conductive contacts is directly and selectively connected with one of the conducting layers .
2. The device structure of claim 1, comprising a first surface and a second surface opposite to the first surface, wherein the two or more conductive contacts each have a terminal on the first surface, but not the second surface, of said device structure.
3. The device structure of claim 1, wherein the two or more conducting layers each are characterized by a thickness in a range from about 5 A to about 500 A.
4. The device structure of claim 1, wherein the one or more intermediate insulating layers each are characterized by a thickness in a range from about 5 A to about 200 A.
5. The device structure of claim 1, comprising a coupled quantum well device .
6. A method for forming a device structure, comprising: providing a precursor structure that comprises: (i) two or more conducting layers, (ii) two peripheral insulating layers, and (in) one or more intermediate insulating layers, wherein said two or more conducting layers are sandwiched between the two peripheral insulating layers and spaced apart from one another by the one or more intermediate insulating layers, forming two or more quantum wells for quantum-mechanical confinement of free electrons; and fabricating two or more conductive contacts in said precursor structure, wherein each of said conductive contacts is directly and selectively connected with one of the two or more conducting layers, thereby forming a device structure having direct and selective contacts for quantum wells.
7. The method of claim 6, wherein the device structure comprises a first surface and a second surface opposite to the first surface, wherein the two or more conductive contacts each have a terminal on the first surface, but not the second surface, of said device structure.
8. The method of claim 6, wherein the two or more conducting layers of the precursor structure each are characterized by a thickness in a range from about 5 A to about 500 A.
9. The method of claim 6, wherein the one or more intermediate insulating layers of the precursor structure each are characterized by a thickness in a range from about 5 A to about 200 A.
10. The method of claim 6, wherein the two or more conducting layers of the precursor structure each comprise GaAs, wherein the peripheral and intermediate insulating layers of the precursor structure each comprise GaAlAs, and wherein a first conductive contact directly and selectively contacting a lowermost conducting layer of said precursor structure is fabricated by a process comprising:
(a) selectively etching the precursor structure to form a first pit defined by a bottom and multiple sidewalls, wherein the bottom of said first pit exposes an upper surface of the lowermost conducting layer, and wherein the sidewalls of said first pit expose the other conducting layer (s) and the one or more intermediate insulating layers of the precursor structure; (b) selectively etching the conducting layers in said first pit to expose an upper surface of the peripheral insulating layer that underlies said lowermost conducting layer and to form recesses in the conducting layers, wherein unetched edges of the one or more intermediate insulating layers form one or more protrusions on the sidewalls of the first pit; (c) selectively etching the one or more intermediate insulating layers in said first pit, so as to eliminate the protrusions on the sidewalls of the first pit and to form an expanded first pit having a narrower, upper portion and a wider, lower portion separated by a projecting edge therebetween; (d) depositing a layer of a contact material in said expanded first pit by using an angled, collimated beam, wherein the projecting edge between the narrower, upper portion and the wider, lower portion of the expanded first pit provides a deposition stop, so that edges of the deposited layer of contact material are substantially aligned with the lowermost conducting layer;
(e) forming a dielectric filling in the extended first pit over the layer of contact material formed in step (d) ;
(f) selectively etching the dielectric filling to form an isolated via opening that exposes an upper surface of said layer of the contact material; and
(g) filling the isolated via opening with a contact material, thereby forming the first conductive contact, which is directly connected with the lowermost conducting layer and is isolated from the other conducting layer (s) by the dielectric filling formed in step (e) .
11. The method of claim 10, wherein steps (a) and (f) are carried out by using ion milling, reactive ion etching, plasma etching, laser etching, or wet etching, and a residue gas analyzer (RGA) is employed for etching control.
12. The method of claim 10, wherein step (b) is carried out by using buffered oxide etch.
13. The method of claim 10, wherein step (c) is carried out by using an etching solution containing one or more etchants selected from the group consisting of hydrogen fluoride.
14. The method of claim 10, wherein a second conductive directly and selectively contacting an uppermost conducting layer of the precursor structure is fabricated by a process comprising:
(a) selectively etching the precursor structure to form a second pit defined by a bottom and multiple sidewalls, wherein the bottom of said second pit exposes the upper surface of the lowermost conducting layer, and wherein the sidewalls of said second pit expose the other conducting layer (s) and the one or more intermediate insulating layers of the precursor structure;
(b) selectively etching the conducting layers at the bottom and sidewalls of said second pit to expose an upper surface of the peripheral insulating layer that underlies said lowermost conducting layer and to form recesses in the conducting layers, wherein unetched edges of the one or more intermediate insulating layers form one or more protrusions on the sidewalls of the second pit; (c) selectively etching the one or more intermediate insulating layers at the sidewalls of said second pit, so as to eliminate the protrusions on the sidewalls of the second pit and form an expanded second pit having a narrower, upper portion and a wider, lower portion separated by a projecting edge therebetween; (d) depositing a layer of a dielectric material in said expanded second pit by using an angled, collimated beam, wherein the projecting edge between the narrower, upper portion and the wider, lower portion of the expanded second pit provides a deposition stop, so that edges of the deposited layer of dielectric material are substantially aligned with a lower surface of the uppermost conducting layer;
(e) expanding the narrower, upper portion of the expanded second pit to form a further expanded second pit that has substantially straight sidewalls and is devoid of any projecting edge; and
(f) filling the further expanded second pit with a contact material, thereby forming the second conductive contact, which is directly connected with the uppermost conducting layer and is isolated from the other conducting layer (s) by the layer of dielectric material formed in step (d) .
15. The method of claim 14, wherein at least one intermediate conductive contact directly and selectively contacting at least one intermediate conducting layer of the precursor structure is fabricated by a process comprising:
(a) selectively etching the precursor structure to form an intermediate pit defined by a bottom and multiple sidewalls, wherein the bottom of said second pit exposes the upper surface of the lowermost conducting layer, and wherein the sidewalls of said intermediate pit expose the other conducting layer (s) and the one or more intermediate insulating layers; (b) selectively etching the two or more conducting layers at the bottom and sidewalls of said intermediate pit to expose an upper surface of the peripheral insulating layer that underlies said lowermost conducting layer and to form recesses in the conducting layers, wherein unetched edges of the one or more intermediate insulating layers form one or more protrusions on the sidewalls of the intermediate pit;
(c) selectively etching the one or more intermediate insulating layers at the sidewalls of said intermediate pit, so as to eliminate the protrusions on the sidewalls of the intermediate pit and form an expanded intermediate pit having a narrower, upper portion and a wider, lower portion separated by a projecting edge therebetween;
(d) depositing a layer of a dielectric material in said expanded intermediate pit by using an angled, collimated beam, wherein the projecting edge between the narrower, upper portion and the wider, lower portion of the expanded intermediate pit provides a deposition stop, so that edges of the deposited layer of dielectric material are substantially aligned with a lower surface of the intermediate conducting layer;
(e) depositing a layer of a contact material in said expanded intermediate pit over the layer of insulating material deposited in step (d) , by using an angled, collimated beam, wherein the projecting edge between the narrower, upper portion and the wider, lower portion of the expanded intermediate pit provides a deposition stop, so that edges of the deposited layer of contact material are substantially aligned with the intermediate conducting layer;
(f) forming a dielectric filling in the extended intermediate pit over the layer of contact material formed in step (e) ;
(g) selectively etching the dielectric filling to form an isolated via opening that exposes an upper surface of said layer of the contact material; and
(h) filling the isolated via opening with a contact material, thereby forming the intermediate conductive contact, which is directly connected with the intermediate conducting layer and is isolated from the other conducting layer (s) by the layer of dielectric material formed in step (d) and the dielectric filling formed in step (f) .
16. The method of claim 6, wherein the conducting layers of the precursor structure each comprise CdF2, wherein the peripheral and intermediate insulating layers of the precursor structure each comprise CaF2, and wherein a first conductive directly and selectively contacting a lowermost conducting layer of said precursor structure is fabricated by a process comprising:
(a) selectively etching the precursor structure to form a first pit defined by a bottom and multiple sidewalls, wherein the bottom of said first pit exposes an upper surface of the lowermost conducting layer, and wherein the sidewalls of said first pit expose the other conducting layer (s) and the one or more intermediate insulating layers;
(b) regrowing an insulating material over the lowermost conducting layer in said first pit;
(c) selectively etching the regrown insulating material to form an isolated via opening that exposes the upper surface of said lowermost conducting layer; and
(d) filling the isolated via opening with a contact material, thereby forming the first conductive contact, which is directly connected with the lowermost conducting layer and is isolated from the other conducting layer (s) by the insulating material regrown in step (b) .
17. The method of claim 16, wherein a second conductive directly and selectively contacting an uppermost conducting layer of the precursor structure is fabricated by a process comprising:
(a) selectively etching the precursor structure to form a second pit defined by a bottom and multiple sidewalls, wherein the bottom of said second pit exposes the upper surface of the lowermost conducting layer, and wherein the sidewalls of said second pit expose the other conducting layer (s) and the one or more intermediate insulating layers;
(b) regrowing a first layer of insulating material over the lowermost conducting layer in said second pit, wherein an upper surface of said first layer of insulating material is substantially aligned with a lower surface of the uppermost conducting layer;
(c) regrowing a layer of conducting material over the first layer of insulating material in said second pit, wherein an upper surface of said layer of conducting material is substantially aligned with an upper surface of the uppermost conducting layer; (d) regrowing a second layer of insulating material over the layer of conducting material to fill said second pit;
(e) selectively etching the regrown second layer of insulating material to form an isolated via opening that exposes the upper surface of said layer of conducting material as regrown in step (c) ; and (f) filling the isolated via opening with a contact material, thereby forming the second conductive contact, which is directly connected with the uppermost conducting layer and is isolated from the other conducting layer (s) by the first layer of insulating material regrown in step (b) and the second layer of insulating material regrown in step (d) .
18. The method of claim 17, wherein at least one intermediate conductive contact directly and selectively contacting at least one intermediate conducting layer of the precursor structure is fabricated by a process comprising: (a) selectively etching the precursor structure to form an intermediate pit defined by a bottom and multiple sidewalls, wherein the bottom of said second pit exposes the upper surface of the lowermost conducting layer, and wherein the sidewalls of said intermediate pit expose the other conducting layer (s) and the one or more intermediate insulating layers;
(b) regrowing a first layer of insulating material over the lowermost conducting layer in said intermediate pit, wherein an upper surface of said first layer of insulating material is substantially aligned with a lower surface of the intermediate conducting layer; (c) regrowing a layer of conducting material over the first layer of insulating material in said intermediate pit, wherein an upper surface of said layer of conducting material is substantially aligned with an upper surface of the intermediate conducting layer;
(d) regrowing a second layer of insulating material over the layer of conducting material to fill said intermediate pit;
(e) selectively etching the regrown second layer of insulating material to form an isolated via opening that exposes the upper surface of said layer of conducting material as regrown in step (c) ; and
(f) filling the isolated via opening with a contact material, thereby forming the intermediate conductive contact, which is directly connected with the intermediate conducting layer and is isolated from the other conducting layer (s) by the first layer of insulating material regrown in step (b) and the second layer of insulating material regrown in step (d) .
19. A coupled quantum well structure, comprising: (i) two or more quantum wells that are arranged and constructed for tunneling coupling at degenerate energy levels, and (ii) two or more conductive contacts, each of which is directly and selectively connected with one of the quantum wells.
20. A memory cell comprising: a plurality of insulating layers; at least first, second and third conducting layers spaced apart by said insulating layers, wherein quantum-mechanical confinement of free electrons exists in each of said first, second and third conducting layers; at least first, second and third electrodes, which are directly and selectively contacted with said first, second and third conducting layers respectively; a first voltage applicator for applying a predetermined voltage between the first and third conducting layers through the first and third electrodes, in such a manner that no tunneling current flows directly between said first and third conducting layers; and a second voltage applicator for applying a variable voltage to the second conducting layer through the second electrode, in such a manner that a tunneling current can flow either between said first and second conducting layers, defining a first memory state, or between said second and third conducting layers, defining a second, different memory state.
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4717545B2 (en) * 2005-08-01 2011-07-06 シャープ株式会社 Method for manufacturing photoelectric conversion element
US8309387B2 (en) * 2007-04-13 2012-11-13 David Forehand Improving back-contact performance of group VI containing solar cells by utilizing a nanoscale interfacial layer
EP2113945A1 (en) * 2008-04-30 2009-11-04 3S Swiss Solar Systems AG Method for producing contact for solar cells
US20130201550A1 (en) * 2011-01-04 2013-08-08 National Institute For Materials Science Electronic Printable Medium, Electronic Print Device and Method of Printing on Electronic Printable Medium
US8541773B2 (en) * 2011-05-02 2013-09-24 Intel Corporation Vertical tunneling negative differential resistance devices
US9029914B2 (en) * 2012-11-26 2015-05-12 Triquint Semiconductor, Inc. Group III-nitride-based transistor with gate dielectric including a fluoride -or chloride- based compound
US8907378B2 (en) * 2013-03-15 2014-12-09 Mitsubishi Electric Research Laboratories, Inc. High electron mobility transistor with multiple channels
US9275916B2 (en) * 2013-05-03 2016-03-01 Infineon Technologies Ag Removable indicator structure in electronic chips of a common substrate for process adjustment
US10587348B2 (en) * 2017-09-15 2020-03-10 Swimmersive Co. Systems and methods for underwater coaching systems
WO2019196008A1 (en) * 2018-04-10 2019-10-17 雄安华讯方舟科技有限公司 Resonant tunneling diode wafer structure having high peak-to-valley current ratio, and preparation method therefor
US10684414B1 (en) * 2019-01-29 2020-06-16 Ciene Corporation Interconnect between different multi-quantum well waveguides in a semiconductor photonic integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194061A2 (en) * 1985-02-28 1986-09-10 Tokyo Institute Of Technology Improvements in semiconductor structures and devices
GB2303246A (en) * 1995-07-07 1997-02-12 Toshiba Cambridge Res Center Resonant tunneling semiconductor device
US5625589A (en) 1995-02-22 1997-04-29 International Business Machines Corporation Static memory cell with spaced apart conducting layers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825049A (en) * 1996-10-09 1998-10-20 Sandia Corporation Resonant tunneling device with two-dimensional quantum well emitter and base layers
US7442953B2 (en) * 1999-06-14 2008-10-28 Quantum Semiconductor Llc Wavelength selective photonics device
GB2362506A (en) * 2000-05-19 2001-11-21 Secr Defence Field effect transistor with an InSb quantum well and minority carrier extraction
US6949776B2 (en) * 2002-09-26 2005-09-27 Rockwell Scientific Licensing, Llc Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194061A2 (en) * 1985-02-28 1986-09-10 Tokyo Institute Of Technology Improvements in semiconductor structures and devices
US5625589A (en) 1995-02-22 1997-04-29 International Business Machines Corporation Static memory cell with spaced apart conducting layers
GB2303246A (en) * 1995-07-07 1997-02-12 Toshiba Cambridge Res Center Resonant tunneling semiconductor device

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
A. PALEVSKI ET AL.: "Resistance Resonance in Coupled Potential Wells", PHYSICAL REVIEW LETTERS, vol. 65, no. 15, 1990, pages 1929
I. B. SPIELMAN ET AL.: "Observation of a Linearly Dispersing Collective Mode in a Quantum Hall Ferromagnet", PHYSICAL REVIEW LETTERS, vol. 87, no. 3, 2001
J.A. SIMMONS ET AL.: "Unipolar Complementary Bistable Memories Using Gate-Controlled Negative Differential Resistance in a 2D-2D Quantum Tunneling Transistor", INTERNATIONAL ELECTRON DEVICES MEETING, 7 December 1997 (1997-12-07), pages 755 - 758
J.P. EISENSTEIN ET AL.: "Independently Contracted Two-Dimensional Electron Systems in Double Quantum Wells", APPL. PHYS. LETT., vol. 57, no. 26, 1990, pages 2324
M. WATANABE ET AL.: "CaF2/CdF2 Double-Barrier Resonant Tunneling Diode with High Room-Temperature Peak-to-Valley Ratio", JAPANESE JOURNAL OF APPL. PHYS., vol. 39, no. 7B, 2000, pages 716
RUBEL H ET AL: "Fabrication of independently contacted and tuneable 2D-electron-hole systems in GaAs/AlGaAs double quantum wells", MATERIALS SCIENCE AND ENGINEERING B, ELSEVIER SEQUOIA, LAUSANNE, CH, vol. 51, no. 1-3, 27 February 1998 (1998-02-27), pages 207 - 211, XP004129565, ISSN: 0921-5107 *
RUBEL H ET AL: "STUDY OF THE CARRIER DENSITY DEPENDENCE OF THE FRICTIONAL DRAG BETWEEN CLOSELY SPACED TWO-DIMENSIONAL ELECTRON GASES", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, IOP, BRISTOL, GB, vol. 10, no. 9, 1 September 1995 (1995-09-01), pages 1229 - 1232, XP000522157, ISSN: 0268-1242 *
WATANABE M ET AL: "CaF2/CdF2 double-barrier resonant tunneling diode with high room-temperature peak-to-valley ratio", JAPANESE JOURNAL OF APPLIED PHYSICS, PART 2 (LETTERS) JAPAN SOC. APPL. PHYS JAPAN, vol. 39, no. 7B, 15 July 2000 (2000-07-15), pages L716 - L719, XP002424109, ISSN: 0021-4922 *
Y. KATAYAMA ET AL.: "Lumped Circuit Model of Two-Dimensional Tunneling Transistors", APPL. PHYS. LETT., vol. 62, no. 20, 1993, pages 2563
Y. KATAYAMA: "New Complementary Logic Circuits using Coupled Quantum Wells", IEEE, 2004

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