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System of virtual data channels across clock boundaries in an integrated circuit

Info

Publication number
WO2007056735A3
WO2007056735A3 PCT/US2006/060629 US2006060629W WO2007056735A3 WO 2007056735 A3 WO2007056735 A3 WO 2007056735A3 US 2006060629 W US2006060629 W US 2006060629W WO 2007056735 A3 WO2007056735 A3 WO 2007056735A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
lines
physical
system
clock
connection
Prior art date
Application number
PCT/US2006/060629
Other languages
French (fr)
Other versions
WO2007056735A2 (en )
Inventor
Anthony Mark Jones
Original Assignee
Ambric Inc
Anthony Mark Jones
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/405Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • H04L12/40019Details regarding a bus master
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information

Abstract

This disclosure relates to a system of communicating data within an integrated circuit across different clock boundaries. Multiple components can share common physical communication lines between elements within the system, even if those elements are in different clock domains. In some aspects, only one component can access the physical lines at a given time and a selection device chooses which component is active on the physical lines and makes the appropriate connection to the lines. The selection and connection can be completed without requiring or reporting information to the components, and is thus transparent.
PCT/US2006/060629 2005-07-26 2006-11-07 System of virtual data channels across clock boundaries in an integrated circuit WO2007056735A3 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US73462305 true 2005-11-07 2005-11-07
US60/734,623 2005-11-07
US11/340,957 2006-01-27
US11340957 US7801033B2 (en) 2005-07-26 2006-01-27 System of virtual data channels in an integrated circuit
US11/458,061 2006-07-17
US11458061 US20070038782A1 (en) 2005-07-26 2006-07-17 System of virtual data channels across clock boundaries in an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20060839752 EP1952583A4 (en) 2005-11-07 2006-11-07 System of virtual data channels across clock boundaries in an integrated circuit

Publications (2)

Publication Number Publication Date
WO2007056735A2 true WO2007056735A2 (en) 2007-05-18
WO2007056735A3 true true WO2007056735A3 (en) 2007-12-13

Family

ID=56290868

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2006/060629 WO2007056735A3 (en) 2005-07-26 2006-11-07 System of virtual data channels across clock boundaries in an integrated circuit
PCT/US2006/060631 WO2007056737A3 (en) 2005-07-26 2006-11-07 Reconfigurable processing array having hierarchical communication network

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2006/060631 WO2007056737A3 (en) 2005-07-26 2006-11-07 Reconfigurable processing array having hierarchical communication network

Country Status (2)

Country Link
EP (1) EP1952583A4 (en)
WO (2) WO2007056735A3 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319771A (en) * 1989-05-10 1994-06-07 Seiko Epson Corporation CPU clock generator having a low frequency output during I/O operations and a high frequency output during memory operations
US6636922B1 (en) * 1999-03-17 2003-10-21 Adaptec, Inc. Methods and apparatus for implementing a host side advanced serial protocol
US20050044324A1 (en) * 2002-10-08 2005-02-24 Abbas Rashid Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5577213A (en) * 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
US5799208A (en) * 1996-04-03 1998-08-25 United Microelectronics Corporation Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6963535B2 (en) * 2000-12-28 2005-11-08 Intel Corporation MAC bus interface
US6816562B2 (en) * 2003-01-07 2004-11-09 Mathstar, Inc. Silicon object array with unidirectional segmented bus architecture
US7191256B2 (en) * 2003-12-19 2007-03-13 Adams Lyle E Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319771A (en) * 1989-05-10 1994-06-07 Seiko Epson Corporation CPU clock generator having a low frequency output during I/O operations and a high frequency output during memory operations
US6636922B1 (en) * 1999-03-17 2003-10-21 Adaptec, Inc. Methods and apparatus for implementing a host side advanced serial protocol
US20050044324A1 (en) * 2002-10-08 2005-02-24 Abbas Rashid Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1952583A4 *

Also Published As

Publication number Publication date Type
WO2007056735A2 (en) 2007-05-18 application
EP1952583A4 (en) 2009-02-04 application
WO2007056737A2 (en) 2007-05-18 application
WO2007056737A3 (en) 2007-12-06 application
EP1952583A2 (en) 2008-08-06 application

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Legal Events

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121 Ep: the epo has been informed by wipo that ep was designated in this application
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