WO2007052584A1 - 積層回路基板の製造方法、回路板およびその製造方法 - Google Patents
積層回路基板の製造方法、回路板およびその製造方法 Download PDFInfo
- Publication number
- WO2007052584A1 WO2007052584A1 PCT/JP2006/321623 JP2006321623W WO2007052584A1 WO 2007052584 A1 WO2007052584 A1 WO 2007052584A1 JP 2006321623 W JP2006321623 W JP 2006321623W WO 2007052584 A1 WO2007052584 A1 WO 2007052584A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit board
- conductor
- interlayer adhesive
- film
- laminated
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000000853 adhesive Substances 0.000 claims abstract description 171
- 230000001070 adhesive effect Effects 0.000 claims abstract description 171
- 239000011229 interlayer Substances 0.000 claims abstract description 155
- 230000001681 protective effect Effects 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000004020 conductor Substances 0.000 claims description 224
- 238000004519 manufacturing process Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 26
- 238000010030 laminating Methods 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000011247 coating layer Substances 0.000 claims description 12
- -1 polyethylene terephthalate Polymers 0.000 claims description 11
- 229920001721 polyimide Polymers 0.000 claims description 11
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 9
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 5
- 239000009719 polyimide resin Substances 0.000 claims description 5
- 239000004743 Polypropylene Substances 0.000 claims description 2
- 229920001225 polyester resin Polymers 0.000 claims description 2
- 239000004645 polyester resin Substances 0.000 claims description 2
- 229920013716 polyethylene resin Polymers 0.000 claims description 2
- 229920001155 polypropylene Polymers 0.000 claims description 2
- 229920005990 polystyrene resin Polymers 0.000 claims description 2
- 239000010408 film Substances 0.000 description 110
- 239000010410 layer Substances 0.000 description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 239000011889 copper foil Substances 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- IUVCFHHAEHNCFT-INIZCTEOSA-N 2-[(1s)-1-[4-amino-3-(3-fluoro-4-propan-2-yloxyphenyl)pyrazolo[3,4-d]pyrimidin-1-yl]ethyl]-6-fluoro-3-(3-fluorophenyl)chromen-4-one Chemical compound C1=C(F)C(OC(C)C)=CC=C1C(C1=C(N)N=CN=C11)=NN1[C@@H](C)C1=C(C=2C=C(F)C=CC=2)C(=O)C2=CC(F)=CC=C2O1 IUVCFHHAEHNCFT-INIZCTEOSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 235000011470 Adenanthera pavonina Nutrition 0.000 description 1
- 240000001606 Adenanthera pavonina Species 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 101001012040 Pseudomonas aeruginosa (strain ATCC 15692 / DSM 22644 / CIP 104116 / JCM 14847 / LMG 12228 / 1C / PRS 101 / PAO1) Immunomodulating metalloprotease Proteins 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- QKAJPFXKNNXMIZ-UHFFFAOYSA-N [Bi].[Ag].[Sn] Chemical compound [Bi].[Ag].[Sn] QKAJPFXKNNXMIZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
Definitions
- the present invention relates to a method for manufacturing a laminated circuit board, a circuit board, and a method for manufacturing the circuit board.
- a build-up method is employed as a technique for stacking such multilayer circuit boards.
- the build-up method is a method in which interlayer connection is made between single layers while a resin layer composed only of a resin and a conductor layer are stacked.
- This build-up method is broadly divided into a method of forming via holes in the resin layer and connecting the force layers, and a method of forming an interlayer connection portion and laminating the resin layers.
- the interlayer connection part is divided into a case where the via hole is formed with a contact and a case where it is formed with a conductive paste.
- a fine via hole for interlayer connection is formed in the resin layer with a laser, and the via hole is electrically bonded to copper paste or the like.
- a method of filling a hole with an agent and obtaining an electrical connection with this conductive adhesive! See, for example, JP-A-8-316598.
- one of the methods for forming a multi-layer substrate having a thin-lined circuit is a bonding method using bump bonding, and is formed by the following method, for example.
- a substrate 2 having conductor posts 204 made of copper and metal, or copper and an alloy, and a film 5 with a layer indirect adhesive are prepared (FIG. 2 (a)).
- the substrate 2 having the conductor posts 204 and the film 5 with an inter-layer adhesive are thermocompression bonded (FIGS. 2 (b) and (c)).
- a substrate 3 having lands 302 for connection to the conductor posts 204 is prepared (FIG. 2).
- the void portion 602 lacking the adhesive is not completely filled with heat and pressure at the time of laminating and crimping, and the void portion remains (FIGS. 2 (g) and (h)).
- Interlaminar adhesive 104 may remain on the top 206 of 04. Therefore, even if metal bonding is performed, the interlayer adhesive 104 remains between the conductor post 204 and the conductor pad 302, and sufficient electrical connection may not be obtained (FIG. 3 (h)).
- Figures 3 (a) to 3 (c) are the same as in Figure 2.
- a film 25 with an interlayer adhesive is thermocompression bonded to the circuit board 3 having the conductor pads 302 that receive the conductor posts (FIGS. 8A and 8B).
- the pressure on the circuit may be insufficient, such as in the case of a complicated conductor circuit or when the circuit density is high, and the interlayer adhesive 124 is completely eliminated.
- Can not conductor pad 302 or conductor Interlayer adhesive 124 may remain on the circuit surface of circuit 306 (FIG. 8 (c)).
- the substrate 211 obtained in 07 (f) and the substrate 311 obtained in FIG. 8 (c) are set so that the adhesive faces face each other (FIG. 9 (a)), and are heated and cured to form a multilayer.
- the substrate 23 is obtained (Fig. 9 (c)).
- the conductor pad top 106 covered with the adhesive and the adhesive on the conductor circuit surfaces 302 and 306 are not completely removed (Fig. 9 (b)). Connection may not be obtained (Fig. 9 (c)).
- JP-A-8-195560 discloses the following method. Using a conductor post having a solder layer formed at the tip, the conductor post is passed through an uncured resin layer and an uncured adhesive layer at a temperature lower than the melting temperature of the solder. After pressurizing the connection pad at about 2.5 MPa, the adhesive layer is cured. Further, a solder joint is formed by melting and cooling the solder.
- the inner layer circuit is distorted or the circuit board is wavy due to the distortion of the inner layer circuit. .
- the distortion tends to become more pronounced.
- Patent Document 1 Japanese Patent Application Laid-Open No. 8-316598
- Patent Document 2 Japanese Patent Laid-Open No. 11-54934
- Patent Document 3 Japanese Patent Laid-Open No. 2000-059028
- Patent Document 4 JP-A-8-195560
- the present invention has been made in view of the above circumstances, and provides a method for manufacturing a laminated circuit board, a circuit board, or a method for manufacturing the same capable of stable layer indirect connection in a simple process. It is in.
- the method for producing a laminated circuit board comprises a step of preparing a first film in which a first protective film and a first interlayer adhesive are laminated, a first substrate, and the first substrate A step of preparing a first circuit board having a conductor post protruding from a base material; and the first film and the first circuit board so that the first interlayer adhesive and the conductor post are in contact with each other.
- the method for producing a laminated circuit board of the present invention includes a step of preparing a first film in which a first protective film and a first layer indirect adhesive are laminated, a first base material, A step of preparing a first circuit board having a conductor post protruding from a first base material; and the first film and the first film so that the first inter-layer adhesive and the conductor post are in contact with each other.
- a method of manufacturing a circuit board can be obtained by etching the laminated circuit board obtained by the above method, and further, a circuit board can be obtained by this method.
- FIG. 1 is a cross-sectional view of a manufacturing process of a laminated circuit board showing one embodiment of the present invention.
- FIG. 2 is a manufacturing process sectional view of a multilayer circuit board showing a conventional example.
- FIG. 3 is a cross-sectional view of a manufacturing process of a laminated circuit board showing a conventional example.
- FIG. 4 is a cross-sectional view of a manufacturing process of a circuit board showing an embodiment of the present invention.
- FIG. 5 is a cross-sectional view of a circuit board manufacturing process showing an embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a manufacturing process of a laminated circuit board showing one embodiment of the present invention.
- FIG. 7 is a process cross-sectional view illustrating a conventional circuit board manufacturing method.
- FIG. 8 is a process cross-sectional view illustrating a conventional circuit board manufacturing method.
- FIG. 9 is a process cross-sectional view illustrating a conventional method for manufacturing a laminated circuit board.
- FIG. 10 is a cross-sectional view of a laminated circuit board showing an embodiment of the present invention.
- FIG. 11 is a cross-sectional view of a circuit board showing an embodiment of the present invention.
- FIG. 1 is a cross-sectional view showing an embodiment of a method for manufacturing a laminated circuit board according to the present invention. This manufacturing method includes the following steps as shown in FIG.
- the first protective film 102 is peeled from the first interlayer adhesive 104, the first interlayer adhesive on the top of the conductor post 204 is selectively removed, the top is exposed, and the first The process of attaching the removal part 105 to the protective film 102 side (Fig. 1 (e)),
- the first protective film 102 As shown in FIG. First, the first interlayer adhesive 104 is applied and dried to form the protective film 1 with an interlayer adhesive.
- the first protective film 102 uses at least one resin film in which polyethylene terephthalate resin film, polyethylene resin film, polyimide resin film, polyester resin film, polypropylene resin film, and polystyrene resin film force are also selected.
- the releasability of the interlayer adhesive 104 and the protective film 102 is also preferable.
- a polyethylene terephthalate resin film is more preferable from the viewpoint of economy.
- the thickness of the first protective film 102 is preferably 3 ⁇ m or more and 25 ⁇ m or less.
- the thickness of the first protective film 102 is more preferably 9 m or more and 15 m. First protection If the thickness of the protective film 102 is within this range, the projection of the conductor post can be reliably embedded and the first protective film 102 can be easily peeled off.
- the thickness of the first interlayer adhesive 104 is preferably thinner than the height at which the substrate surface force of the conductor post 204 protrudes. If the thickness of the first interlayer adhesive 104 is thinner, the first interlayer adhesive 104 at the top 206 of the conductor post is removed when the first protective film 102 is peeled off from the top of the conductor post 204. It becomes easy.
- the first circuit board 2 having the conductor posts 204 is prepared.
- the base material 202 include resin films such as polyether ether ketone film and polyether sulfone film, polyimide resin, epoxy resin, phenol resin, cyanate resin, and liquid crystal polymer. A cured product or a laminate of these can be used. Among these, a resin film typified by a polyimide film is preferable. Thereby, heat resistance can be improved. Furthermore, flexibility can be exhibited. As described above, the height of the protrusion of the substrate surface 204 of the conductor bump 204 is higher than the thickness of the interlayer adhesive 104, and is more preferable!
- the thickness of the substrate is not particularly limited, but is preferably 9 ⁇ m or more and 50 ⁇ m or less, particularly 12
- the plating time for forming the conductor post can be shortened.
- the first interlayer adhesive 104 is softened by heating with a vacuum laminator or the like, and the protrusions of the conductor post 204 are embedded without voids by the first interlayer adhesive 104 by pressurization (FIG. 1 (d)). . At this time, the first interlayer adhesive 104 on the top 206 of the conductor post is embedded in the protrusion height of the conductor post 204. The first interlayer adhesive 104 is not removed on the top 206 of the conductor post 204. It remains thin.
- the step of peeling off the first protective film 102 (FIG. 1 (e)) will be described.
- the first protective film 102 With the first interlayer adhesive 104 and the conductor post 204 laminated (FIG. 1 (d)), the first protective film 102 is peeled off.
- the angle of the film from which the first protective film 102 is peeled off is preferably about 180 °. The closer the peeling angle is to 180 °, the more the peeling
- the first interlayer adhesive 104 can be uniformly left on the surface of the base material 202 on the side of the first circuit board 2 where the force is small.
- the first interlayer adhesive 104 at the top 206 of the conductor post 204 is thin, the first interlayer adhesive 104 at the top 206 of the conductor post 102 is peeled off at the same time as the first protective film 102 is peeled off. The remaining part is removed with it attached to the 102 side. On the other hand, the top portion 206 of the conductor post 204 is exposed, so that the conductor pad can be stably connected.
- the base material 304 may be the same material as the first circuit board 2 or may be different.
- a method of reading and aligning a positioning mark formed in advance as a conductor pattern with an image recognition device, a method of aligning with a positioning pin, etc. can be used! ,.
- calothermal pressure is applied in a vacuum state, and the conductive pattern of the second circuit board 3 is embedded and molded with the first interlayer adhesive 104.
- the temperature is increased until the solder is melted, and the conductor post 204 and the conductor pad 302 are electrically joined (FIG. 1 (h)).
- 4 to 6 are cross-sectional views showing a method for manufacturing a laminated circuit board in the present embodiment.
- This manufacturing method includes the following steps as shown in FIG. 4 and FIG.
- the first protective film 102 is peeled off from the first interlayer adhesive 104, and the first interlayer adhesive 104 at the top 206 of the conductor post 204 is selectively removed 105 to expose the top 206. (Fig. 4 (e), (f)),
- the second protective film 112 is peeled off from the second interlayer adhesive 114, and the second interlayer adhesive 114 on the conductor surface of the conductor pad 302 is selectively removed 115 to remove the second protective film 112 from the conductor surface. (Fig. 5 (e), (f)),
- the base material 304 may be the same material as the first circuit board 2 or may be different. Since heating is performed when the conductor post 204 and the conductor pad 302 are laminated, the material expands and contracts, and internal stress is easily generated. For this reason, it is more preferable to use materials having the same thermal expansion coefficient because internal stress can be prevented.
- the second protective film 112 in the step of preparing the protective film 10 with an interlayer adhesive in which the second protective film 112 and the second interlayer adhesive 114 are laminated, the second protective film 112 as shown in FIG. 5 (b).
- a second interlayer adhesive 114 is applied on the top and dried to form a protective film 10 with an interlayer adhesive.
- the adhesiveness to the conductor is smaller than the tackiness to the insulator. If the adhesiveness is greater than the adhesiveness to the conductor than the adhesiveness to the insulator, many interlayer adhesives 114 remain on the conductor pad 302 when the second protective film 112 is peeled off.
- the second protective film 112 a resin film similar to the protective film described above can be preferably used.
- these resin films polyethylene terephthalate resin film is more preferable from the viewpoint of economy.
- the thickness of the second protective film 112 is preferably 25 ⁇ m or more and 50 ⁇ m or less.
- the thickness of the second protective film 112 is more preferably 33 ⁇ m or more and 43 ⁇ m. If the thickness of the second protective film 112 is within this range, it can be surely embedded between the conductor pads and easily peeled off without breaking when the second protective film 112 is peeled off.
- the thickness of the second interlayer adhesive 114 is preferably not less than half the thickness of the conductor pad 302 and not more than the thickness of the conductor pad. If the thickness of the second interlayer adhesive 114 is too small, the interlayer adhesive 114 cannot be embedded between the conductor pads, and voids are likely to occur. Further, if the thickness of the second interlayer adhesive 114 is too large, the interlayer adhesive 114 becomes excessive and exists thickly on the conductor pad 302. Therefore, a large amount of the second interlayer adhesive 114 tends to remain on the conductor pad 302 when the second protective film 112 is peeled off.
- the second interlayer adhesive 114 is softened by heating with a vacuum press or the like, and the space between the conductor pads 302 is filled with the second interlayer adhesive 114 without pressure by pressurization (FIG. 2 (c)). At this time, the second interlayer adhesive 114 on the conductor pad 302 is thinner than the original interlayer adhesive because the second interlayer adhesive 114 flows between the conductor pads 302. Further, the second interlayer adhesive 114 and the second protective film 112 are bonded by heating and pressing. In order to stabilize this adhesion, it is preferable to store for 24 hours or more in a low humidity environment.
- the step of peeling the second protective film 112 (FIG. 5 (d)) will be described.
- the second interlayer adhesive 114 and the conductor pad 302 laminated (FIG. 5 (d))
- the angle of the film from which the second protective film 112 is peeled off is preferably about 180 °. The closer the peeling angle is to 180 °, the smaller the peeling force, and the more even it can be peeled off.
- the adhesiveness of the second interlayer adhesive 114 is such that the adhesiveness to the conductor ⁇ the adhesiveness to the insulator, so that many second interlayer adhesives on the surface of the base material 304 on the second circuit board 3 side.
- the circuit board 30 having a uniform thickness of the interlayer adhesive 114 can be obtained regardless of the conductivity of the second circuit board 3.
- the first circuit board 2 and the second circuit board 3 are arranged such that the conductor post 204 and the conductor pad 302 face each other through the first interlayer adhesive 104 and the second interlayer adhesive 114.
- the process of laminating and adhering to (Fig. 6 (a), (b), (c)) will be described.
- a method of reading and aligning a positioning mark formed in advance as a conductor pattern with an image recognition device, a method of aligning with a positioning pin, etc. can be used! ,.
- calothermal pressure is applied in a vacuum state, and the conductive pattern of the second circuit board 3 is embedded and molded with the first interlayer adhesive 104.
- the temperature is raised until the solder is melted, and the conductor post 204 and the conductor pad 302 are electrically joined (FIG. 6 (c)).
- a circuit board manufacturing method including the step of etching the laminated circuit board obtained as described above can be obtained.
- FIG. 10 and FIG. 11 are cross-sectional views showing an embodiment of a method for manufacturing a laminated circuit board according to the present invention.
- FIG. 10 is a cross-sectional view of the multilayer circuit board obtained in the present embodiment
- FIG. 11A is a cross-sectional view of the first substrate
- FIG. 2B is a cross-sectional view of the second substrate.
- first substrate 17 having the first base 12 and the conductor post 16 and the second base 1 A second substrate 20 having a second conductor pad 18 for receiving 9 and a conductor post 16 is prepared (FIGS. 2A and 2B).
- first and second substrates 12 and 19 the same ones as described above can be used.
- the materials of the first and second substrates may be the same or different. Further, the thicknesses of the first and second substrates may be the same or different.
- Examples of the material constituting the first conductor pad 11 and the second conductor pad 18 include copper foil and aluminum. Among these, copper foil is preferable.
- the thickness is preferably 5 m or more and 30 ⁇ m or less, particularly 9 ⁇ m or more and 22 ⁇ m or less. When the thickness is within the above range, the circuit forming property by the etching process is particularly excellent, and the handling property (handling property) of the base material 12 after the first conductor pad 11 and the second conductor pad 18 are formed. ) Is also excellent.
- the ratio of the area of the surface on which the second conductor pad 18 is formed that the second conductor pad occupies the second substrate is preferably 30% or more and 70% or less. In particular, it is preferably 40% or more and 50% or less. If this occupation ratio is too small, the handleability of the second substrate 20 may be inferior. If the occupation ratio is too large, the interlayer adhesive 13 between the conductor post 16 and the second conductor pad 18 is eliminated. In some cases, the stability of the joints may decrease.
- the conductor post 16 includes a conductor post body portion 14 and a metal coating layer 15 that covers the conductor post body portion.
- the conductor post 16 is first formed with the conductor post body 14 by, for example, a paste or a staking method. It is preferable that the height of the conductor post body portion 14 protrudes from 5 m to 10 m from the surface of the first base 12 opposite to the surface on which the first conductor pads 11 are formed. When the height is in the above range, the plating time can be shortened, and the interlayer smoothness between the first substrate 17 and the second substrate 20 is excellent.
- the metal coating layer 15 is formed of an alloy or the like.
- a conductor post composed of the conductor post body and the metal coating layer covering the conductor post body is formed.
- the height of the conductor bump 16 is preferably 15 m or more and 30 m or less from the surface of the first substrate 12 opposite to the surface on which the first conductor pads 11 are formed. When the height is in the above range, the bonding stability between the conductor post 16 and the second conductor pad 18 is excellent.
- the metal coating layer 15 is made of, for example, a metal or an alloy.
- the metal For example, it is preferably made of tin.
- the alloy is preferably a metal coating layer 15 composed of at least two kinds of metals selected from the group consisting of tin, lead, silver, zinc, bismuth, antimony, and copper. Examples include tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, and tin-copper, but are limited to metal combinations and compositions. The most suitable one can be selected.
- Examples of the material constituting the interlayer adhesive 13 include epoxy resin-based adhesives and acrylic resin-based adhesives. Among these, an epoxy resin adhesive having flux activity is preferable. Thereby, the oxide film on the surfaces of the metal coating layer 15 and the second conductor pad 18 is removed, and the bonding stability of the conductor post 16 and the second conductor pad 18 is improved. In addition, when a polyimide film or the like is used as the first substrate 12, the adhesion is particularly excellent.
- the thickness of the interlayer adhesive 13 is not less than the height protruding from the first base 12 of the conductor post body 14 and the height protruding from the first base 12 of the conductor post 16. It is preferable that: When the thickness is within the above range, the joint stability between the conductor post 16 and the second conductor pad 18 is particularly excellent, and both the adhesion and the bleeding out of the adhesive are excellent. Further, when the thickness is within the above range, voids with good embedding by the interlayer adhesive 13 of the second conductor pad 18 are not generated.
- the interlayer adhesive 13 can be laminated on the first substrate 12 by a liquid coating method, a method of heating and pressing with a vacuum laminator or the like. The latter is simpler and the thickness of the interlayer adhesive 13 is stable.
- the predetermined temperature is preferably preheated to about 230 ° C to about 280 ° C, particularly about 250 ° C to about 270 ° C.
- the interlayer adhesive 13 Since the viscosity of the resin is soft at about lOPa ′ S to about 400 Pa ′ S, the interlayer adhesive 13 between the metal coating layer 15 and the conductor pad 18 can be eliminated.
- the metal coating layer 15 since the metal coating layer 15 is melted, the pressure concentration on the conductor post 16 is alleviated, so that the first substrate 17 and the second substrate 20 are distorted or the substrate is wavy due to the distortion. Can be prevented.
- the electrical connection between the first substrate 17 and the second substrate 20 is stabilized by forming a good fillet.
- the predetermined pressure is preferably about 0.5 MPa to about 2 MPa, particularly about 1.5 MPa to about 2 MPa.
- the pressure is within the above range, the interlayer adhesive 13 between the metal coating layer 15 and the second conductor pad 18 can be eliminated. If the pressure is too low, the interlayer adhesive 13 may not be completely eliminated. If the pressure is too high, the first substrate 17 and the second substrate 20 may be distorted, and the substrate may be wavy due to the distortion. In addition, the amount of the layer indirect adhesive oozes out, and the interlayer thickness may become unstable.
- a conductor pad is formed on the first circuit board, and a conductor post is included in the upper layer of the first circuit board. It may be a manufacturing method of a laminated circuit board in which the second circuit board is laminated and bonded. In this way, a plurality of layers may be added to the desired first circuit board or second circuit board.
- connection rate is expressed as the number of conductions (conductivity) with respect to the total number of junctions.
- the process was performed according to the process described in FIG. That is, a polyethylene terephthalate film 12 ⁇ m was prepared as a protective film, and an interlayer adhesive 13 ⁇ m was applied and dried by a coater.
- a 2-layer single-sided circuit board SE1310 made by Ube Industries
- SE1310 made by Ube Industries
- the plating height was 23 m from the base material, and the circuit was formed by etching.
- the substrate with conductor posts and the film with an interlayer adhesive were thermocompression bonded with a vacuum laminator at 120 ° C. and 0.4 MPa.
- the protective film polyethylene terephthalate film was peeled off at an angle of 180 ° to form a circuit board in which the interlayer adhesive on the top of the conductor post was selectively removed.
- a circuit was formed by etching a two-layer double-sided circuit board (PKW1012ECU manufactured by Arisawa Manufacturing Co., Ltd.) having a copper peeling force m and a base material having a polyimide film thickness of 25 m. In this way, a first circuit board having a conductor post was formed.
- a laminated circuit board in which the interlayer adhesive on the top of the conductor post was selectively removed along the process shown in FIG. 1 was formed.
- a circuit board was formed along the process shown in FIG. Since the protective film is thick, it cannot follow the shape of the protruding conductor post.In the protective film peeling process, a large amount of interlayer adhesive is taken on the protective film and laminated and adhered as shown in Fig. 2 (e). when, as shown in FIG. 2 (h), was sure that the laminated circuit board interlayer adhesive around the conductive post has a greater lacking space is formed 0
- a circuit board was formed along the process shown in FIG. Since the interlayer adhesive is thick, the interlayer adhesive remains on the top of the protruding conductor post.In the process after the protective film is peeled off, the interlayer adhesive is applied to the top of the conductor post as shown in Fig. 3 (f). As shown in FIG. 3 (h), it was confirmed that an interlayer adhesive remained between the conductor posts and the conductor pads, and a multilayer circuit board was formed.
- Experimental Example Table 1 shows the results of the electrical bonding rate of the substrates treated by the methods of A1 to A3.
- Experimental Example Al and A2 had a good bonding rate.
- the space around the joint between the conductor post and the conductive pad was a gap, so the gap during bonding expanded and the bonding rate was low.
- the interlayer adhesive was interposed between the conductor posts and the conductor pads, and the bonding rate was low.
- a first circuit board having conductor posts was formed in the same manner as in Example A1.
- a polyethylene terephthalate film 38 ⁇ m was prepared as a protective film, and an interlayer adhesive 8 IX m was applied and dried with a coater.
- This two-layer double-sided circuit board and a film with an interlayer adhesive were thermocompression bonded with a vacuum press at 150 ° C and 0.8 MPa, and left for 24 hours in an environment with a humidity of 10% or less.
- the protective film was peeled off at an angle of 180 ° to form a circuit board in which the interlayer adhesive on the conductor pad was selectively removed.
- the 2nd circuit board which has a conductor node was formed.
- the two circuit boards were subjected to automatic alignment by image recognition using a conductor pattern, followed by vacuum thermocompression bonding at 150 ° C and 0.3 MPa, followed by vacuum thermocompression at 260 ° C and 0.3 MPa.
- a laminated circuit board was prepared in the same manner as in Experimental Example B 1 except that the thickness of the interlayer adhesive laminated on the two-layer double-sided circuit board was 12 m.
- a laminated circuit board was created in the same manner as in Experimental Example B1, except that the adhesive of the interlayer adhesive laminated on the two-layer double-sided circuit board was made substantially the same as the adhesive to the conductor and the adhesive to the insulator. . When the protective film was peeled off, it was confirmed that a slight amount of interlayer adhesive remained on the conductor pad.
- Table 2 shows the results of the electrical bonding rate of the multilayer circuit boards processed by the methods of Experimental Examples B1 to B4. Experimental examples B1 to B4 had good bonding rates.
- Fig. 10 ⁇ Performed along the process described in L1.
- a two-layer single-sided circuit board (SE1310 manufactured by Ube Industries, Ltd.) with a copper foil of 12 ⁇ m and a base material of polyimide film thickness of 25 ⁇ m was formed with a diameter via from the opposite side of the copper foil by UV laser. .
- the copper post height was 8 ⁇ m from the substrate, the metal coating layer was 15 ⁇ m, and the conductor post height was 23 ⁇ m from the substrate.
- a circuit was formed by etching, and the substrate with a conductor post and an interlayer adhesive having a thickness of 13 m were thermocompression bonded with a vacuum laminator at 120 ° C. and 0. IMPa.
- a circuit was formed by etching a two-layer double-sided circuit board (PKW1012ECU made by Arisawa Seisakusho) with a copper foil of 12 / ⁇ ⁇ and a base film of 25 ⁇ m thick polyimide film. The ratio occupied by the conductor circuit at this time was 50%.
- the hot plate was heated to 260 ° C in advance with a vacuum press and pressed at 2 MPa for 5 minutes.
- the thickness of the interlayer adhesive was 16 m. Otherwise, a laminated circuit board was produced in the same manner as in Example C1.
- the thickness of the interlayer adhesive was 25 m. Otherwise, a laminated circuit board was produced in the same manner as in Example C1.
- the height of the conductor post was set to 35 m. Otherwise, a laminated circuit board was produced in the same manner as in Example C1.
- the first circuit board having no conductor post protruding from the base material was used. Otherwise, a laminated circuit board was fabricated in the same manner as in Experimental Example A1.
- Experimental Example Table 3 shows the evaluation results of the laminated circuit board processed by the methods C1 to C6. Examples Examples C1 to C4 have good force Comparative Examples C5 and C6 had defects in substrate performance.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06822580A EP1954112A4 (en) | 2005-11-04 | 2006-10-30 | METHOD FOR PRODUCING A MULTILAYER CONDUCTOR PLATE, CIRCUIT BOARD AND METHOD FOR PRODUCING THE CIRCUIT BOARD |
CN2006800412537A CN101300912B (zh) | 2005-11-04 | 2006-10-30 | 多层电路板及其制造方法、电路板及其制造方法 |
US12/092,160 US8153901B2 (en) | 2005-11-04 | 2006-10-30 | Method for fabricating multilayer circuit board, circuit plate, and method for fabricating the circuit plate |
JP2007542717A JP5109662B2 (ja) | 2005-11-04 | 2006-10-30 | 積層回路基板の製造方法および回路板の製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2005-321336 | 2005-11-04 | ||
JP2005-321406 | 2005-11-04 | ||
JP2005321406 | 2005-11-04 | ||
JP2005321336 | 2005-11-04 |
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WO2007052584A1 true WO2007052584A1 (ja) | 2007-05-10 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/JP2006/321623 WO2007052584A1 (ja) | 2005-11-04 | 2006-10-30 | 積層回路基板の製造方法、回路板およびその製造方法 |
Country Status (8)
Country | Link |
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US (1) | US8153901B2 (ja) |
EP (1) | EP1954112A4 (ja) |
JP (1) | JP5109662B2 (ja) |
KR (1) | KR20080064872A (ja) |
CN (1) | CN101300912B (ja) |
SG (1) | SG166824A1 (ja) |
TW (1) | TW200731900A (ja) |
WO (1) | WO2007052584A1 (ja) |
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KR101538186B1 (ko) * | 2007-12-11 | 2015-07-20 | 스미토모 덴키 고교 가부시키가이샤 | 회로판, 회로판의 제조 방법 및 커버 레이 필름 |
JP2015201636A (ja) * | 2014-03-31 | 2015-11-12 | 大日本印刷株式会社 | 多層配線基板の製造方法、及び多層配線基板 |
JP2015201635A (ja) * | 2014-03-31 | 2015-11-12 | 大日本印刷株式会社 | 多層配線基板の製造方法 |
JP2015201637A (ja) * | 2014-03-31 | 2015-11-12 | 大日本印刷株式会社 | 多層配線基板の製造方法及び多層配線基板 |
US10575411B2 (en) | 2008-07-02 | 2020-02-25 | Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno | Method of providing conductive structures in a multi-foil system and multifoil system comprising same |
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US9631054B2 (en) | 2010-07-23 | 2017-04-25 | E I Du Pont De Nemours And Company | Matte finish polyimide films and methods relating thereto |
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JP2011096900A (ja) * | 2009-10-30 | 2011-05-12 | Fujitsu Ltd | 導電体およびプリント配線板並びにそれらの製造方法 |
US20130011645A1 (en) * | 2010-03-01 | 2013-01-10 | E. I. Du Pont De Nemours And Company | Multilayer film for electronic circuitry applications and methods relating thereto |
US9095085B2 (en) * | 2013-03-29 | 2015-07-28 | Kinsus Interconnect Technology Corp. | Method of manufacturing a stacked multilayer structure |
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- 2006-10-30 US US12/092,160 patent/US8153901B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
JPWO2007052584A1 (ja) | 2009-04-30 |
CN101300912B (zh) | 2010-11-10 |
EP1954112A4 (en) | 2009-09-23 |
JP5109662B2 (ja) | 2012-12-26 |
US20090126975A1 (en) | 2009-05-21 |
TW200731900A (en) | 2007-08-16 |
US8153901B2 (en) | 2012-04-10 |
EP1954112A1 (en) | 2008-08-06 |
KR20080064872A (ko) | 2008-07-09 |
SG166824A1 (en) | 2010-12-29 |
CN101300912A (zh) | 2008-11-05 |
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