WO2007029166A2 - Full-adder modules and multiplier devices using the same - Google Patents
Full-adder modules and multiplier devices using the same Download PDFInfo
- Publication number
- WO2007029166A2 WO2007029166A2 PCT/IB2006/053099 IB2006053099W WO2007029166A2 WO 2007029166 A2 WO2007029166 A2 WO 2007029166A2 IB 2006053099 W IB2006053099 W IB 2006053099W WO 2007029166 A2 WO2007029166 A2 WO 2007029166A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- full
- adder
- carry
- type
- control signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
Definitions
- a Type 0 full-adder generates a sum (S) output and a carry (C) output from three Boolean inputs, X, Y, and a carry-in (Z). None of the inputs or outputs is inverted. Thus, a Type 0 full-adder is equivalent to a conventional full-adder.
- a Type 1 full-adder also generates a sum (S) output and a carry (C) output from three Boolean inputs, X, Y, and Z (carry-in). However, the Z (carry- in) input and the sum output (S) are both inverted.
- the SGU 44 generates the sum (S) as described in Equations 1 and outputs it to the first output terminal 40.
- FIG. 4 a schematic diagram of an array multiplier according to the invention is shown, the array multiplier being indicated generally by 400.
- the array multiplier 400 which can be used inside the logic block of an SRAM-based FPGA, comprises a plurality of modified full adders according to the invention in an interconnected array, arranged to calculate the product terms from the input data.
- the potential of the control signal applied to full-adder modules 410 is arranged to be low (0) such that full-adder modules 410 act as Type 0 full- adders.
- any suitably arranged apparatus such as an SRAM block, may provide the control signal to the full-adder module.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Complex Calculations (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/065,633 US20080256165A1 (en) | 2005-09-05 | 2006-09-04 | Full-Adder Modules and Multiplier Devices Using the Same |
JP2008528643A JP2009507413A (en) | 2005-09-05 | 2006-09-04 | Full adder module and multiplier device using the full adder module |
EP06795898A EP1927046A2 (en) | 2005-09-05 | 2006-09-04 | Full-adder modules and multiplier devices using the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05108124 | 2005-09-05 | ||
EP05108124.8 | 2005-09-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007029166A2 true WO2007029166A2 (en) | 2007-03-15 |
WO2007029166A3 WO2007029166A3 (en) | 2007-07-05 |
Family
ID=37775134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2006/053099 WO2007029166A2 (en) | 2005-09-05 | 2006-09-04 | Full-adder modules and multiplier devices using the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US20080256165A1 (en) |
EP (1) | EP1927046A2 (en) |
JP (1) | JP2009507413A (en) |
CN (1) | CN101258464A (en) |
WO (1) | WO2007029166A2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102882513B (en) * | 2012-10-09 | 2015-04-15 | 北京大学 | Full adder circuit and chip |
KR102072543B1 (en) * | 2013-01-28 | 2020-02-03 | 삼성전자 주식회사 | Multiple data type supporting adder and method for supporting adding operation of multiple data type using the adder |
WO2017079947A1 (en) * | 2015-11-12 | 2017-05-18 | 京微雅格(北京)科技有限公司 | Adder wiring method supporting pin swapping |
CN106528046B (en) * | 2016-11-02 | 2019-06-07 | 上海集成电路研发中心有限公司 | Long bit wide timing adds up multiplier |
US10545727B2 (en) | 2018-01-08 | 2020-01-28 | International Business Machines Corporation | Arithmetic logic unit for single-cycle fusion operations |
CN110190843B (en) * | 2018-04-10 | 2020-03-10 | 中科寒武纪科技股份有限公司 | Compressor circuit, Wallace tree circuit, multiplier circuit, chip and apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58181143A (en) * | 1982-04-15 | 1983-10-22 | Matsushita Electric Ind Co Ltd | Digital multiplier |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5151875A (en) * | 1990-03-16 | 1992-09-29 | C-Cube Microsystems, Inc. | MOS array multiplier cell |
US5187679A (en) * | 1991-06-05 | 1993-02-16 | International Business Machines Corporation | Generalized 7/3 counters |
US5493524A (en) * | 1993-11-30 | 1996-02-20 | Texas Instruments Incorporated | Three input arithmetic logic unit employing carry propagate logic |
US5442577A (en) * | 1994-03-08 | 1995-08-15 | Exponential Technology, Inc. | Sign-extension of immediate constants in an alu |
US6263424B1 (en) * | 1998-08-03 | 2001-07-17 | Rise Technology Company | Execution of data dependent arithmetic instructions in multi-pipeline processors |
US7870182B2 (en) * | 2003-12-29 | 2011-01-11 | Xilinx Inc. | Digital signal processing circuit having an adder circuit with carry-outs |
-
2006
- 2006-09-04 JP JP2008528643A patent/JP2009507413A/en not_active Withdrawn
- 2006-09-04 EP EP06795898A patent/EP1927046A2/en not_active Withdrawn
- 2006-09-04 CN CNA2006800323552A patent/CN101258464A/en active Pending
- 2006-09-04 WO PCT/IB2006/053099 patent/WO2007029166A2/en active Application Filing
- 2006-09-04 US US12/065,633 patent/US20080256165A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58181143A (en) * | 1982-04-15 | 1983-10-22 | Matsushita Electric Ind Co Ltd | Digital multiplier |
Non-Patent Citations (2)
Title |
---|
BANDEIRA N ET AL: "A TWO'S COMPLEMENT ARRAY MULTIPLIER USING TRUE VALUES OF THE OPERANDS" IEEE TRANSACTIONS ON COMPUTERS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. C-32, no. 8, August 1983 (1983-08), pages 745-747, XP007901745 ISSN: 0018-9340 * |
WESTE N H E ET AL: "Excerpt" PRINCIPLES OF CMOS VLSI DESIGN. SYSTEMS PERSPECTIVE, READING, ADDISON WESLEY, US, 1985, XP007901520 * |
Also Published As
Publication number | Publication date |
---|---|
EP1927046A2 (en) | 2008-06-04 |
CN101258464A (en) | 2008-09-03 |
WO2007029166A3 (en) | 2007-07-05 |
JP2009507413A (en) | 2009-02-19 |
US20080256165A1 (en) | 2008-10-16 |
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