WO2007000726A2

WO2007000726A2 - Electronic device

Info

Publication number: WO2007000726A2
Application number: PCT/IB2006/052114
Authority: WO
Inventors: Henricus H. Van Den Berg
Original assignee: Nxp B.V.
Priority date: 2005-06-28
Filing date: 2006-06-27
Publication date: 2007-01-04
Also published as: WO2007000726A3

Abstract

An electronic device is provided comprising at least one processing module (PH) and a secure configuration managing unit, which is coupled to the at least one processing module (PH). The at least one processing module (PH) is enabled or disabled according to a reprogrammable security image. The secure configuration manager (SCM) comprises at least a first and second security setting unit (Ll, L2) for storing first and second security image settings according to the security image, respectively. The first and second security settings of the security image are reprogrammable.

Description

Electronic device

The invention relates to an electronic device and a method of enabling/disabling processing modules.

Modern semiconductor devices can be designed based on IP elements (intellectual property) which may constitute data as well as circuit information. Often these elements are to be protected from any external faltering. IP blocks are used in the design of semiconductor devices to reduce the time to market and to increase the flexibility and the functionality over different application areas. The protection of any integrated IP block has to be performed in a secure manner which is still flexible for customers in order to decide on the functionality which should be supported by the semiconductor device. For example, if a customer or user does not pay for all of the delivered integrated functions or modules, the IP block related to these functions or modules has to be disabled. Furthermore, a customer may not be allowed to make any updates in the device such that write protection to some of the sections of the memory must be implemented. Alternatively, a customer may not be allowed to read contents within a memory in order to protect any algorithm stored in a memory. Any available external interfaces may not be allowed to be utilized by an end customer. One example can be the JTAG interface. The underlying aspect is to protect access to internal IP blocks from different suppliers.

US 6,304,100 discloses a programmable semiconductor device providing security of circuit information. Here, an IP protection for FPGA (field programmable gate array) is provided. Accordingly, a pure hardware solution with a non- volatile storage is used for the IP modules. Once the security setting is being performed, any overruling is impossible. Accordingly, the semiconductor device according to this document does not allow flexibility after the security settings have been performed.

US 2003/0014653 relates to a memory device with a data security implemented in a processor. Here, user programs or codes stored in a device with an on-chip memory are to be protected. The code can be protected by two interface groups. The first group is used directly to the memory portion, while the second group can be used via the processor. The interfaces can only be disabled on a hardware basis before a boot procedure is started.

US 5,530,753 discloses an apparatus for secure hardware configuration. Here, a fusing technology is used. Furthermore, a complete separate cryptographic processor is used.

It is an object of the invention to provide an electronic device with an improved security for internal embedded security settings. This object is solved by an electronic device according to claim 1 and a method according to claim 7.

Therefore, an electronic device is provided comprising at least one processing module, and a secure configuration managing unit coupled to at least one of the processing modules for enabling or disabling at least one of the processing modules according to a reprogrammable security image. The secure configuration manager comprises at least a first and second security setting unit for storing first and second security settings according to the security image, respectively. The first and second security settings of the security image are reprogrammable .

Accordingly, the security of the processing modules is improved and various levels of security are introduced. Furthermore, the flexibility of the security settings is improved and different customers may be related to different security settings.

According to an aspect of the invention, the security configuration managing unit disables at least one of the processing modules by disabling a clock signal, by denying any read access or by denying any write access to a memory. Accordingly, the disabling can be performed on a flexible basis.

According to a further aspect of the invention, the security image is stored in the secure configuration managing unit. Alternatively, the security image can be stored in a non- volatile memory arranged in the electronic device. Therefore, the security image can be stored such that it can be reprogrammed. According to a further aspect of the invention, the electronic device comprises a plurality of power domains, wherein one of the power domains is always in an on-state. The security configuration managing unit is arranged in the power domain being always in the on- state. This is advantageous, as a wake-up sequence of the electronic device will not be required for the configuration according to the current security settings. According to still a further aspect of the invention, the electronic device comprises an interface unit being coupled to the non- volatile memory for reprogramming the security image stored in the non- volatile memory by a new security image. The device furthermore comprises a processing unit being coupled to the interface to determine whether the new security image is valid. The new security image is stored in the non-volatile memory if the processing unit has determined that the new security image is valid.

The invention also relates to a method for enabling/disabling processing modules within an electronic device. At least one of the processing modules is enabled/disabled according to the reprogrammable security image. First and second security settings are stored in at least a first and second security setting unit according to the security image. The first and second security settings of the security image are reprogrammable.

The invention relates to an idea to protect intellectual property within processing modules by a combination of a secure configuration manager and a security image which can be reprogrammed, wherein the security image may be based on several security settings.

Further aspects of the invention are subject to the dependent claims.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter and with respect to the following figures.

Fig. 1 shows a block diagram of a basic architecture of an electronic device according to the first embodiment,

Fig. 2 shows a flow of a security configuration update according to the first embodiment,

Fig. 3 shows a block diagram of the basic architecture of an electronic device according to the second embodiment, and

Fig. 4 shows a block diagram of a security configuration manager according to Fig. 3.

Fig. 1 shows a block diagram of a basic architecture of an electronic device according to the first embodiment. The electronic device comprises an interface unit IU, a memory MEM, a digital signal processor DSP, peripheral units PH and a further memory M, which can be implemented as a non-volatile memory. Furthermore, a first and second trust boundary TBl, TB2 is depicted. The first trust boundary TBl includes part of the interface unit IU as well as part of the non- volatile memory M. The non- volatile memory M may be implemented as a flash and/or ROM memory. The non- volatile memory comprises an application section APPL, a security configuration SC as well as a section for keys K and IDs. The first trust boundary TBl includes the security configuration section SC and the section for the keys and IDs. The first trust boundary TBl serves to update the memory content (or part of the memory content) and the settings in the security configuration section SC from the outside via the interface unit IU. The second trust boundary TB2 relates to an internal trust boundary. This second trust boundary TB2 can be adjusted or set by means of the configuration. The second trust boundary TB2 is used to protect the internal peripheral units PH, the internal memory areas, the content of the internal memory areas as well as algorithms which are performed by the digital signal processor DSP. The implementation of the first trust boundary TBl can be implemented by appropriate software encryption/decryption. Examples of such an encryption/decryption scheme can be implemented by a RSA algorithm or a hashing algorithm such as MD5 or SHA-I.

Fig. 2 shows a flow for a security configuration update according to the first embodiment. With the above-mentioned encryption and decryption algorithms, a security configuration update can be implemented by downloading the respective update. Here, a method for securely upgrading the security configuration is shown in more detail. A security image SI can be provided by a provider. A hash function HF is performed on the security image such that a message digest is achieved. The output of the hash function HF is signed by a private key according to the RSA algorithm in order to obtain a key "b". The security image SI is forwarded to the receiving side, i.e. the device, where a hash function HF is performed on the security image in order to generate a message digest. The output of the signing process SP is forwarded to a signal verification SV, where it is examined based on a public key according to the RSA algorithm. The extract from the signature is forwarded to a compare unit where this extract is compared to the message digest. The output of the compare step serves as indication whether to abort or continue the upgrading. Fig. 3 shows a block diagram of an architecture of an electronic device according to the second embodiment. The electronic device comprises a micro controller MC, at least one digital signal processor DSP, an internal memory SRAM, several bridges BR, a peripheral unit PH and a secure configuration manager SCM. The micro controller MC can be implemented by an ARM7TDMI. The secure configuration manager SCM is connected to the digital signal processor DSP, the internal memory SRAM and the peripheral unit PH. The secure configuration manager SCM is designed to protect internal device peripherals and/or algorithms of the digital signal processor DSP. The secure configuration manager SCM is programmable with a security image and can be downloaded or stored in the flash memory (i.e. the internal (non-volatile) memory SRAM).

The downloading of a new security image can for example be preformed via an interface (not shown), which is controlled by the micro controller MC based on the security configuration update according to Fig. 2.

The secure configuration manager SCM is coupled to a main microprocessor such that it acts as a peripheral unit PH such that it can be accessed and therefore be configured according to the settings of the security image SI. The security image SI can be protected from illegal modification and tampering as described according to Fig. 2. After the secure configuration manager SCM has been programmed, this secure configuration manager will be locked and any further changes will be prohibited. Therefore, each peripheral unit PH coupled to the secure configuration manager can be disabled or enabled according to the settings of the secure configuration manager. The disabling of a peripheral unit PH can be implemented such that the peripheral unit is not functional. This can for example be done by disabling a clock signal. The disabling of the peripheral unit can be performed by denying any read access or by denying any write access if the content to be protected is stored in the memory.

Preferably, the secure configuration manager SCM comprises two different levels to disable any of the peripheral units PH. If the first level disables any of the peripheral units, the second layer is redundant. On the other hand, if the first layer does not disable a peripheral unit PH, the peripheral unit PH can be disabled by the second layer. Optionally, the electronic device comprises several different power domains.

The secure configuration manager SCM is preferably located in a power domain which is always active such that the security settings are always active. This is advantageous as any sequence to wake-up the electronic device will not require a configuration according to the current security settings. If the device is activated, i.e. a cold boot sequence is initiated after a power- on-reset, the security image SI (which may be stored in the flash memory) is examined through the signature verification SV and the hashing function HF as described according to Fig. 2. This is performed in order to determine whether the security image in the flash memory is valid or invalid. For the case that the security image is invalid, the electronic device is able to open a programming interface to import or download a valid security image in the area reserved for the security image. The remaining of the electronic device is restricted in order to provide a secure device during importing the new security image. Therefore, the remaining flash sectors as well as the DSP can be closed. However, if a valid security image is detected, i.e. the security image has not been tampered, the first level of the security configuration manager SCM is programmed according to the security image information. Locking of the first level of the security configuration manager SCM can be based on e.g. a sticky bit configuration. Other implementations are also possible. Thereafter, the security settings of the device have been programmed and an application code can be started.

The second level of the security configuration manager SCM is still available such that additional peripheral units or IP functions can be disabled by the currently running application, i.e. by the customer. It should be noted that any features or IP iunctions which have been disabled at the first level may not be enabled at the second level. This is advantageous as an additional flexibility for disabling peripheral units even at a customer level is provided.

Fig. 4 shows a block diagram of the security configuration manager SCM of Fig. 3. The security configuration manager SCM comprises a bus interface and two levels Ll, L2 for the security setting. Additionally, different peripheral settings are provided. The micro controller MC can access the first and second registers Ll, L2 which are referring to the first and second level of the security configuration manager. The bit positions 0-30 within the particular registers serve to disable an IP function or a peripheral unit PH. The bit number 31 is used to indicate whether the settings in the register have been configured. In particular, if the bit number 31 is written, the settings of the register have been configured. Accordingly, the bits in this particular register become read-only bits. Until the next boot sequence, e.g. power-on-reset, the settings in the register cannot be modified any more. If a peripheral unit PH has already been disabled in the first level, the second level L2 cannot enable it. However, if a peripheral unit is still enabled in the first level, a disabling of this function is still possible in the second level. Furthermore, the bit number 31 can be used to freeze the settings in the register.

Accordingly, the register associated to the first level can be used to disable a functionality of a peripheral unit PH such that a consumer is not allowed to use it or in other words the usage thereof is prohibited. However, the first customer may still change the registers of the second level L2. One example which may be enabled in the first level is the JTAG interface as such an interface will be required for any customer to perform any additional design with the electronic device. However, when the design is finished, the usage of the JTAG interface can be disabled by the registers in the second level. This is advantageous as the end consumer will not be able to make any changes regarding to the application running on the electronic device according to the second embodiment.

The above described principle of the invention to restrict the accessibility of certain functionalities and functions within an electronic device for different kind of users according to a security image which may be stored in a flash memory is advantageous as such a concept enables a flexible configuration of an electronic device. With the above- mentioned security configuration manager, an electronic device or an integrated circuit can be used within different market areas by merely changing the security configuration without the danger of disclosing any of its relevant IP content.

Accordingly, such an electronic device or integrated circuit may support different features for different customers according to the current security image. In addition, the electronic device or integrated circuit may be updated according to a new security image whereby some of the functionality within the electronic device is enabled.

Alternatively or additionally, the security checking scheme can be implemented as an algorithm in a digital signal processor DSP. The above mentioned secure configuration manager and the secure configuration managing scheme can be implemented in a mobile device (e.g. a mobile phone, a PDA, etc), portable media players (e.g. MP3-player), car radios, etc.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims

CLAIMS:

1. Electronic device, comprising at least one processing module (PH) a secure configuration managing unit (SCM) coupled to at least one of the processing modules (PH) for enabling or disabling at least one of the processing modules (PH) according to a reprogrammable security image, wherein the secure configuration manager (SCM) comprises at least a first and second security setting unit (Ll, L2) for storing first and second security settings according to the security image, respectively, wherein the first and second security settings of the security image are reprogrammable.

2. Electronic device according to claim 1, wherein the secure configuration managing unit (SCM) is adapted to disable at least one of the processing modules (PH) by disabling a clock signal, by denying any read access or by denying any write access to a memory (M).

3. Electronic device according to claim 1, wherein the security image is stored in the secure configuration managing unit (SCM).

4. Electronic device according to claim 1, further comprising a non- volatile memory, wherein the security image is stored in the non-volatile memory.

5. Electronic device according to claim 1, further comprising a plurality of power domains, wherein one of the plurality of power domains is always in an ON state, wherein the secure configuration managing unit (SCM) is arranged in the power domains being always in the ON state.

6. Electronic device according to claim 4, further comprising: an interface unit (IU) coupled to the non-volatile memory for reprogramming the security image stored in the non-volatile memory with a new security image, and a processing unit (MC) coupled to the interface unit (IU) for determining whether the new security image is valid wherein the new security image is stored in the nonvolatile memory if the processing unit (MC) has determined that the new security image is valid.

7. Method for enabling/disabling processing modules (PH) within an electronic device, comprising the steps of: enabling or disabling at least one of the processing modules (PH) according to a reprogrammable security image, storing first and second security settings in at least a first and second security setting unit (Ll, L2) according to the security image, respectively wherein the first and second security settings of the security image are reprogrammable.

8. Data processing system comprising at least one electronic device according to any one of the claims 1-6.