WO2006129427A1

WO2006129427A1 - Light sensor and display device

Info

Publication number: WO2006129427A1
Application number: PCT/JP2006/308113
Authority: WO
Inventors: Hiromi Katoh; Yoshihiro Izumi
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2005-05-31
Filing date: 2006-04-18
Publication date: 2006-12-07

Abstract

A light sensor (1) provided with semiconductor regions (2-4, 9, 10) formed on a silicon film (11) and intrinsic semiconductor regions (5-8) is used. The semiconductor regions (2-4, 9, 10) are arranged along the surface of the silicon film (11) in a row at intervals so that the adjacent semiconductor regions have opposite conductivity types. The intrinsic semiconductor regions (5-8) are arranged in contact with the adjacent semiconductor regions between the adjacent semiconductor regions. PIN photodiodes (D1-D4) are composed of the intrinsic semiconductor regions (5-8) and the adjacent semiconductor regions.

Description

Specification

Optical sensor and display device

Technical field

[0001] The present invention relates to an optical sensor and a display device including the same.

Background art

[0002] In the field of display devices typified by liquid crystal display devices, it has been proposed to mount an optical sensor on the display device in order to adjust the brightness of the display screen in accordance with the intensity of ambient light. (For example, see Patent Document 1 and Patent Document 2.) _{0 When a} light sensor is mounted on a transmissive liquid crystal display device, the light intensity of the backlight can be increased in bright environments such as outdoors and in the environment. In a relatively dark environment such as indoors, the light intensity of the backlight can be reduced. For this reason, the visibility of the screen is improved, and the power consumption and life of the liquid crystal display device are reduced.

[0003] For example, an optical sensor can be mounted on a liquid crystal display device by mounting an optical sensor of a discrete component on a liquid crystal display panel. In recent years, an attempt has been made to monolithically form an optical sensor on an active matrix substrate constituting a liquid crystal display panel (see, for example, Patent Document 3). _{0 In the} latter case, the optical sensor is an active sensor. It is formed on the glass substrate that becomes the base of the active matrix substrate at the same time by the process of forming the element (TFT) and peripheral circuits. According to the latter, the manufacturing cost can be reduced and the display device can be downsized by reducing the number of parts compared to the former.

[0004] As a photosensor in the latter case, for example, a PIN photodiode is known (for example, see Non-Patent Document 1). O This PIN photodiode has a so-called lateral structure. Here, the PIN photodiode formed monolithically on the active matrix substrate will be described with reference to FIG. FIG. 9 is a plan view showing an optical sensor constituted by a conventional PIN photodiode.

As shown in FIG. 9, the optical sensor 51 includes a p-type semiconductor region (p layer) 52, an intrinsic semiconductor region (i layer) 53, and an n-type semiconductor region (n layer) formed in a silicon film 55. ) 54. The p layer 52, the i layer 53, and the n layer 54 are sequentially arranged along the plane direction of the silicon film 55. Shi The recon film 55 is formed on the glass substrate 60 which is the base of the active matrix substrate. In FIG. 9, 58 and 59 are electrode patterns. Electrode pattern 58 is connected to p layer 52 via contact plug 56. The electrode pattern 59 is connected to the n layer 54 via a contact plug 57.

[0006] The optical sensor 51 shown in FIG. 9 is formed simultaneously with an active element (not shown) formed on the active matrix substrate and a peripheral circuit forming process. For example, the silicon film 55 is a thin film common to the silicon film constituting the active element (TFT), and is formed at the same time by the formation process of the silicon film constituting the active element.

Examples of the silicon film include an amorphous silicon film, a polysilicon film, and a continuous grain boundary crystal silicon (CGS) film (see, for example, Patent Document 4). Of these, the power that has been mainly used for amorphous silicon films in recent years.To improve the performance of active elements in recent years, polysilicon films with higher electron mobility than amorphous silicon films and continuous grain boundary crystalline silicon have been used. The use of membranes is increasing.

[0008] Further, in order to provide appropriate sensitivity to the optical sensor 51 shown in FIG. 9, it is necessary to output a sufficient generated current. However, if the length L of the i-layer 53 exceeds a certain value, the generated current decreases conversely. For this reason, in the optical sensor shown in FIG. 9, the width W of the i layer 53 is set so that a sufficient generated current is output.

Patent Document 1: Japanese Patent Laid-Open No. 4-174819

Patent Document 2: Japanese Patent Laid-Open No. 5-241512

Patent Document 3: Japanese Patent Laid-Open No. 2002-175026 (Fig. 12)

Patent Document 4: Japanese Patent Laid-Open No. 2001-319878

Non-Patent Document 1: N. Tada and 6 others “A Touch Panel Function Integrated LCD Using LTPS Technology”, Late—News Paper AMD 7—4L, 11th International Display Workshops (2004), 2004, p. 349-350

Disclosure of the invention Problems to be solved by the invention

[0009] If a sufficient generated current can be output from the optical sensor 51 shown in FIG. 9 while the force is applied, the width W of the i layer 53 becomes very large compared to the length L, and the shape of the i layer 53 Becomes an elongated shape. Therefore, the optical sensor 51 shown in FIG. 9 has a problem that the sensitivity to light from a specific direction is lowered.

[0010] In addition, the polysilicon film and the CGS film have a characteristic that, although the electron mobility is larger than that of amorphous silicon, the light absorption coefficient is smaller than that of amorphous silicon. Therefore, when using a polysilicon film or a CGS film, it is necessary to further increase the width W of the i layer 53 than when using an amorphous silicon film, and the i layer 53 has a further elongated shape. For this reason, in the optical sensor 51 formed of a polysilicon film or a CGS film, the sensitivity to light from a specific direction is further reduced as compared with the optical sensor 51 formed of an amorphous silicon film.

An object of the present invention is to provide an optical sensor that can solve the above-described problems and suppress a decrease in sensitivity to light from a specific direction, and a display device including the optical sensor.

Means for solving the problem

In order to achieve the above object, an optical sensor according to the present invention includes three or more semiconductor regions and intrinsic semiconductor regions formed on a substrate or a thin film, and the three or more semiconductor regions are formed on the substrate or the thin film. The intrinsic semiconductor regions are arranged between the adjacent semiconductor regions, with the conductive types of adjacent semiconductor regions being opposite to each other at intervals in a row along the surface. The PIN photodiode is formed together with the adjacent semiconductor region, which is disposed so as to contact the matching semiconductor region.

In order to achieve the above object, a display device according to the present invention includes an active matrix substrate on which a plurality of active elements are formed, and a photosensor that outputs a signal in response to ambient light. The optical sensor includes three or more semiconductor regions and intrinsic semiconductor regions formed in a thin film, and the thin film is formed on a base substrate of the active matrix substrate, and the three or more semiconductor regions are formed. The semiconductor regions are arranged in a row along the surface of the thin film, and are arranged so that the conductivity types of adjacent semiconductor regions are opposite to each other, and the intrinsic semiconductor region is an adjacent semiconductor region Between areas, the adjacent It is disposed so as to be in contact with a semiconductor region, and a PIN photodiode is formed together with the adjacent semiconductor region.

In the present invention, the “intrinsic semiconductor region” may be a region that is electrically neutral compared to the adjacent first conductivity type semiconductor region and second conductivity type semiconductor region. However, the “intrinsic semiconductor region” is preferably a region containing no impurities or a region where the conduction electron density and the hole density are equal. In addition, the display device of the present invention may be an EL display device as well as a liquid crystal display device as long as the display device includes an active matrix substrate.

The invention's effect

As described above, since the p-type semiconductor region and the n-type semiconductor region can be alternately arranged in the optical sensor of the present invention, the intrinsic semiconductor region is formed in, for example, a stripe shape or a lattice shape. It is done. For this reason, according to the optical sensor of the present invention, it is possible to suppress a decrease in sensitivity to light from a specific direction as compared with a conventional optical sensor including a PIN photodiode (see FIG. 9).

FIG. 1 is a perspective view showing a schematic configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the configuration of an active element formed on the active matrix substrate shown in FIG.

FIG. 3 is a diagram showing the configuration of the photosensor according to the embodiment of the present invention. FIG. 3 (a) is a plan view, and FIG. 3 (b) is a section line A in FIG. 3 (a). FIG. 3 is a cross-sectional view taken along a line.

FIG. 4 is a plan view showing an example in which the wiring structure of the photosensor shown in FIG. 3 is different.

FIG. 5 is a circuit diagram of the photosensor shown in FIG. 3.

[FIG. 6] FIG. 6 is a diagram showing an example in which mask displacement occurs in the optical sensor manufacturing process according to the embodiment of the present invention. FIG. 6 (a) is a plan view, and FIG. 6 (b) is FIG. It is a sectional view cut along a cutting line B- in (a).

FIG. 7 is a cross-sectional view showing another example of the optical sensor of the present invention.

FIG. 8 is a plan view showing another example of the optical sensor of the present invention. [FIG. 9] FIG. 9 is a plan view showing an optical sensor constituted by a conventional PIN photodiode.

BEST MODE FOR CARRYING OUT THE INVENTION

The optical sensor according to the present invention includes three or more semiconductor regions and intrinsic semiconductor regions formed on a substrate or a thin film, and the three or more semiconductor regions are arranged in a line along the surface of the substrate or the thin film. Are arranged so that the conductivity types of adjacent semiconductor regions are opposite to each other, and the intrinsic semiconductor region is in contact with the adjacent semiconductor region between adjacent semiconductor regions. The PIN photodiodes are formed together with the adjacent semiconductor regions.

[0018] In the optical sensor according to the present invention, the first wiring connected to all the one-conductivity-type semiconductor regions among the three or more semiconductor regions, and the one of the three or more semiconductor regions described above. It is preferable that the second wiring connected to all the semiconductor regions having the conductivity type opposite to the one conductivity type is further provided. In this case, since the plurality of PIN photodiodes formed by the intrinsic semiconductor region and the adjacent semiconductor region are connected in parallel, the current value of the generated current output by the optical sensor force can be increased.

[0019] In the optical sensor of the present invention, the three or more semiconductor regions and the intrinsic semiconductor region are formed in a silicon film, and the silicon film is an active matrix substrate including a plurality of active elements. An embodiment in which a film is formed on the base substrate is also possible. In this case, the optical sensor is formed monolithically on the active matrix substrate. For this reason, the number of parts of the active matrix substrate can be reduced, and the manufacturing cost of the display device equipped with the photosensor of the present invention can be reduced.

The display device according to the present invention is a display device having an active matrix substrate on which a plurality of active elements are formed, and an optical sensor that outputs a signal in response to ambient light. Comprises three or more semiconductor regions and intrinsic semiconductor regions formed in a thin film, the thin film is formed on a base substrate of the active matrix substrate, and the three or more semiconductor regions are formed on a surface of the thin film. Are arranged so that the conductivity types of adjacent semiconductor regions are opposite to each other, and the intrinsic semiconductor regions are adjacent to each other between adjacent semiconductor regions. In contact with the semiconductor region The PIN photodiode is formed together with the adjacent semiconductor regions.

[0021] (Embodiment)

Hereinafter, an optical sensor and a display device according to an embodiment of the present invention will be described with reference to FIGS. First, the overall structure of the display device in this embodiment will be described with reference to FIG. FIG. 1 is a perspective view showing a schematic configuration of a display device according to an embodiment of the present invention.

As shown in FIG. 1, in the present embodiment, the display device is a liquid crystal display device. The display device includes a liquid crystal display panel in which a liquid crystal layer 102 is sandwiched between an active matrix substrate 101 and a counter substrate 103, and a knock light 110. The knock light 110 illuminates the liquid crystal display panel also with the active matrix substrate 101 side force.

[0023] In the active matrix substrate 101, a region in contact with the liquid crystal layer 102 is a display region. In the display area, although not shown in FIG. 1, a plurality of pixels each having an active element and a pixel electrode are formed in a matrix. The configuration of the active element will be described later with reference to FIG.

In addition, in order to detect the intensity of external light, the area around the display area of the active matrix substrate 101 (hereinafter referred to as “peripheral area”) is provided with the optical sensor 1 in the present embodiment. ing. The optical sensor 1 outputs a current (generated current) having a magnitude corresponding to the intensity of external light to the detection device 111 that is also provided in the peripheral region.

[0025] The detection device 111 has a capacity, and generates a voltage signal by accumulating the generated current output from the optical sensor in the capacity. In the present embodiment, the detection device 111 compares the potential of the voltage signal with a reference potential, and generates a digital signal that specifies the level of the potential of the voltage signal. This digital signal is input to a control device (not shown) of the backlight 110, and the brightness of the backlight 110 is adjusted according to the intensity of external light. When the liquid crystal display device shown in FIG. 1 is mounted on a mopile device such as a mobile phone, for example, reference potentials of about 4 to 5 steps are set. In this case, the digital signal output from the detection device 111 is 2 bits or more.

[0026] In the present embodiment, the optical sensor 1 includes an active sensor as shown in FIG. It is formed monolithically on the base substrate (glass substrate) of the submatrix substrate 101. Further, the detection device 111 is also monolithically formed on the base substrate. In the present invention, “monolithically formed on a glass substrate” means that a device is formed directly on a glass substrate by a physical process and a z or chemical process, and a semiconductor circuit. Does not include being mounted on a glass substrate.

Furthermore, a horizontal drive circuit (source driver) 104 and a vertical drive circuit (gate driver) 105 are also provided in the peripheral region of the active matrix substrate 101. The semiconductor elements constituting the horizontal drive circuit 104 or the vertical drive circuit 105 are also monolithically formed on the base substrate (glass substrate) of the active matrix substrate 101.

Further, an external substrate 107 is connected to the active matrix substrate 101 via an FPC 106. An IC chip 108 and an IC chip 109 are mounted on the external substrate 107. The IC chip 109 includes a reference power supply circuit that generates a power supply voltage used inside the display device. The IC chip 108 includes a control circuit for controlling the horizontal drive circuit 104 and the vertical drive circuit 105. In the first embodiment, an IC chip other than the IC chip 108 and the IC chip 109 can be mounted on the external substrate 107.

Here, the configuration of the active element will be described with reference to FIG. FIG. 2 is a cross-sectional view showing the configuration of active elements formed on the active matrix substrate shown in FIG. As shown in FIG. 2, the active element 21 includes a silicon film 25 formed on the glass substrate 20 and a gate electrode 26 disposed on the upper layer. The glass substrate 20 is a base substrate of the active matrix substrate 101 (see FIG. 1). In Fig. 2, 20 glass substrates! Don't forget hatching.

Further, the active element 21 shown in FIG. 2 is an n-type TFT. In the silicon film 25, n-type semiconductor regions 22 and 24 which are the source or drain of the TFT are formed. The n-type semiconductor regions 22 and 24 are formed by ion implantation of phosphorus (P) arsenic (As) t and other n-type impurities. Reference numeral 23 denotes a channel region serving as a TFT channel.

[0031] The silicon film 25 can be formed of an amorphous silicon film, a polysilicon film, a continuous grain boundary crystal silicon (CGS) film, or the like. However, in this embodiment, as described above, the detection device 111, the horizontal drive circuit 104, and the vertical drive circuit 105 are connected to the active matrix. It is formed monolithically on the task substrate 101. Therefore, from the viewpoint of electron mobility, the silicon film 25 is preferably formed of a polysilicon film or a CGS film. In particular, it is preferable that the silicon film 25 is formed of a CGS film because it has the highest electron mobility.

The formation of the silicon film 25 using the CGS film can be performed as follows, for example. First, an oxide silicon film and an amorphous silicon film are sequentially formed on the glass substrate 20. Next, a nickel thin film serving as a catalyst for promoting crystallization is formed on the surface of the amorphous silicon film. Next, the nickel thin film and the amorphous silicon film are reacted by heating to form a crystalline silicon layer at these interfaces. Thereafter, the unreacted nickel film and the silicon-nickel layer are removed by etching or the like. Next, annealing is performed on the remaining silicon film to advance crystallization, and a CGS film is obtained. Thereafter, by patterning the CGS film by forming a resist pattern by photolithography and performing etching using the resist pattern as a mask, a silicon film 25 shown in FIG. 2 is obtained.

Further, as shown in FIG. 2, a first interlayer insulating film 31 is formed between the gate electrode 26 and the silicon film 25. The portion of the first interlayer insulating film 31 immediately below the gate electrode 26 functions as a gate insulating film. In the example of FIG. 2, the formation of the first interlayer insulating film 31 is performed by forming a silicon nitride film or a silicon oxide film by the CVD method after the silicon film 25 is formed. The gate electrode 26 is formed by forming a conductive film such as a silicon film on the first interlayer insulating film 31 by a CVD method or the like, and then forming a resist pattern by a photolithography method or using the resist pattern as a mask. This is done by performing an etching.

A second interlayer insulating film 32 is formed on the first interlayer insulating film 31 so as to cover the gate electrode 26. The formation of the second interlayer insulating film 32 is performed by forming a silicon nitride film or a silicon oxide film by the CVD method after the formation of the gate electrode 26, as in the case of the first interlayer insulating film 31. Yes. Further, contact plugs 27 and 28 that penetrate the first interlayer insulating film 31 and the second interlayer insulating film 32 and are connected to the semiconductor region 22 or 24 are also formed. On the second interlayer insulating film 32, electrode patterns 29 and 30 connected to the contact plugs 27 or 28 are also formed!

Next, a specific configuration of the optical sensor 1 shown in FIG. 1 will be described with reference to FIGS. . FIG. 3 is a diagram showing the configuration of the optical sensor according to the embodiment of the present invention. FIG. 3 (a) is a plan view, and FIG. 3 (b) is a cut line Α-ΑΊ along FIG. 3 (a). It is sectional drawing cut | disconnected by. FIG. 4 is a plan view showing an example in which the wiring structure of the photosensor shown in FIG. 3 is different. FIG. 5 is a circuit diagram of the photosensor shown in FIG. In FIG. 3, the hatching of the glass substrate 20 is omitted.

[0036] As shown in FIGS. 3A and 3B, the optical sensor 1 includes three or more semiconductor regions and an intrinsic semiconductor region. In the present embodiment, the optical sensor 1 includes five semiconductor regions, that is, p-type semiconductor regions (p layer) 2 to 4 and n-type semiconductor regions (n layer) 9 and 10. . The optical sensor 1 includes four intrinsic semiconductor regions (i layers) 5 to 8. In the present embodiment, the ρ layers 2 to 4, the i layers 5 to 8, and the n layers 9 and 10 are formed on the silicon film 11. As shown in FIG. 3 (a), p layers 2-4, i layers 5-8, and n layers 9 and 10 are formed in a strip shape extending in the vertical direction of the drawing! Speak.

In addition, the p layers 2 to 4 and the n layers 9 and 10 formed in the silicon film 11 are arranged in rows along the surface of the silicon film 11, and the conductivity type of the adjacent semiconductor regions is the same. They are arranged so that they are opposite to each other. In other words, the p layer and the n layer are alternately arranged in a line along the horizontal direction of the drawing (a direction substantially perpendicular to the direction in which each layer extends). Further, the i layers 5 to 8 are disposed between the adjacent p layer and n layer so as to be in contact with them. In the present embodiment, the length Ll of the i layer 5, the length L2 of the i layer 6, the length L3 of the i layer 7, and the length L4 of the i layer 8 are all set to be the same. .

[0038] For this reason, one PIN photodiode D1 is formed by the p layer 2, the i layer 5, and the n layer 9. Similarly, a PIN photodiode D2 is formed by ρ layer 3, i layer 6, and n layer 9, and a PIN photodiode D3 is formed by p layer 3, i layer 7, and n layer 10, and p layer 4, i layer 8 The n layer 10 forms a PIN photodiode D4. In the present embodiment, the optical sensor 1 includes four PIN photodiodes. The PIN photodiodes D1 to D4 share the p layer or the n layer with the adjacent PIN photodiodes.

In the present embodiment, the silicon film 11 is formed on the glass substrate 20 that becomes the base substrate of the active matrix substrate 101 (see FIG. 1). The silicon film 11 is formed simultaneously with the silicon film 25 by the formation process of the silicon film 25 (see FIG. 2) constituting the active element 21. Is formed. The p layers 2 to 4 and the n layers 9 and 10 form the active element 21 (see FIG. 2) and the p-type or n-type semiconductor region of the horizontal drive circuit 104 and the vertical drive circuit 105 (see FIG. 1). It is formed using a process (ion implantation process).

For example, the n layers 9 and 10 can be formed by the process (ion implantation process) of forming the semiconductor regions 22 and 24 of the active element 21 shown in FIG. In the case where the semiconductor regions 22 and 24 of the active element 21 are performed by a plurality of ion implantations under different implantation conditions, the optimum ion implantation for forming the n layers 9 and 10 is selected from these.

[0041] The i layers 5 to 8 may be formed so as to be electrically more neutral than the adjacent p layer and n layer. In the present embodiment, the i layers 5 to 8 are formed so that the impurity concentration is lower than the impurity concentration of the adjacent P layer and n layer. For example, the i layers 5 to 8 can be formed by providing a mask in the formation region of the i layers 5 to 8 at the time of ion implantation, or when the formed silicon film is not electrically neutral. 8 can be formed by ion implantation in the formation region. Further, when ion implantation is performed, an optimum condition can be selected from the ion implantation steps performed at the time of forming the active element 21, the horizontal driving circuit 104, and the vertical driving circuit 105, and can be used. However, the rings 5 to 8 can be formed by a method of electrically neutralizing the region to be the i layers 5 to 8, and the forming method of the i layers 5 to 8 is limited to the above method. is not.

Further, as shown in FIG. 3B, a first interlayer insulating film 12 and a second interlayer insulating film 13 are sequentially stacked on the upper surface of the optical sensor 1. The first interlayer insulating film 12 and the second interlayer insulating film 13 are formed by using the step of forming the first interlayer insulating film 31 or the second interlayer insulating film 32 of the active element 21 shown in FIG. Done. In FIG. 3A, illustration of the first interlayer insulating film 12 and the second interlayer insulating film 13 is omitted.

Furthermore, the first interlayer insulating film 12 and the second interlayer insulating film 13 are formed with contact plugs 14a to 14c and contact plugs 15a and 15b penetrating therethrough. The contact plugs 14a to 14c, 15a and 15b are formed by using the process of forming the contact plugs 27 and 28 of the active element 21 shown in FIG. Contact plugs 14a-14c are connected to corresponding p layers 2-4. The contact plugs 15a and 15b are connected to the corresponding n layers 9 and 10! In addition, wirings 16 and 17 are formed on the second interlayer insulating film 13. The wirings 16 and 17 are formed using the process of forming the electrode patterns 29 and 30 of the active element shown in FIG. The wiring 16 includes a main wiring 16d and branch wirings 16a to 16c branched therefrom. The branch wirings 16a to 16d are connected to contact plugs 14a to 14c connected to the p layer. For this reason, the main wiring 16d of the wiring 16 is electrically connected to all the P-type semiconductor regions (P layers 2 to 4). Therefore, all the currents generated from the PIN photodiodes D1 to D4 are output to the detection device 111 (see FIG. 1) via the wiring 16.

Similarly, the wiring 17 also includes a main wiring 17c and branch wirings 17a and 17b branched therefrom. Each of the branch wirings 17a and 17b is connected to contact plugs 15a and 15b connected to the n layer. Therefore, the main wiring 17c of the wiring 17 is electrically connected to all the n-type semiconductor regions (n layers 9 and 10). Wiring 17 is connected to the power supply potential V.

DD

The reverse bias voltage is applied to the n layers 9 and 10.

Further, as shown in FIG. 4, the optical sensor 1 is configured such that the branch wirings 16a to 16c and the branch wirings 17a and 17b are extended in the width direction as compared with the example of FIG. You can also. In this embodiment, three contact plugs 14a to 14c, 15a and 15b are formed. Therefore, each of the branch wirings 16a to 16c is connected to the corresponding p layers 2 to 4 at three locations, and similarly, each of the branch wirings 17a and 17b is connected to the corresponding n layer 9 or 10 at three locations.

Therefore, with the configuration shown in FIG. 4, in n layers 9 and 10, power supply potential V is applied uniformly to the entire layer, and in p layers 2 to 4, current I is output from the entire layer. The Also,

DD PH

With the configuration shown in FIG. 4, the contact resistance between the optical sensor 1 and the contact plugs 14a to 14c, 15a and 15b can be reduced.

Further, as shown in FIG. 5, the PIN photodiodes D1 to D4 included in the optical sensor 1 are connected in parallel by the wirings 16 and 17 shown in FIGS. In this case, the current value I of the generated current I output from the entire photosensor 1 is generated by each of the PIN photodiodes D1 to D4.

PH

This corresponds to the sum of current values. Note that the generated current I output from the optical sensor 1 includes the light

PH

In addition to the photocurrent caused only by the incident light, dark current is also included. So actually The current value of the generated current is the sum of the current value of the photocurrent and the current value of the dark current.

[0049] As described above, in the optical sensor 1 according to the present embodiment, a plurality of i layers 5 to 8 are formed, and these i layers 5 to 8 are sandwiched between the p layer and the n layer. In a state, they are arranged in a line along a direction perpendicular to the width direction. In other words, in this embodiment, the i layers 5 to 8 are formed in a striped pattern, so that compared to a conventional optical sensor (see FIG. 9) having a PIN photodiode, A decrease in sensitivity can be suppressed.

In the background art, in the optical sensor 51 shown in FIG. 9, not only the shape of the i layer 53 but also the overall shape is an elongated shape. For this reason, the optical sensor 51 shown in FIG. 9 is likely to become an obstacle to other wiring and semiconductor elements laid out on the active matrix substrate, and it is difficult to lay out the optical sensor 51 on the active matrix substrate. On the other hand, according to the optical sensor 1 in the present embodiment, a sufficient generated current can be output without making the i layer elongated as in the prior art. For this reason, if the optical sensor 1 is used, the outer shape of the entire optical sensor 1 can be made into a square or a shape close thereto, and the layout can be made easier as compared with the conventional one.

[0051] Further, in the case of the conventional optical sensor shown in FIG. 9, when a leak current is generated from the i layer, the entire display panel becomes a defective product. The situation can be avoided. In other words, according to the optical sensor 1, even if leakage current is generated from several i layers, a normal PIN photodiode is constituted by the remaining i layers, so that the entire display panel is prevented from being defective. it can.

[0052] Further, in the conventional optical sensor shown in FIG. 9, if the mask shift occurs in the formation process of the p layer or the n layer, and the length L of the i layer deviates from an appropriate range, it is sufficient. However, according to the optical sensor in the present embodiment, this problem can also be avoided. This point will be described with reference to FIG. FIG. 6 is a diagram showing an example in which mask displacement occurs in the optical sensor manufacturing process according to the embodiment of the present invention. FIG. 6 (a) is a plan view, and FIG. 6 (b) is FIG. a) Middle cutting line Β—A cross-sectional view taken along the edge.

As shown in FIG. 6, in this example, mask displacement occurs in the process of forming the η layers 9 and 10, and the positions of the η layers 9 and 10 are displaced. Therefore, the length of the i layer 5 is L and the length L3 ′ of the i layer 7 is shorter than that in the example of FIG. 3 (Ll> Lr, L3> L3, i layer 5 and i layer 7 The current value of the generated generated current is reduced.

[0054] The length of the i-layer 6 and the length of the i-layer 8 are increased in comparison with the example of FIG.

(L2 ′> L2, L4 ′> L4), the current value of the generated current output from the i layer 6 and the i layer 8 increases. Further, the length of the entire i layer (Lr + L2 ′ + L3 ′ + L4 ′) is the same as the case of the example in FIG. 3 (L1 + L2 + L3 + L4).

[0055] For this reason, the current value of the generated current I of the entire optical sensor 1 output from the wiring 17 is not changed.

PH

The light sensor 1 can output a sufficient generated current even when mask displacement occurs. The “length of the i layer” refers to the distance from the boundary (interface) between the i layer and the adjacent p layer to the boundary (interface) between the i layer and the adjacent n layer.

In the present embodiment, the length of each i layer (Ll to L4 (Lr to L4)) is particularly limited as long as it is set so as to output a sufficient generated current. However, for example, if the silicon film 11 is formed of a CGS film, the length of each i layer is preferably set to 2.5 / zm or more and 10 / zm or less. If the length of each i layer exceeds 10 m, the generated current decreases but the dark current increases, so the sensitivity and dynamic range of the optical sensor 1 decrease. If the length is less than 2.5 m, the rate of change in dark current when the reverse bias voltage fluctuates increases, and this is a force that reduces the detection accuracy of the detection device 111 (see FIG. 1).

[0057] In addition, the length of each i layer when a CGS film is used is preferably set to 3 m or more and 7 m or less. In this case, the rate of change of the dark current when the reverse bias voltage fluctuates can be reduced, which can improve the detection accuracy of the detection device 111 (see FIG. 1). That's it.

Note that in practice, it is necessary to consider the mask displacement shown in FIG. Therefore, the length of the i layer when using the CGS film is most preferably set based on the design rule of the active matrix substrate. For example, if the design rule of the active matrix substrate is 3 m, the length of the i layer when using the CGS film should be set to about 5 / ζ πι to 6 / ζ πι.

[0059] In the optical sensor 1 according to the present embodiment, the width W of the i layers 5 to 8 is not particularly limited. Depending on the lengths L1 to L4 of the i layers 5 to 8 and the use environment of the display device Appropriate What is necessary is just to set so that a raw current can be output. When a CGS film is used as the silicon film 11, the electron mobility of the silicon film 11 is 200 [cm ² Zvs] or more, in particular, 200

[cmVvs] ~ 400 [cmVvs] or better!ヽ.

[0060] The lengths (length in the arrangement direction) of each of the p layers 2 to 4 and the n layers 9 and 10 are preferably as short as possible from the viewpoint of downsizing the optical sensor 1. However, the length of each of the p layers 2-4 and n layers 9 and 10 must be set in consideration of the design rules of the active matrix substrate so that they can be connected to the contact plugs 14a to 14c, 15a and 15b. There is. For example, if the design rule of the active matrix substrate is 3 μm, the length of each of the p layers 2 to 4 and the n layers 9 and 10 should be about 15 μm.

In the present invention, the optical sensor is not limited to the example shown in FIG. FIG. 7 is a cross-sectional view showing another example of the optical sensor of the present invention. Unlike the optical sensor 1 shown in FIG. 3, the optical sensor shown in FIG. 7 has an LDD structure. In the example of FIG. 7, the p layer and the n layer include a high concentration layer and a low concentration layer.

Specifically, the p layer 2 includes high concentration p layers 2a and 2c and a low concentration p layer 2b. Similarly, the p layer 3 includes high concentration p layers 3a and 3c and a low concentration layer 3b, and the p layer 4 includes high concentration p layers 4a and 4c and a low concentration layer 4b. The n layer 9 includes high concentration n layers 9a and 9c and a low concentration n layer 9b, and the n layer 10 includes high concentration n layers 10a and 10c and a low concentration n layer 10b. In FIG. 7, the part denoted by the reference numeral shown in FIG. 3 is the same part as the part denoted by the same reference numeral in FIG.

[0063] In the example of FIG. 7, the p layers 2 to 4 are formed into the high concentration p layers 2a to 4a and 2c to 4c after ion-implanting p-type impurities at a low concentration into the formation regions of the respective p layers It is formed by ion-implanting p-type impurities at a high concentration in the region. The formation of the n layers 9 and 10 is the same.

As described above, the optical sensor shown in FIG. 7 has an LDD structure. For this reason, the energy level changes at the interface between the i layer 5-8 and the p layer and at the interface between the i layer 5-8 and the n layer can be made smoother. A current can be generated.

In addition, as shown in FIG. 8, the optical sensor of the present invention may have an aspect in which the arrangement and shape of the p layer, i layer, and n layer are different from the example shown in FIG. FIG. 8 is a plan view showing another example of the optical sensor of the present invention. In the example of FIG. 8, illustration of wiring is omitted. [0066] As shown in FIG. 8, in this example, the p layers 42 to 44 and the n layers 46 to 48 are arranged in rows and in two directions perpendicular to each other (X direction and Y direction). Conductive semiconductor regions are arranged next to each other. For this reason, the i layer 45 is formed along two directions (X direction and Y direction) perpendicular to each other, that is, in a lattice shape. Therefore, according to the example of FIG. 8, the i layer 45 is more than the example shown in FIG. Furthermore, a decrease in sensitivity to light from a specific direction can be suppressed.

In the example of FIG. 8, seven PIN photodiodes sharing a semiconductor region are formed, and the number of PIN photodiodes per area can be increased. Therefore, the current value of the generated current output from the optical sensor force can be improved. Also in the optical sensor 41 shown in FIG. 8, the ρ layers 42 to 44, the i layer 45, and the n layers 46 to 48 are formed on the silicon film 49, as in the f row of FIG. .

1 to 8 illustrate an example in which the semiconductor region and the intrinsic semiconductor region constituting the photosensor of the present invention are formed in a silicon film on a substrate. However, the present invention is not limited to this example, and the semiconductor region and the intrinsic semiconductor region may be formed in a film other than the silicon film. In the present invention, the semiconductor region and the intrinsic semiconductor region may be formed on various substrates such as a semiconductor substrate. For example, the optical sensor of the present invention may have a mode in which the semiconductor region and the intrinsic semiconductor region are formed on a silicon substrate constituting the IC chip.

Industrial applicability

[0069] The optical sensor of the present invention can be mounted on a display device such as a liquid crystal display device or an EL display device. Therefore, not only the photodiode of the present invention but also a display device equipped with the photodiode has industrial applicability.

Claims

The scope of the claims

[1] Three or more semiconductor regions formed on a substrate or a thin film, and an intrinsic semiconductor region, wherein the three or more semiconductor regions are spaced in a row along the surface of the substrate or the thin film, And the adjacent semiconductor regions are arranged such that the conductivity types are opposite to each other,

The intrinsic semiconductor region is disposed between adjacent semiconductor regions so as to be in contact with the adjacent semiconductor region, and forms a PIN photodiode together with the adjacent semiconductor region.

[2] a first wiring connected to all semiconductor regions of one conductivity type among the three or more semiconductor regions;

2. The optical sensor according to claim 1, further comprising a second wiring connected to all semiconductor regions having a conductivity type opposite to the one conductivity type among the three or more semiconductor regions.

[3] The three or more semiconductor regions and the intrinsic semiconductor region are formed in a silicon film, and the silicon film is formed on a base substrate of an active matrix substrate having a plurality of active elements! The optical sensor according to claim 1.

[4] A display device having an active matrix substrate on which a plurality of active elements are formed, and an optical sensor that outputs a signal in response to ambient light,

The optical sensor includes three or more semiconductor regions formed in a thin film, and an intrinsic semiconductor region,

The thin film is formed on a base substrate of the active matrix substrate, and the three or more semiconductor regions are spaced in rows along the surface of the thin film, and the conductivity type of adjacent semiconductor regions is The intrinsic semiconductor regions are disposed so as to be in contact with the adjacent semiconductor regions between adjacent semiconductor regions, and form a PIN photodiode together with the adjacent semiconductor regions. A display device characterized by that.