WO2006127856A3 - Operand width indication for micro-sequence processing - Google Patents

Operand width indication for micro-sequence processing Download PDF

Info

Publication number
WO2006127856A3
WO2006127856A3 PCT/US2006/020162 US2006020162W WO2006127856A3 WO 2006127856 A3 WO2006127856 A3 WO 2006127856A3 US 2006020162 W US2006020162 W US 2006020162W WO 2006127856 A3 WO2006127856 A3 WO 2006127856A3
Authority
WO
WIPO (PCT)
Prior art keywords
micro
opcode
operand
sequence
sequence processing
Prior art date
Application number
PCT/US2006/020162
Other languages
French (fr)
Other versions
WO2006127856A2 (en
Inventor
Gilbert Cabillic
Jean-Phillipe Lesot
Gerald Chauvel
Original Assignee
Texas Instruments Inc
Gilbert Cabillic
Jean-Phillipe Lesot
Gerald Chauvel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/135,796 external-priority patent/US20060026392A1/en
Application filed by Texas Instruments Inc, Gilbert Cabillic, Jean-Phillipe Lesot, Gerald Chauvel filed Critical Texas Instruments Inc
Priority to EP06771120A priority Critical patent/EP1891517A4/en
Publication of WO2006127856A2 publication Critical patent/WO2006127856A2/en
Publication of WO2006127856A3 publication Critical patent/WO2006127856A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30174Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30185Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30192Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing

Abstract

Methods and apparatus for data processing provide operand width indication for micro- sequence execution. Described embodiments include methods and apparatus that fetch a first opcode, assert a flag if the first opcode modifies an operand width of a subsequent opcode, fetch a second opcode, trigger a micro-sequence based on the opcode, read the flag by instructions of the micro-sequence (504), and fetch an operand of the second opcode by the micro-sequence (the bit width of the operand based on a state of the flag) (508, 510).
PCT/US2006/020162 2005-05-24 2006-05-24 Operand width indication for micro-sequence processing WO2006127856A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06771120A EP1891517A4 (en) 2005-05-24 2006-05-24 Operand width indication for micro-sequence processing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/135,796 US20060026392A1 (en) 2004-07-27 2005-05-24 Method and system of informing a micro-sequence of operand width
US11/135,796 2005-05-24

Publications (2)

Publication Number Publication Date
WO2006127856A2 WO2006127856A2 (en) 2006-11-30
WO2006127856A3 true WO2006127856A3 (en) 2007-02-22

Family

ID=37452815

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/020162 WO2006127856A2 (en) 2005-05-24 2006-05-24 Operand width indication for micro-sequence processing

Country Status (2)

Country Link
EP (1) EP1891517A4 (en)
WO (1) WO2006127856A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10698859B2 (en) 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
US10452399B2 (en) 2015-09-19 2019-10-22 Microsoft Technology Licensing, Llc Broadcast channel architectures for block-based processors
US10963379B2 (en) 2018-01-30 2021-03-30 Microsoft Technology Licensing, Llc Coupling wide memory interface to wide write back paths

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258419A (en) * 1978-12-29 1981-03-24 Bell Telephone Laboratories, Incorporated Data processing apparatus providing variable operand width operation
US4825355A (en) * 1985-10-25 1989-04-25 Hitachi, Ltd. Instruction format for program control type data processing systems
US5155807A (en) * 1986-02-24 1992-10-13 International Business Machines Corporation Multi-processor communications channel utilizing random access/sequential access memories
US5898850A (en) * 1997-03-31 1999-04-27 International Business Machines Corporation Method and system for executing a non-native mode-sensitive instruction within a computer system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0159699A3 (en) * 1984-04-23 1988-09-28 Nec Corporation A data processor executing microprograms according to a plurality of system architectures
US4747046A (en) 1985-06-28 1988-05-24 Hewlett-Packard Company Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
US5815695A (en) 1993-10-28 1998-09-29 Apple Computer, Inc. Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor
US6775763B2 (en) * 2001-03-09 2004-08-10 Koninklijke Philips Electronics N.V. Bytecode instruction processor with switch instruction handling logic
EP1387253B1 (en) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Dynamic translation and execution of instructions within a processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258419A (en) * 1978-12-29 1981-03-24 Bell Telephone Laboratories, Incorporated Data processing apparatus providing variable operand width operation
US4825355A (en) * 1985-10-25 1989-04-25 Hitachi, Ltd. Instruction format for program control type data processing systems
US5155807A (en) * 1986-02-24 1992-10-13 International Business Machines Corporation Multi-processor communications channel utilizing random access/sequential access memories
US5898850A (en) * 1997-03-31 1999-04-27 International Business Machines Corporation Method and system for executing a non-native mode-sensitive instruction within a computer system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1891517A4 *

Also Published As

Publication number Publication date
EP1891517A2 (en) 2008-02-27
WO2006127856A2 (en) 2006-11-30
EP1891517A4 (en) 2008-08-13

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