WO2006123281A1 - Test structure for combined electrical testing and voltage-contrast inspection - Google Patents

Test structure for combined electrical testing and voltage-contrast inspection Download PDF

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Publication number
WO2006123281A1
WO2006123281A1 PCT/IB2006/051495 IB2006051495W WO2006123281A1 WO 2006123281 A1 WO2006123281 A1 WO 2006123281A1 IB 2006051495 W IB2006051495 W IB 2006051495W WO 2006123281 A1 WO2006123281 A1 WO 2006123281A1
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WO
WIPO (PCT)
Prior art keywords
provided
conductive
structure
insulating layer
lines
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Application number
PCT/IB2006/051495
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French (fr)
Inventor
Dirk Kenneth De Vries
Original Assignee
Koninklijke Philips Electronics N.V.
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Publication date
Priority to EP05300387.7 priority Critical
Priority to EP05300387 priority
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006123281A1 publication Critical patent/WO2006123281A1/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets

Abstract

A test structure (32) for detecting the presence of defects in conductive features formed on integrated circuit topography, which is configured for both voltage contrast inspectability and electrical measurability. A comb- like structure comprising pairs of adjacent conductive lines (22) is provided on a first side of an insulating (dielectric) layer provided on a substrate, each pair of lines (22) being selectively connectable at one end to ground (GND). Floating conductive lines (14) are provided in between the lines (22). Each pair of conductive lines (22) is connected together at the other end thereof by a conductive connecting piece (30), by means of respective vias (28) provided through the insulating layer, to provide a serpentine structure to support electrical measurement of opens. The ends of the floating lines (14) are connected to a conductive spine (18) on the other side of the insulating layer, by means of respective vias (16) provided through the insulating layer to provide a conductive comb- like structure to support electrical measurement of shorts.

Description

TEST STRUCTURE FOR COMBINED ELECTRICAL TESTING AND VOLTAGE- CONTRAST INSPECTION

FIELD OF THE INVENTION

The invention relates generally to a test structure for testing the accuracy at which conductive structures are formed in a semiconductor fabrication process and, more particularly, to such a test structure for combined electrical testing and voltage-contrast inspection.

BACKGROUND OF THE INVENTION High yields are essential to the profitable manufacture of integrated circuits and, accordingly, yield prediction, used to predict the yield of a new semiconductor manufacturing process, is a very valuable tool in assuring that to process will be economically successful. Such yield prediction involves accurate quantification of the yield impact of different yield less mechanisms. A wafer fabrication process typically forms multiple integrated circuits upon each of several silicon wafers processed simultaneously. In general, the yield associated with a product wafer manufactured using a particular wafer fabrication process depends on the number of steps in the wafer fabrication process, the number of defects introduced during each processing step, and the vulnerability of the features formed during a given processing step to the defects introduced during the processing step.

A defect is simply a flaw caused by an imperfect manufacturing process. There are two basic types of defects which may occur when conductive layers are formed on an integrated circuit topography. Extra material defects (EMDs) may occur when the conductive structures include material extending beyond predefined boundaries. Such material may extend to another conductive structure causing a "short" to be formed between the two conductive structures. Missing material defects (MMDs) may occur when a conductive structure is formed which is missing some of its conductive material. Such a defect may cause the formation of an "open" conductive structure in which the continuity of a conductive structure is broken. EMDs and MMDs may be detected using electrical test structures, which structures are commonly used to determine the occurrence (frequency and/or defect size distribution) of electrical opens and shorts, especially in between metal lines, and in and between contact or via chains. Typically, these test structures include a number of electrically testable conductive lines. Electrical probing of these conductive lines may be used to determine the presence of shorts between two or more conductive lines or the presence of opens in a conductive line. Referring to Figure 1 of the drawings, there is illustrated schematically a plan view of the typical layout of a known electrical test structure for electrically measuring opens and shorts. The layout comprises a serpentine structure 100 which may be used to test for MMDs in a conductive structure, and first and second conductive combs 102, 104 formed in close proximity to each other for use in testing for EMDs in a conductive structure. Opens in the "serpentine" or "snake" 100 can be detected by a resistance measurement between terminals Serp A and Serp_B. Shorts between the serpentine 100 and either of the combs 102, 104 can be detected by a resistance measurement between terminals Serp A and Serp_B and the terminals Comb l and Comb_2 which are connected to the combs 102, 104 respectively. It will be appreciated by a person skilled in the art that many other layouts are possible, and used in practice. Dedicated structures for opens can omit one or both of the combs 102, 104. Dedicated structures for shorts can omit the snake 100. Alternatively, for example, parallel "nested" snakes can be used for open and short measurements.

More recently, in-line e-beam defect detection equipment has become available. In this case, defect detection depends strongly on voltage contrast between features and, since prior art electrical test structures do not give an optimal response in voltage contrast inspection techniques, dedicated layouts have been proposed in, for example, US Patent Nos. 6,509,197 and 6,576,923. In these layouts, referring to Figure 2 of the drawings, typically a grounded comb 106 is used to detect opens, wherein an open in any of the fingers of the comb 106 results in the end of that finger no longer being grounded, but instead becoming electrically floating, a difference which can be effectively detected by voltage contrast inspection techniques. Floating lines 108 are provided between the grounded fingers of the comb 106 for detection of shorts, wherein the floating lines 108 will become grounded if there is a short between the originally floating line and any one of the grounded fingers. Again, this voltage contrast is relatively easily detected by e-beam inspection. It will be apparent from a comparison of the test structures of Figures 1 and 2 that the voltage contrast test structure of Figure 2 is incompatible with the electrical measurements for opens and shorts described with reference to Figure 1. The elements sensitive to opens and shorts are not - and in the layout illustrated in Figure 2 of the drawings, cannot be - attached to terminals allowing electrical access for measurements in respect of opens and shorts.

More often than not, in process technology development, a choice is made between implementing either voltage contrast structures or electrical test structures, each choice making it impossible to implement measurement of the "complementary" attribute. Sometimes, both test structure layouts are used in parallel, but this is an expensive and inefficient use of silicon area.

US Patent No. 6,297,644 describes a test structure which may be used in both voltage contrast inspection and electrical testing. The proposed test structure comprises a floating serpentine structure routed around the fingers of a grounded comb, wherein a transistor is positioned between the comb and ground to enable the comb to be switched from a grounded to a floating state, which allows the same test structure to be used for a variety of testing techniques. However, the proposed structure does not optimize either electrical testability or voltage-contrast inspectability and, as such, may affect the efficiency of root cause analysis of yield loss.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an improved test structure for combined electrical testing and voltage-contrast inspection which enhances the efficiency of root cause analysis of yield loss, thereby assisting in accelerating the yield learning curve which is critical to new semiconductor manufacturing technologies, without requiring any special process steps.

In accordance with the present invention, there is provided a test structure for detecting the presence of defects in conductive features formed on an integrated circuit topography, said test structure comprising a substrate on which is provided an insulating layer, a first side of which insulating layer is provided a plurality of conductive lines and on the opposite side of which insulating layer is provided at least one connecting line, at least two of said conductive lines being electrically connected together by said at least one connecting line by means of respective vias provided through said insulating layer from said first side to the opposite side thereof.

The present invention also extend to a semiconductor device including such a test structure.

The test structure of the present invention can be provided in various configurations to combine voltage-contrast inspectability with electrical testability, wherein use of the resultant test structure(s) enhances the efficiency of root cause analysis of yield loss, and thus helps accelerate the yield leaning curve so critical to new semiconductor manufacturing technologies.

In one exemplary embodiment, a grounded conductive comb- like structure is provided on the first side of the insulating, preferably dielectric, layer with floating conductive lines being provided between the lines of said comb- like structure, the resultant conductive structure on the first side of the insulating layer supporting voltage-contrast inspectability. In order to support electrical measurement of shorts, one end of each of the floating lines is connected, by means of respective vias provided through the insulating layer, to a conductive spine provided on the opposite side of the insulating layer. The electrical resistance of the resultant comb- like structure can thus be measured to reveal the presence of electrical shorts as well as their resistance.

In addition, or alternatively, in order to support electrical measurement of opens, a first end of each of the conductive lines of the comb- like structure may be selectively connected to ground by means of respective active switching devices (e.g. field effect transistors), and the opposite ends of adjacent pairs of said conductive lines may be connected, by means of vias provided through the insulating layer, to respective conductive connecting pieces, such that when the first ends of the lines are disconnected from ground, i.e. electrically floating, the resultant structure (comprising the lines on the first side of the insulating layer and the connecting pieces on the opposite side of the insulating layer) is a "serpentine" or "snake" structure which can be used to perform electrical continuity measurement by measuring the resistance between the end terminals of the serpentine structure.

In a preferred embodiment, the above-mentioned embodiments including the conductive spine and the connecting pieces may be combined in a single test structure that supports voltage contrast inspectability and electrical measurement of both shorts and opens.

These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:

Figure 1 is a schematic plan view of a typical test structure for electrical testing according to the prior art; Figure 2 is a schematic plan view of a typical test structure for voltage-contrast inspection according to the prior art;

Figure 3 is a schematic plan view of a test structure according to a first exemplary embodiment of the present invention, optimized for voltage-contrast inspection and electrical measurement of shorts;

Figure 4 is a schematic plan view of a test structure according to a second exemplary embodiment of the present invention, optimized for voltage-contrast inspection and electrical measurement of opens; and

Figure 5 is a schematic plan view of a test structure according to a third exemplary embodiment of the present invention, optimized for voltage-contrast inspection and electrical measurement of opens and shorts.

DETAILED DESCRIPTION OF THE INVENTION

In general, an integrated circuit typically comprises a semiconductor wafer (usually of silicon) on which is formed active and passive devices (such as transistors, resistors, capacitors, etc). After deposition of an insulating and planarizing layer on top of the active devices, contact holes to the devices are after which conducting metal lines are defined. In subsequent steps, new isolating layers are deposited, via holes patterned and upper metal lines defined.

Referring to Figure 3 of the drawings, a test structure 10 according to a first exemplary embodiment of the present invention, wherein the voltage-contrast test structure of Figure 2 has been modified to make it compatible with electrical short measurements, is illustrated schematically. In the first instance, the configuration of Figure 2 is realized on one side of an Insulating layer formed, or otherwise provided, on a semiconductor substrate or wafer (not shown) by forming a grounded, conductive (i.e. metallic) comb- like structure 12, with floating metallic lines 14 therebetween, and this configuration may be inspected in voltage contrast, as described above. In the subsequent process steps, the floating lines 14 are connected, by means of respective vias 16 formed through the insulating - preferably dielectric - layer, to a metal spine 18 formed at the other side of the insulating layer. Thus, the electrical resistance of the comb (which consists of the lines 14 and the spine 18), measured between the terminal COMB and ground GND electrically reveals the presence of electrical shorts as well as their resistance. The modification of the structure of Figure 2 to achieve the above-described test structure according to a first exemplary embodiment of the present invention requires no special process steps and uses no active devices, and is therefore compatible with a so-called "back end short loop" flow, which is a simplified integrated circuit manufacturing process flow known to a person skilled in the art, in which a large number of steps, in particular those relating to the active devices, have been eliminated.

Referring to Figure 4 of the drawings, a test structure 20 according to a second exemplary embodiment of the present invention, wherein the voltage-contrast test structure of Figure 2 has been modified fairly substantially to make it compatible with electrical open measurements, is illustrated schematically. In this case, the original comb structure, formed on a first side of an insulating dielectric layer provided on a semiconductor substrate (not shown) has been split up into a number of parallel "U" shaped structures 22, and the ground connection 24 has been separated from the U-shaped structures 22. The floating conductive lines 14 are still provided between each elongate arm of the U-shaped structures 22. The connection between the U-shaped structures 22 and ground 24 is now realized through a channel of active devices, i.e. field effect transistors 26 which, while the gates are not connected, are sufficiently conductive to permit the electrical charge deposited on the U- shaped structures 22 in an e-beam inspection to escape to ground. Thus, the voltage contrast features of the original comb- like structure are retained.

In the subsequent process steps, the free ends of the U-shaped structures are connected, by means of vias 28 formed in the semiconductor substrate, to metal links 30 provided at the opposite side of the insulating layer provided on the semiconductor substrate. As a result, a serpentine or snake structure is created which allows conventional electrical continuity measurement after the connection between the U-shaped structures 22 has been switched off by applying an appropriate voltage to the gates of the active devices 26 through terminal D, by measuring the resistance between terminals Serp A and Serp_B, in a similar manner to that described with reference to Figure 1 of the drawings.

The modification of the structure of Figure 2 to achieve the above-described test structure according to the second exemplary embodiment of the present invention again requires no special process steps but, since it uses active devices, requires a full front end. Therefore it can be used in "full flow", but not with a so-called "back end short loop" flow, as will be apparent to a person skilled in the art. The proposed test structures of the first and second exemplary embodiments of the present invention, as illustrated in and described with reference to Figures 3 and 4 of the drawings, can be combined to form a single test structure 32 according to a third exemplary embodiment of the present invention, as shown in Figure 5 of the drawings. The combined test structure 32 illustrated in Figure 5 has full voltage contrast features for opens and shorts, as well as complete electrical measurability.

Thus, new test structures are proposed herein which combine voltage-contrast inspectability with electrical testability, wherein use of these test structures enhances the efficiency of root cause analysis of yield loss, and thus helps accelerate the yield learning curve so critical to new semiconductor manufacturing technologies.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A test structure (10, 20, 32) for detecting the presence of defects in conductive features formed on an integrated circuit topography, said test structure comprising a substrate on which is provided an insulating layer, on a first side of which insulating layer is provided a plurality of conductive lines (14, 22) and on the opposite side of which insulating layer is provided at least one connecting line (18, 30), at least two of said conductive lines (14, 22) being electrically connected together by said at least one connecting line (18, 30) by means of respective vias (16, 28) provided through said insulating layer from said first side to the opposite side thereof.
2. A test structure (10) according to claim 1, wherein a conductive comb- like structure (12; 24-22) is provided on the first side of the insulating layer with floating conductive lines (14) being provided between the lines of said comb- like structure.
3. A test structure (10) according to claim 2, wherein the conductive comb- like structure is a grounded comb- like structure (12) and wherein one end of each of the floating conductive lines (14) is connected, by means of a respective via (16) provided through the substrate, to a connecting line in the form of a conductive spine (18) provided on the opposite side of said insulating layer.
4. A test structure (20) according to claim 2, wherein a first end of each of the conductive lines (22) of the comb- like structure (24, 22) is selectively connected to ground by means of respective active switching devices (26), and the opposite ends of adjacent pairs of said conductive lines (22) are connected, by means of vias (28) provided through the insulating layer, to respective connecting lines in the form of conductive pieces (30).
5. A test structure (20) according to claim 4, wherein said active switching devices (26) comprise field effect transistors.
6. A test structure (20) according to claim 4, wherein an active switching device (26) is provided in respect of each adjacent pair of conductive lines (22) to selectively connect them to ground.
7. A test structure (32) according to claim 2, wherein one end of each of floating first conductive lines (14) is connected, by means of a respective via (16) provided through the insulating layer, to a first connecting line in the form of a conductive spine (18) provided on the opposite side of the insulating layer, and a first end of each of second conductive lines (22) of the comb- like structure (24, 22) is selectively connected to ground, and the opposite ends of adjacent pairs of said second conductive lines (22) are connected together, by means of vias (28) provided through the insulating layer to respective connecting lines in the form of conductive pieces (30).
8. A semiconductor device comprising a test structure as claimed in claim 1.
PCT/IB2006/051495 2005-05-19 2006-05-12 Test structure for combined electrical testing and voltage-contrast inspection WO2006123281A1 (en)

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CN104422870A (en) * 2013-09-10 2015-03-18 中芯国际集成电路制造(上海)有限公司 Test structure and test method for micro grooves
US9627371B1 (en) 2016-04-04 2017-04-18 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells
US9691672B1 (en) 2015-12-16 2017-06-27 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
US9721937B1 (en) 2016-04-04 2017-08-01 Pdf Solutions, Inc. Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
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US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US9805994B1 (en) 2015-02-03 2017-10-31 Pdf Solutions, Inc. Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
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Cited By (74)

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Publication number Priority date Publication date Assignee Title
CN104422870A (en) * 2013-09-10 2015-03-18 中芯国际集成电路制造(上海)有限公司 Test structure and test method for micro grooves
CN104201172A (en) * 2014-09-11 2014-12-10 武汉新芯集成电路制造有限公司 Test structure for monitoring dielectric layer film quality and hole-filling capacity
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US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
US9805994B1 (en) 2015-02-03 2017-10-31 Pdf Solutions, Inc. Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
US10199293B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas
US10211111B1 (en) 2015-02-03 2019-02-19 Pdf Solutions, Inc. Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas
US10211112B1 (en) 2015-02-03 2019-02-19 Pdf Solutions, Inc. Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas
US10290552B1 (en) 2015-02-03 2019-05-14 Pdf Solutions, Inc. Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
US10199290B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
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