WO2006114732A1

WO2006114732A1 - Liquid crystal displays with sequential drive schemes

Info

Publication number: WO2006114732A1
Application number: PCT/IB2006/051222
Authority: WO
Inventors: Jason R. Hector; John R. Hughes; Hidetoshi Watanabe
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-04-26
Filing date: 2006-04-20
Publication date: 2006-11-02
Also published as: TW200707366A

Abstract

A method of driving a liquid crystal display pixel comprises (i) driving the pixel to a reference state (30a, 32a, 34a) , (ii) driving the pixel to a first overdrive voltage derived from a desired pixel drive level (30b, 32b, 34b) , (in) driving the pixel to a second voltage derived from the desired pixel drive level (30c, 32c, 34c) ; and (iv) illuminating the pixel using a backlight (R, G, B) . These steps are repeated a plurality of times for each colour addressing operation, each repetition comprising an addressing phase. The illumination uses a different backlight colour output for each phase (30, 32, 34) .

Description

DESCRIPTION

LIQUID CRYSTAL DISPLAYS WITH SEQUENTIAL DRIVE SCHEMES

This invention relates to liquid crystal displays, in particular active matrix liquid crystal displays which use a sequential drive scheme to provide a colour output.

Active matrix liquid crystal displays (AMLCDs) typically generate coloured images by providing pixels which consist of three separate portions, each of which has a colour filter transmitting one primary colour. These portions usually cover an area of one third of a full pixel. As a result of limitations in process and design of the image portions, the aperture for transmitted light is reduced in AMLCD displays, resulting either in low brightness or high power in the backlight.

An alternative method for generating coloured images is to have just one portion per pixel space, and sequentially flash the backlight with the three colour primaries. This creates what is known as a colour sequential display. The liquid crystal pixel can then sequentially control the amount of each primary colour transmitted. Because the sequential flashing occurs quickly, the eye will integrate the light to perceive a full colour image.

A similar display technology is known as spectrum sequential display, and this technology only requires that the backlight is flashed twice per frame time. Colour is then generated by each backlight flash in the form of two primaries (for example blue and yellow in the first sub-frame and cyan and red in the second sub-frame). Each pixel is divided into two portions and each portion has a colour filter which transmits one primary from each flash of the backlight (for example blue and cyan for the first portion and yellow and red for the second portion). This approach thus provides a compromise between the time available for each flash of the backlight and the size of each pixel portion.

The two approaches above each rely upon flashing of the backlight, and the desired colour for each pixel is built up as a sequence of colour outputs. These two approaches can both be described as a "sequential drive scheme".

Typically, the pixel colour output must be derived within one frame time (of 16.6ms assuming a refresh rate of 60Hz). Within this frame time, all flashes of the backlight must be complete. This requires that the total time taken to address the LC pixels, wait for them to respond, and flash the backlight is approximately 5ms for (three-cycle) colour sequential displays and approximately 8ms for (two-cycle) spectrum sequential displays.

This time is of course a fraction of the frame period, and can be described as a sub-frame time period. Typical LC pixels take significantly longer than this to switch to the desired voltage.

The addressing of an AMLCD is typically carried out row-by-row. When the addressing time may not be sufficient for all possible changes in pixel output, there will be variations in brightness which will depend on the previous output of the pixel. There will also be variations in brightness depending on the position in the screen, as the rows which are addressed first will have a longer addressing period before the backlight flash.

These issues could in theory be addressed by improving the switching speed. This could be achieved by adjusting the material properties of the LC (to lower the viscosity) or adjusting the properties of the cell design (to reduce the cell gap).

On the one hand, reducing cell gap can only be taken so far before display manufacturing yield makes the technique unviable. On the other hand, low viscosity liquids are generally compromised in other areas. This means that current technology does not enable sufficiently fast LC response time to be obtained to remove variations across the display. Instead, drive scheme modification is required to tolerate the inability to switch sufficiently rapidly and remove the image artifacts which can result.

According to the invention, there is provided a method of driving a liquid crystal display pixel, comprising:

(i) driving the pixel to a reference state; (ii) driving the pixel to a first overdrive voltage derived from a desired pixel drive level;

(iii) driving the pixel to a second voltage derived from the desired pixel drive level; and

(iv) illuminating the pixel using a backlight, wherein steps (i) - (iv) are repeated a plurality of times for each colour addressing operation, each repetition comprising an addressing phase, the illumination using a different backlight colour output for each phase.

This method provides a sequential drive scheme in which all pixels are initially driven to a reference state. This removes dependency of the pixel output on the previous pixel drive level. An overdrive operation is then used, and this enables the pixel state to be driven to the desired value with rapid charge transfer. To ensure that all pixels reach a voltage level which is independent of their position in the display array, the second voltage level acts as a holding voltage, and effectively ends the pixel drive operation. This can be used to implement a fixed time duration during which the pixel drive voltage is varied, so that uniform response across the display can be obtained.

In this way, the drive scheme can overcome image artifacts usually present in sequential displays that are caused by the liquid crystal pixels not switching sufficiently rapidly.

The reference state may comprise a black pixel state, particularly for a normally white display. This reference state is then a state which requires the active matrix transistors of the display to be driven hard ON.

The second voltage can be derived from the pixel drive level taking into account the limit second voltage which can be reached within the addressing time available. For example, the second voltage can be selected to comprise substantially the pixel voltage reached during step (ii), and it thus acts as a holding voltage for holding the voltage appearing on the pixel at the end of the overdrive operation.

This method is preferably used for driving a liquid crystal display comprising an array of pixels. In this case, driving the pixel to a reference state comprises driving all pixels to the reference state. This can be carried out simultaneously.

Driving the pixel to a first overdrive voltage derived from a desired pixel drive level and driving the pixel to a second voltage derived from the desired pixel drive level can then comprise row-by-row driving of all pixels.

The effect of the second voltage, functioning as a holding voltage, is that the pixels are driven to the first overdrive voltage during a time window which is constant for all pixels.

When driving the pixels to a first overdrive voltage, a polarity pattern is preferably applied, and an opposite polarity pattern is applied when driving the pixels to a first overdrive voltage during the same phase of the next colour addressing operation. This removes dc offset between successive colour addressing operations. The pattern may be a checkerboard pattern, a row pattern, a column pattern, or other pattern.

When driving the pixels to the second voltage, a polarity pattern is also preferably applied, and again an opposite polarity pattern is applied when driving the pixels to the second voltage during the same phase of the next colour addressing operation.

Although a polarity pattern may also be applied when driving the pixels to the reference state, all pixels can instead be driven with the same polarity. All pixels may be driven with the same polarity in all phases, and with opposite polarity in all phases of the next colour addressing operation. Alternatively, all pixels can be driven with opposite polarity in sequential phases of each colour addressing operation.

There may be three phases, for a colour sequential drive scheme, or two phases, for a spectrum sequential drive scheme.

The invention also provides a liquid crystal display drive circuit for driving each pixel in phases, each phase comprising a sequence comprising: a reference state; a first overdrive state derived from a desired pixel drive level; and a second state derived from the desired pixel drive level.

A liquid crystal display using the drive circuit has an array of liquid crystal pixels and a backlight for illuminating the pixels after addressing to the second state, and using a different backlight colour for each phase.

Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

Figure 1 shows schematically the known method of sequentially driving a liquid crystal display;

Figure 2 shows how the sub-field time period may not be sufficient to enable a pixel to be driven to a desired brightness, and also shows the relationship between drive voltage and transmission/capacitance of the LC layer;

Figure 3 shows schematically the method of sequentially driving a liquid crystal display of the invention;

Figure 4 shows an example of the timing of one phase (for one colour or colour combination) of the sequential drive scheme of the invention;

Figure 5 shows how the pixel voltages vary during one phase of the sequential drive scheme of the invention;

Figure 6 shows a first polarity inversion scheme which can be used with the drive scheme of the invention;

Figure 7 shows a second polarity inversion scheme which can be used with the drive scheme of the invention;

Figure 8 shows a third polarity inversion scheme which can be used with the drive scheme of the invention; and

Figure 9 shows a display device of the invention.

Figure 1 shows schematically how a known sequential drive scheme operates.

The drive scheme shown has three phases 10, 12, 14. Each phase has row-by-row addressing of the pixel array (10a, 12a, 14a), and a wait period (10b, 12b, 14b) followed by the backlight flash, with the backlight flash in each phase being a different primary colour. This is thus a colour sequential drive scheme. The wait period allows the LC to switch to the newly addressed grey level and to tries to ensure the whole display has switched before the backlight is flashed.

One significant drawback of this scheme is that the LC response is too slow for the LC to have finished switching by the time the backlight is flashed. This means that the pixels at the top may be almost finished but pixels at the bottom of the display are still switching.

The speed of switching and the final transmission level after switching also depends on the previous sub-frame (i.e. phase) information. The LC is addressed to a new value, but has a capacitance which relates to the transmission during the previous sub-frame. This variable capacitance alters the response characteristics of the LC layer, and introduces response characteristics which are dependent on the previous output. This gives rise to further errors and image non-uniformities which can be detected by the viewer.

Figure 2 is used to show how the sub-field time period (i.e. the duration of the individual phases) may not be sufficient to enable a pixel to be driven to a desired brightness, and also shows the relationship between drive voltage and transmission/capacitance of the LC layer.

Plot 20 shows that within an available sub-field addressing time 22, the transmission of the LC layer may not be able to reach a desired 100% level, but can only reach 80% (height 24).

Plot 26 shows the relationship between LC drive voltage and transmission and uses the right hand y-axis. Plot 28 shows how the LC capacitance is dependent on the LC drive level and uses the left hand y-axis.

At low voltages, the transmission is high, and this diagram thus represents a normally white display.

The pixel LC cell has a high capacitance in the dark (low transmission), high voltage state compared to the bright, low voltage state. This difference in capacitance also gives rise to image artifacts.

Figure 3 shows schematically the method of sequentially driving a liquid crystal display of the invention. For the purposes of explanation, three sub- fields (or phases) are again shown, 30, 32, 34.

Each phase involves:

(i) driving the pixel to a reference state 30a, 32a, 34a; (ii) driving the pixel to a first overdrive voltage 30b, 32b, 34b;

(iii) driving the pixel to a second voltage 30c, 32c, 34c; and

(iv) illuminating the pixel using a backlight R₁G₁B (red, green, blue) with different backlight colours for the different phases.

The reference state is preferably the black pixel state. This "Black" addressing step removes memory of the previous sub-frame, and is also preferably an "overdrive" operation in that a voltage is applied which is beyond that required to reach the state. For example, the black state can be obtained by driving a high voltage (for example 7.5V) across the LC layer, even though 5V is sufficient to drive the LC layer into the black state. This additional operation also gives a good black level for pixels which are to be addressed to black, and thereby gives good contrast.

The black overdrive (assuming a normally white LC mode) is to a level where the derivative of the capacitance of the LC with respect to voltage has started to approach zero i.e. to high voltage in the case of a normally white display. This removes the memory from the previous sub-frame by forcing the pixels to a known capacitance. Switching from any grey level towards this black state is the fastest transition the LC makes, so this step can be short. By way of example, 5V may be needed for the black state, and the black addressing step may then involve applying 7.5V.

The response time of the LC layer is related to the viscosity and the strength of the turning force which can be applied. The viscosity is dependent on the LC material, and the turning force is dependent on the electric the field strength (dipole effect). The field is proportional to voltage applied and inversely proportional to the cell gap.

The transition towards white is slower because it is a relaxation transition.

The black addressing operation is improved if the pixels are all addressed at the same time rather than a row at a time. This is possible as all the pixels are being addressed to the same voltage. This provides an improvement because the LC is connected to the column via the ON TFT, which means any changes in capacitance that would normally cause changes in voltage (and hence the wrong transmission after the switching has finished) in the usual high impedance addressing situation are countered by charge from the column.

The LC response time does not give sufficient time for full switching to white from the black reference state. The time that is available (which depends on the number of phases) dictates the peak transmission of the LC which can be reached.

The voltage applied in the overdrive operation 30b, 32b, 34b is derived from the pixel drive level, but also takes into account the limit voltage which can be reached with the addressing time available. In particular, the pixels are addressed to a voltage that corresponds to, but is not necessarily, that required for the final desired transmission. The voltage chosen ensures the pixel switches as fast as possible - again as an overdrive operation. Overdrive is a known technique for increasing switching time, and is for example employed in LC-TV display applications.

In the example given, the overdrive voltage is a lower voltage than that determined by the desired pixel transmission, because the drive is towards the low voltage white state. Typically, the voltage for white is 1.5V and for maximum switching speed, the overdrive voltage will be OV. The other grey levels can then be scaled from this, so that the amount of overdrive varies in proportion to the required transmission.

The overdrive operation enables a pixel which is to be driven to white to reach as close as possible to the white state in the time available. For a pixel which is to be driven to a voltage near to a black grey level, no overdrive will be required, as the pixel may be able to reach the desired voltage within the time duration of the overdrive operation in any case. Thus, the voltages used during the overdrive operation will comprise a mapping of the desired voltage levels, and this mapping may be a non-linear function of the desired voltages. In addition, the desired voltages are ideally scaled, so that if the maximum brightness that can be achieved is 80%, all brightness levels are scaled by 80% to derive new target brightness levels.

It is these target brightness levels which are then used as the basis for the overdrive voltages and the normal drive voltages (discussed below). Again, the mapping of the image data to the target brightness levels may not be a uniform 80% scaling, but may again be a non-linear mapping function to give the best visual output for a given maximum transmission level.

The chosen overdrive voltage depends on the LC, LC mode and other display affects, and can also be different in positive and negative fields.

The aim is that by the time the pixel is next addressed the LC will have reached the target transmission and voltage characteristics that are desired for the phase.

The third addressing of the pixels, 30c, 32c, 34c, to the second voltage, involves selecting a voltage that directly corresponds to the target transmission desired. This may be considered to be a "normal" drive operation rather than the previous "overdrive" operation. Preferably, the previous overdrive level will have been chosen so that the pixel will be momentarily at this desired target value at the beginning of this normal addressing operation. Thus, the second voltage is selected to comprise substantially the pixel voltage reached during the overdrive operation. This stops the LC switching after its previous overdriven address operation and ensures that all pixels in the display are at the correct transmission level and have stopped switching when the backlight is flashed.

The example of Figure 3 is a three phase colour sequential drive scheme. The invention can be applied to other sequential drive schemes, and by way of example, Figure 4 shows an example of the timing of one phase for a two phase spectrum sequential drive scheme.

The total sub-field time period is 8.33ms. The black addressing operation 40 has a duration of 0.53ms, and this is sufficient to drive all the pixels simultaneously to black. The transistor in each pixel is held on for a period significantly longer than the normal line time (which is the addressing period divided by the number of rows, for example around 50 μs). The LC pixels thus stay connected to the columns and so can source / sink charge to the columns and hence to the driver ICs. This speeds up the switching and ensures the pixels end at the desired high voltage for switching to black. After a wait period 42 of 0.3ms, the overdrive addressing operation 44 begins. This comprises row by row addressing of the pixels, and during the 2.6 ms period shown all rows are addressed in turn. Each row is thus addressed for only a fraction of the 2.6 ms period (the period divided by the number of rows) and the remainder of the 2.6 ms is a settling period The addressing to the second voltage, during addressing operation 46, has the same 2.6 ms duration, and again involves row by row addressing. This is performed in the same row order, so that the settling period for the overdrive addressing operation has the same duration for each pixel.

A further wait period 48 again of 0.3ms precedes the backlight illumination 49, which has a duration of 2ms in the example shown. This wait period enables stabilization of the pixel values.

In the example above, the addressing periods (to black, overdrive and normal drive) last 6ms of the 8.33ms time available. The remaining time is available for backlight operation, and the backlight intensity will be selected in dependence on the time available for the backlight to be on.

The light from the backlight is proportional to the time it is on. However, the increase in light transmission is not proportional to the time available for switching. Initially, the increase in transmission is faster than proportional, but as the transmission increases, the speed decreases as the LC enters the real relaxation phase.

For example, after 2.5 ms of addressing, the LC may have reached 80% transmission. After 3 ms of addressing, the LC may only have reached 90%. If addressing with two 2.5 ms address pulses allows a backlight pulse 2ms long, then addressing with two 3ms address pulses will only allow a backlight pulse 1 ms long.

The relative corresponding transmission levels are 90%*1=0.9 for 3ms addressing and 80%*2=1.6 for 2.5ms addressing. Thus, more light output is achieved with shorter addressing schemes, giving lower power and lower cost.

By tolerating the inability to fully switch the LC layer into the white state during the addressing period, the invention enables shorter addressing periods and longer backlight illumination periods to be used. Figure 5 shows how the pixel voltages vary during one phase of the sequential drive scheme of the invention. The change in transmission setting over time for a pixel in the first row (plot 50) and for a pixel in the last row (plot 52) is shown. During the black addressing operation 54, both pixels are driven simultaneously to the black state. On the x-axis, 01 and 02 signify the timing of the start of the overdrive addressing operation, and N1 and N2 signify the timing of the start of the normal addressing operation. The pixels are only actively driven at the start of these addressing operations, as a result of the line-by-line addressing.

At the beginning of the overdrive addressing operation 56, the pixel in the first row is addressed to the overdrive voltage. At the end of the overdrive addressing operation 56, the pixel in the last row is addressed to its overdrive voltage. In the example shown, the pixel in the first row is to be driven to white, whereas the pixel in the last row is to be driven to an intermediate grey level.

The addressing operation 57, which terminates the overdrive operation, is also started in the staggered row by row manner so that the duration 58 of the overdrive addressing operation (in particular the settling period) is constant for all pixels. The normal drive operation has a duration which varies depending on the pixel row position, but this is merely a voltage holding operation and does not therefore introduce non-uniformity. Backlight illumination during period 59 is for all pixels.

Inversion schemes are implemented in many liquid crystal display devices. According to known inversion schemes, two different polarities of data voltage are employed (note these need not actually be positive and negative in an absolute sense, provided they produce opposite polarity voltages across the light modulating layer, e.g. liquid crystal layer, of the particular display device). Inversion schemes are employed to alleviate degradation of the liquid crystal material that would otherwise occur under continuous single-polarity operation, leading to undesirable effects such as image sticking. With these inversion schemes, the excitation voltage across the LC cell changes polarity with each frame displayed. The most simple scheme is frame, (or field), inversion in which the polarity for all pixels is inverted for each field.

As well as using an AC voltage across the cell, it is important that the AC voltage does not have a non-zero DC offset.

Any given pixel has different polarities applied to it in different frames (usually alternating frames), i.e. the polarity for the pixel is inverted over time. In addition, many inversion schemes have polarity inversion patterns, in which pixels are also inverted on a positional basis with respect to other pixels. This pattern may be arranged as rows or columns of pixels of the same polarity or as a checkerboard pattern (known as a dot inversion scheme or pixel inversion scheme). The dot inversion scheme has the advantage also of reducing the visibility of large area flicker in the display image.

Polarity inversion is preferably applied to the sequential drive scheme of the invention. In order to remove DC offset, the polarity inversion scheme needs to ensure that the polarity used for one phase of one colour addressing operation is reversed for the same phase of the next colour addressing scheme.

Figure 6 shows a first example of polarity inversion scheme suitable for use with the sequential drive scheme of the invention. Two colour addressing operations are shown (colour addressing frame 1 and frame 2), each with two phases (phase 1 and phase 2). In Figure 6, the two possible polarities are represented as "+" and "-" although this does not mean that the actual voltages are necessarily of equal magnitude and opposite sign.

Each phase comprises the three different pixel drive operations (black B, overdrive O and normal drive N).

For the black addressing operation B, all pixels are driven with the same polarity. This polarity alternates between phases within each colour addressing operation (in phase 1 , all pixels have positive polarity and in phase 2, all pixels have negative polarity).

The first, overdrive, addressing operation O uses a polarity inversion pattern. In the example shown, this inversion pattern is a checkerboard pattern. An opposite polarity pattern is applied for the overdrive addressing operation O during the same phase of the next colour addressing operation.

For example, in phase 1 of the first colour addressing operation, the overdrive operation O has a checkerboard pattern with the top left polarity as "+". In phase 1 of the second colour addressing operation, the overdrive operation O has a checkerboard pattern with the top right polarity as "-". This phase change removes DC offset from the pixel drive signals associated with the colour or colours of phase 1.

A polarity pattern is also applied to the normal drive operation N, and again an opposite polarity pattern is applied during the same phase of the next colour addressing operation.

In the example of Figure 6, the same polarity pattern is applied to the overdrive O and normal N drive operations.

Furthermore, in the example of Figure 6, this same polarity pattern is kept the same for all phases.

A slight variation is shown in Figure 7, in which the same polarity pattern is kept for the black addressing operation B for all phases of each colour addressing operation, and this polarity is pattern reversed at each successive colour addressing operation.

A further variation is shown in Figure 8, in which the polarity patterns for the overdrive and normal operations O₁D are reversed at each phase change. This arrangement means that the same polarity pattern is always used for a given phase. For example, the polarity pattern for the overdrive and normal operations O₁N for the first phase of each colour addressing operation is always a checkerboard with the top left as a "+", and the polarity pattern for the overdrive and normal operations O₁N for the second phase of each colour addressing operation is always a checkerboard with the top left as a "-". This means that the pixel drive scheme for a given colour is fixed, and this reduces flicker, although at the expense of possible image retention.

These polarity inversion schemes can easily be implemented using standard row and column drivers. For example, the schemes of Figures 6 and 7 have odd frames (i.e. odd numbered colour addressing operations) using one checkerboard pattern only for the O ad N drive operations, and have even frames using the opposite pattern for the O and N drive operations.

Although checkerboard patterns have been shown, these may be patterns based on alternating polarity rows or columns. Although the polarity of all pixel drive signals is shown to be the same in the black addressing operation B, a pattern may be applied, for example a checkerboard, row or column pattern. The driving of all pixels with the same voltage is preferred as all pixels can be driven simultaneously to the same voltage.

Figure 9 shows a liquid crystal display of the invention, in which a drive circuit 90 drives each pixel in phases, each phase comprising a sequence comprising the a reference state, the first overdrive state derived from a desired pixel drive level and the second state derived from the desired pixel drive level. The circuit 90 controls a row driver circuit 92 and a column driver circuit 94, for addressing the array of liquid crystal pixels 96. The backlight is shown as 98.

The invention is equally applicable to two or three phase sequential drive schemes. For a two phase sequential drive scheme, each pixel comprises two sub-pixels, and one such pixel is shown schematically in Figure 9 as 99. In one example, sub-pixels are arranged in vertical stripes, with one stripe of sub-pixels having broad-band green filtering and the other having magenta filtering. The colour output of the backlight is then red/green and blue/green in sequence. This implementation is suitable for available colour filters and lamps. Another arrangement, mentioned above, uses blue/yellow and cyan/red backlight output, with filtering so that one sub-pixel provides a blue output and then a cyan output, and the other provides a yellow output then a red output.

It is thus apparent that various combinations of backlight colour outputs and filters can be used to enable a colour to be built up from two sequential flashes and using two sub-pixels.

The polarity inversion patterns shown are merely by way of example and other patterns will be apparent to those skilled in the art. The examples above relate to RGB sequential drive schemes. The invention can also be applied to RGBW displays, in which an unfiltered white sub-pixel is used to increase display brightness. The pixel layout is different in such displays, but the same considerations apply to the addressing schemes.

Although positive and negative polarities have been discussed, the column voltage may always be positive. For example, the voltage range applied to the column may be approximately 4V to 11V, with a mid-column voltage of 7.5V. The overdrive voltage which drives to white will then be as close to this mid voltage as possible, for example 8V for the positive polarity drive and 7V for the negative polarity drive.

The invention has been described in detail using the example of a normally white display (i.e. high transmission at low voltage). The invention can also be applied to a normally black display configuration.

Various other modifications will be apparent to those skilled in the art.

Claims

1. A method of driving a liquid crystal display pixel, comprising: (i) driving the pixel to a reference state (30a,32a,34a; 40; 54);

(ii) driving the pixel to a first overdrive voltage (30b, 32b, 34b; 44; 56) derived from a desired pixel drive level;

(iii) driving the pixel to a second voltage (30c,32c,34c; 46; 57) derived from the desired pixel drive level; and

(iv) illuminating the pixel using a backlight (R₁G₁B; 49), wherein steps (i) - (iv) are repeated a plurality of times for each colour addressing operation, each repetition comprising an addressing phase (30,32,34), the illumination using a different backlight colour output (R₁G₁B) for each phase.

2. A method as claimed in claim 1 , wherein the reference state comprises a black pixel state (30a,32a,34a; 40; 54).

3. A method as claimed in claim 1 or 2, wherein the second voltage is derived from the pixel drive level taking into account the limit second voltage (24) which can be reached with the addressing time available (22).

4. A method as claimed in any preceding claim, wherein the second voltage is selected to comprise substantially the pixel voltage reached during step (ii).

5. A method as claimed in any preceding claim, for driving a liquid crystal display comprising an array of pixels, wherein: driving the pixel to a reference state (30a, 32a, 34a; 40; 54) comprises driving all pixels to the reference state; and driving the pixel to a first overdrive voltage derived from a desired pixel drive level (30b,32b,34b; 44; 56) and driving the pixel to a second voltage derived from the desired pixel drive level (30c,32c,34c; 46; 57) comprise row- by-row driving of all pixels.

6. A method as claimed in claim 5, wherein driving the pixels to a first overdrive voltage is performed during a time window (58) which is constant for all pixels.

7. A method as claimed in claim 5 or 6, wherein driving the pixels to a reference state (30a,32a,34a; 40; 54) comprises driving all pixels to the reference state simultaneously.

8. A method as claimed in claim 5, 6 or 7, wherein when driving the pixels to a first overdrive voltage (O), a polarity pattern is applied, and wherein an opposite polarity pattern is applied when driving the pixels to a first overdrive voltage (O) during the same phase of the next colour addressing operation.

9. A method as claimed in any one of claims 5 to 8, wherein when driving the pixels to the second voltage (N), a polarity pattern is applied, and wherein an opposite polarity pattern is applied when driving the pixels to the second voltage (N) during the same phase of the next colour addressing operation.

10. A method as claimed in any one of claims 5 to 9, wherein when driving the pixels to the reference state (B), all pixels are driven with the same polarity.

11. A method as claimed in claim 10, wherein when driving the pixels to the reference state, all pixels are driven with the same polarity in all phases, and with opposite polarity in all phases of the next colour addressing operation.

12. A method as claimed in claim 10, wherein when driving the pixels to the reference state, all pixels are driven with opposite polarity in sequential phases of each colour addressing operation.

13. A method as claimed in any preceding claim, wherein steps (i) to (iv) are performed three times for three phases (30,32,34).

14. A method as claimed in any one of claims 1 to 12, wherein steps (i) to (iv) are performed twice for two phases, and wherein each pixel (99) comprises two independently addressed sub-pixels.

15. A liquid crystal display drive circuit for driving each pixel in phases, each phase comprising a sequence comprising: a reference state (30a,32a,34a; 40; 54); a first overdrive state (30b, 32b, 34b; 44; 56) derived from a desired pixel drive level; and a second state (30c,32c,34c; 46; 57) derived from the desired pixel drive level.

16. A liquid crystal display comprising: an array of liquid crystal pixels (96); a drive circuit (90, 92, 94) as claimed in claim 15; and a backlight (98) for illuminating the pixels after addressing to the second state, and using a different backlight colour (R, G, B) for each phase.