WO2006087508A1

WO2006087508A1 - Charge pump circuits

Info

Publication number: WO2006087508A1
Application number: PCT/GB2005/050153
Authority: WO
Inventors: Clive Roland Taylor
Original assignee: Frontier Silicon Limited
Priority date: 2004-10-11
Filing date: 2005-09-12
Publication date: 2006-08-24
Also published as: EP1805893A1

Abstract

This invention relates to improved charge pump circuits for use particularly with phase locked loops (PLLs). Applications of embodiments of the invention include an improved PLL for a digital audio broadcast (DAB) receiver. A charge pump circuit for a phase locked loop, the circuit comprising: a current generator (P11); a current mirror (N2, N3, N7) having an input (404) coupled to said current generator, said current mirror having at least two series connected output transistors (N3, N7); and a charge pump output (402) coupled to at least one of said output transistors; the circuit having an on-state in which an output current is provided and an off-state in which substantially no output current is provided; the charge pump circuit further comprising; at least one switching device (N4) to switch said circuit between said on-state and said-off state by controlling a first (N3) of said output transistors; and a biasing circuit (N1, N6) to bias a second (N7) of said output transistors into an on-state when said charge pump circuit is in said off-state.

Description

Charge Pump Circuits

This invention relates to improved charge pump circuits, for use particularly in phase locked loops (PLLs). Applications of embodiments of the invention include an improved PLL for a digital audio broadcast (DAB) receiver.

Digital audio broadcast services are currently provided in two frequency bands, 174 - 240 MHz (Band 3 in the UK) and 143 - 1492 MHz (L Band) for the rest of the world; it is also useful for a DAB receiver to be capable of receiving conventional FM (Frequency Modulation) broadcasts, in the UK at 88 - 108MHz. Background information on digital audio broadcast service standards can be found in the EUREKA- 147 standard (ETSI Document EN300 401 Vl.3.3 (2001-5); reference may also be made to BS EN 1248.2001.

It is desirable to be able to provide a radio receiver circuit which is usable in both the present DAB frequency bands and preferably also for receiving conventional FM broadcasts. Preferably such a radio receiver circuit would be suitable for single chip integration so that a single integrated circuit may be provided for constructing a receiver for use with any of the presently envisaged DAB broadcast standards as well as with conventional FM. In order to achieve this efficiently it is desirable to be able to cover the very wide frequency ranges specified with a PLL incorporating a single VCO (voltage controlled oscillator).

Some useful techniques have already been described in the Applicant's co-pending UK patent applications numbers 0420844.3, 0420843.5, 0420842.7 and 0420841.9 all filed on 20 September 2004 (hereby incorporated by reference). Here we describe charge pump circuits which facilitate VCO control by, in embodiments, providing accurate delivery of pump current over a wide range of VCO tuning voltages. Applications of the circuits are not limited to PLLs, but it is helpful for understanding the invention to explain the circuits in this context. Referring to figure Ia, this shows a block diagram of a typical integer-N phase locked loop 10a. This comprises a phase detector 12 which receives a first input 12a from a reference frequency source and a second input 12b from a divided down output of the phase locked loop. The phase detector 12 provides an output to a loop filter 14, the output of the loop filter providing a control voltage 16 for VCO 18 which provides an output 20 for the phase locked loop circuit, and which also provides an input to a divide-by-N circuit 22 the output of which provides frequency divided input 12b to phase detector 12.

Figure Ib shows a linearised model 10b of the phase detector 10a of figure Ia in which, broadly speaking, like elements are indicated by like reference numerals.

In the model of figure Ib:

is the phase of the reference signal; θvco(s) is the phase of the VCO signal; θ_tsi_v(s) is the phase of the divided VCO signal;

K₀ is the VCO sensitivity in radians/second/volt (Ko^πKvco);

Kψ is the phase detector gain in volts/radian

F(s) is the loop filter transfer function;

N is the PLL divider ratio.

With this model, the transfer function relating θ_rcf(s) and θvco(s) is: _θW . U!⁾ _BJ L _[EqUation 1]

Θ_ref(s) l + K_φK₀F(s)/Ns

Further details of this and other PLL models can be found in, for example, Ulrich L. Rohde, David P. Newkirk; "RF/Microwave Circuit design for Wireless Applications", Wiley-Interscience, 2000, pp. 848-876. In such a system a phase (and frequency) detector generally comprises a sequential digital circuit which is treated by the edges of the divided down VCO frequency and reference frequency, the phase detector producing an "up" or a "down" output depending upon the relative timing of these edges. These outputs drive a charge pump which delivers a positive or negative (or zero) output current to the PLL loop filter. The loop filter generally comprises a low pass filter such as a series connected resistor and capacitor which converts the pump current to an analogue voltage for tuning the VCO.

As will be described in more detail later, it is generally desirable for a charge pump to deliver accurately matched "up" and "down" pump currents with, at the same, well matched on/off switching characteristics. Where this is not the case the VCO tuning voltage can include an error term at the reference clock frequency due to non-matched charge injection, resulting in clock spurs which can significantly contribute to output noise.

Some examples of prior art techniques are described in: GB2395384, US2004/004500, US660851 1 , US6636105, JP2003/218694, US6774730, US6664828, US6768359, US2004/010747, US2004/0160249 and "A Novel CMOS Charge-Pump Circuit with Positive Feedback for PLL Applications", Instituto Technologico de Puebia, ELECTRO 2001.

However known techniques are not able to provide accurate and well-controlled up and down pump current pulses with good matching of both on and off switching characteristics, in particular over a wide VCO tuning voltage range. Broadly speaking both up/down pump currents should deliver identical charge under PLL lock conditions for the full vtune range but current solutions either give a well matched charge over a narrow range centred at the natural midpoint value or attain equal pump current values over the full range but with poorly matched on/off characteristics. It is particularly difficult to provide matched switch-on characteristics for up and down current pulses.

According to a first aspect of the present invention there is therefore provided a charge pump circuit for a phase locked loop, the circuit comprising: a current generator; a current mirror having an input coupled to said current generator, said current mirror having at least two series connected output transistors; and a charge pump output coupled to at least one of said output transistors; the circuit having an on state in which an output current is provided and an off state in which substantially no output current is provided; the charge pump circuit further comprising: at least one switching device to switch said circuit between said on state and said off state by controlling a first of said output transistors; and a biasing circuit to bias a second of said output transistors into an on-state when said charge pump circuit is in said off state.

In embodiments biasing the second output transistor into an on-state when the charge pump circuit is in the off-state allows the charge pump to begin its switch-on from a known state for substantially all VCO tuning voltages. In effect all the transistors which substantially contribute to the charge output at switch-on are clamped thus providing a controlled switch-on which can also be readily matched to an equivalent circuit providing an opposite current to provide up and down pump currents. Preferably, therefore, separate current sources (one of positive, one of negative current) are provided by separate but matched "up'^" and "down" charge pumps; the biasing arrangements for these may also be tied together as described in more detail later. Preferably the biasing circuit is configured to provide the same bias to the second output transistor no matter whether the charge pump circuit is in the off state or the on state to reduce the overshoot (although, as will be seen later, in embodiments the bias in these two states differs slightly resulting in a small but well controlled overshoot).

In a preferred embodiment the current mirror comprises a Wilson current mirror which, as the skilled person will understand, typically comprises an input transistor, a diode- connected output transistor (the above-mentioned first transistor), and a feedback transistor (the above-mentioned second transistor); optionally one or more transistors may be included, for example a further diode-connected transistor in the input path to equalise (drain) voltages of the input and first output transistors. As the skilled person will appreciate, the transistors may comprise either MOS (metal oxide semiconductor) or bipolar devices (although for convenience reference is only made to MOS devices when describing the preferred embodiments). In embodiments the gate of the second output transistor is held at a substantially fixed voltage when the charge pump output (current) is off, thus facilitating precise definition of the charging characteristics of the circuit. Preferably the switching device is configured to connect a control (gate or base) connection of the first output transistor to a first power supply line of the charge pump circuit to switch the first output transistor off when the charge pump circuit is in its off-state. Preferably a second switching device is connected in series with the series-connected output transistors to disconnect these output transistors from a second power supply line of the charge pump circuit when the circuit is in the off-state. These two switching devices may comprise additional MOS or bipolar devices. The charge pump output may comprise a third output transistor to provide an additional output for the current mirror in a broadly conventional manner.

The biasing circuit for biasing the second output transistor preferably comprises first and second series connected bias transistors, each preferably diode-connected. Preferably one of these bias transistors is matched to the first output transistor and the second is matched to the second output transistor; in this context matched generally implies having sizes and/or threshold voltages in an integral ratio, for example 1:1, in an MOS device size being typically measured in terms of a W/L ratio. Conveniently the biasing circuit is connected to the current mirror input, and hence to the control connection of the second output transistor.

The current generator preferably comprises a substantially constant current generator, which may be adjustable, and can conveniently be implemented by means of a current control transistor with a suitable bias on a control terminal of the transistor to provide a current adjust input.

As previously mentioned a charge pump providing up and down pump current outputs may be implemented by means of a pair of charge pump circuits as described above. A further pair of replicas of these charge pump circuits may be employed to provide bias voltages for the MOS devices serving as current generators. These replicas preferably have their respective outputs connected together and are configured such that they are permanently on so that one drives an up current at the same time as the other drives a down current (from which it will be appreciated that the switching devices may be omitted from these replica circuits). This arrangement insures that the up and down currents are equal and opposite; one of the replica circuits may then be biased (that is have its current generator controlled) by the other circuit in order to achieve this equal current condition; the up and down biased voltages to achieve this may then be used to bias the actual charge pump circuits of the charge pump. Preferably the biasing arrangement is also servoed to the VCO tuning voltage such that the current control signals (current generator MOS device bias) provide equal (but opposite) currents for substantially all values of tuning voltage; this may be achieved by driving one of the current generators (MOS devices) from an operational amplifier with one input connected to the VCO tuning voltage and another to the joined replica charge pump circuit current outputs.

In another aspect the invention provides a charge pump circuit, the circuit comprising: a current generator having an output; a Wilson current mirror having a current input connection coupled to said current generator output and having a current output connection, said current mirror comprising at least an input transistor coupled to said current input connection, an output transistor coupled to said current output connection, and a third transistor series connected between said output transistor and said output connection said third transistor being further coupled between said current input connection and said current output connection, to mirror a current at said current input connection to said current output connection to provide a mirrored current; a charge pump output coupled to said Wilson current mirror to provide an output current dependent upon said mirrored current; and wherein said charge pump circuit includes at least one switching device to switch said charge pump output current between an on state and an off state, said charge pump circuit being configured such that in said off state said output transistor is held in an off-condition and said third transistor is held in an at least partially on-condition.

As previously mentioned the current generator may comprise a current source or a current sink and the input and output currents may either be positive or negative. In a further aspect the invention provides a method of switching a current for a charge pump, the method comprising: generating a current; mirroring said current to a charge pump output using a current mirror; and switching said mirrored current by switching an output transistor of said current mirror; the method further comprising maintaining at least a portion of an output stage of said current mirror in a biased~on condition when said mirrored current is switched off.

The invention further provides a current switching circuit for a charge pump, the circuit comprising: an input to receive an input current; means for a mirroring said current to a charge pump output using a current mirror; and means for switching said mirrored current by switching an output transistor of said current mirror; the circuit further comprising: means for maintaining at least a portion of an output stage of said current mirror in a biased-on condition when said mirror current is switched off.

These and other aspects of the present invention will now be further described, by way of example only, with reference to the accompanying figures in which:

Figures Ia to Ic show, respectively, a block diagram of a divide-by-N phase locked loop (PLL), a linearised model of the PLL of figure 1 a, and a block diagram of a DAB radio receiver circuit embodying aspects of the present invention;

Figures 2a and 2b show, respectively, a phase locked loop circuit, and a phase detection system incorporating a charge pump;

Figures 3a and 3b show example of charge pump circuits incorporating charge steering techniques;

Figure 4 shows a charge pump circuit current sink according to an embodiment of the present invention;

Figures 5a and 5b show, respectively, an NMOS charge pump current sink switching circuit and a PMOS charge pump current source switching circuit according to embodiments of the present invention; Figure 6 shows transient responses for the charge pump circuits of Figures 5b and 5a;

Figure 7 shows a charge pump bias generation circuit;

Figure 8 shows a circuit diagram of a complete charge pump incorporating a pair of charge pump switching circuits according to embodiments of the present invention; and

Figure 9 shows a block diagram of a complete DAB receiver incorporating the radio receiver circuit of Figure Ic.

Referring first to figure 1 , this shows a block diagram of a radio receiver circuit, as described in the Applicant^'s previous patent applications (ibid), up to an IF output stage (IFOUT). Tliis will generally be followed by analogue-to-digital converter (ADC) and digital signal processing (not shown) for final conversion down to base band and demodulation. In the receiver 100 of figure 1 the circuitry enclosed by solid line 102 is preferably provided on an integrated circuit.

The signal paths begin with off-chip band select filters 104a, b, c, for DAB signals in Band 3 and L-band and FM broadcast signals in Band 2; these may receive their inputs from a single, shared antenna, or from multiple antennas (not shown). These band select filters provide an input 108 into an on-chip variable gain low noise amplifier (LNA) 110; typically band selection information from base band processing circuitry determines which RF input is selected by multiplexer 106 for input into this amplifier. The output of LNA 1 10 is provided to an RF AGC circuit 112, and also to a quadrature down conversion mixer 114a, b, followed by a polyphase filter 116. Receiver 100 operates as a near zero IF receiver and thus the DAB input signal (which has a bandwidth of approximately 1.536MHz) is down converted to a first IF frequency oi 1.024MHz; as described in more detail in the applicant's related UK patent application No. ... filed on the same day as this application. A preferred IF frequency plan employs down conversion to a first IF frequency followed by up conversion to a second higher IF frequency, and this is implemented by local oscillator 118 and second quadrature mixers 120, which are followed by low pass filter 122 and variable gain output buffer 124 which provides a differential output (IFOUT) 126. Although not shown as such, for clarity, preferably all the signal paths in integrated circuit 102 are differential, including RF, local oscillator, and IF signals.

A frequency plan for the receiver of figure 1 is shown in table 1 below. This frequency plan demonstrates high-side injection of the first LO (that is, with the local oscillator frequency greater than that of the target RF signal, fto ⁼ fRF ⁺ fe)- Low side injection (with the local oscillator frequency less than that of the target RF signal, fto ⁼ far - f_\ψ) is also possible with this architecture.

Table 1

From table 1 it can be seen that the first local oscillator frequency must be controlled over a wide range. In the receiver 100 of figure 1 this first local oscillator is implemented by the circuitry within dashed line 128, this providing a quadrature output 130a, b to respective quadrature down conversion mixers 1 14a, b. This first oscillator circuit employs a PLL incorporating a charge pump which embodies aspects of the present invention. However, to facilitate understanding of the context of the invention, operation of the receiver of figure 1 will first be briefly outlined.

As previously described, the IF after downconversion is 1.024MHz for the DAB inputs (Band 3, L-Band); I is 150KHz for the FM input (Band 2). After polyphase filtering the signal is upconverted to 2.048MHz for DAB and 2.198MHz for FM, and an IF variable gain amplifier and output driver provides a differential ADC drive for a subsequent base-band IC (not shown in figure 1). A PLL with on-chip LC VCO and a post divider generates the first LO signal for all bands and this PLL, the second LO generation and the filter alignment are all referenced to the crystal reference frequency (of 16.384, 24.576 or 32.768MHz)

There are three LNA inputs, one for each frequency band. Each LNA has 4OdB of AGC control range, and a PIdB of-15dBm. Without external AGC components the chip can meet the -25dBm high level input requirements for portable receivers; an off-chip PIN diode attenuator may be used to extend the input range to -15 or -10 dBm. The RP input filters may provide protection for ESD discharges to an external antenna.

The IF filters combine the functions of channel selectivity, anti-alias filtering for the baseband ADC and quadrature combining for image rejection. The first IF filter is a four-pole bandpass filter centred at 1.024mHz, with 3dB bandwidth of 1.9MHz to 270IcHz. After the quadrature upconversion to the second IF, additional filtering is used to prevent aliasing. This is achieve with the second IF filter, which has an upper frequency of 2.048MHz and a bandwidth of 3.6MHz. A filter alignment circuit may be used to align the centre frequency and bandwidth of all IF filters to the crystal reference frequency. A calibration cycle may be run each time the PLL is re-programmed, or when the PLL or IF circuits are turned on. Periodically, say every half second, an on die temperature sensor may be employed to take a reading and update the filter tuning.

A first AGC loop controls the RF AGC amplifier and the (optional) external PIN diode attenuator to avoid overloading of the RF and IF circuits; this detects signal levels at the first mixer input and at the first IF filter output. The IF AGC amplifier provides the final gain at the second IF. This is preferably controlled by the baseband IC to give a constant input level to the ADC on the baseband chip.

In a preferred implementation the frequency synthesiser includes an integer ~N PLL comprising a fully integrated VCO, prescaler, phase detector, charge pump, reference divider and reference prescaler; and the loop filter is external. The reference divider divides down an externally provided reference frequency to a comparison frequency of 256IcHz for all bands. The VCO output is divided by 2 for L-Band, or by 12, 14 or 16 for Band 3 and by 28 or 32 for Band 2. The quadrature output of this programmable divider feeds the quadrature downmixers. This results in a first IF frequency of 1.024MHz for all DAB bands (IFDA_B), ^d 150KHz for Band 2 FM mode. The second LO of 1.024MHz (DAB mode) or 2.048MHz (FM mode) for the upconverter is divided down from the reference frequency. This results in a second IF frequency of 2.048MHz for DAB and 2.198MHz for FM mode. The PLL and post-divider provide a channel frequency resolution of 64 KHz for L-band and Band 3, and a 4 KHz resolution for fine tuning in Band 2,

Referring again to figure 1 , the local oscillator frequency synthesiser 128 employs an integer-N phase locked loop comprising a voltage controlled oscillator 132 providing an output to a postscaler 134 providing the quadrature outputs 130a,b, and phase locked loop (PLL) divider 136 also coupled to the output of VCO 132 and providing an output to a phase detector 138 comprising a charge pump (not shown in figure 1 ). Phase detector 138 also receives an input from a crystal oscillator 140 via a reference divider 142 as follows the phase detector 138 provides a charged pump output 139 to an external PLL low pass loop filter 144, the output of which provides a VCO tuning voltage (frequency control signal) to the VCO 132. in preferred arrangements the reference divider divides down a reference frequency from crystal oscillator 140 (which uses an external crystal) to a comparison frequency of 256KHz for all the three bands. A PLL resolution of 0.5 counts allows the VCO to be tuned in 128KHz steps.

Table 2 below shows the first local oscillator frequencies which are employed to obtain the desired first IF frequencies for DAB and FM modes, with high-side injection (local oscillator frequency greater than that of the target RF signal).

Table 2 To produce these local oscillator (LO) frequencies using a single integrated VCO, the output frequency of VCO 132 is chosen to be at a higher frequency than the required LO frequencies, and programmable divider 134 reduces the VCO output frequency as needed. As previously described the quadrature output 130 of programmable divider 134 feeds the quadrature downmixers 1 14.

The output of VCO 132 is divided by 2 for L-band; by 12, 14 or 16 for Band 3; and by 28 or 32 for Band 2. Different division ratios for a single band are thus used to cover sections of the band, thus reducing the VCO tuning range requirements, and in this way the VCO 132 need only run from 2.7GHz to 3.15GHz (a more detailed explanation can be found in GB0420844.3). However this range is still relatively large and, together with the band-switching, results in variation of the VCO sensitivity (Kvco, the change of the VCO frequency with tune voltage vtune) with the band-switching state and with vtune.

From equation 1 it can be seen that the loop gain is dependent on the VCO sensitivity and the loop filter transfer function and we have described elsewhere (GB0420844.3) and outline below how the PLL loop gain can be made substantially constant by varying the charge pump current with vtune and the band-switching state: Since for a given band-switching state, Kvco is approximately inversely proportional to the tune voltage the charge pump current should therefore be substantially proportional to the tuning voltage. This can be achieved by feeding back the charge pump output to the input of the charge pump to adjust the pump current.

Figure 2a shows the phase detector and charge pump 138 in more detail. This comprises a phase detector 150 along the lines described above and a charge pump 152 comprising a pair of adjustable constant current generators, a constant current source 154 and a constant current sink 156 driven by respective "up" and "down" signals from phase detector 150 to produce pulses of current as required. Each of current source 154 and current sink 156 has a respective current adjust input, and both these current adjust inputs receive a (scaled) input from an output 158 of the charge pump. In this way the charge pump output varies with output voltage. In operation the phase-frequency detector 150 compares the PLL divider output to the reference divider output, and, depending on the phase difference, sends an "up" or "down" pulse to enable a selected one of the two current sources of the charge pump. The combined output of the charge pump is connected to the external loop filter (to convert the output current pulse to an output voltage). The voltage at the output is fed back to the current sources and changes their magnitudes, Icp_p and Icp_n.

Figure 2b, this shows a charge pump 152 which incorporates adjustment of the charge pump current output with VCO band-switch state. The charge pump incorporates a pair of current sources 154, 156 as before, with feedback from the charge pump output 158, but additionally a set of three further pairs of (adjustable) current sources 154a, b, c; 156a, b, c (also with feedback) is employed to compensate for changes in VCO sensitivity with the selected band. The current sources 154a-c and sinks 156a-c are selected by respective control units 160, 162, which in turn receive inputs from the band-switching control signals Vi, V₂ and V₃. The current sources/sinks 154a, b, c, 156a, b, c are binary weighted and combined according to the band switching state, together with current generators 154, 156. For the highest band-switching state only current generators 154, 156 contribute to the charge pump output, and the output current is increased, by employing more of the current generators, the lower the band-switching state, to compensate for the reduced VCO sensitivity.

A band-switching controller is implemented using a simple voltage comparator that senses vtune and compares it to upper and lower limits. If vtune<vtune_mi_n for longer than a time t_dday the band is switched to a lower state; if vtune>vtune_max for longer than time t_cj_eiay, the band is switched to a higher state. The time t_dday is chosen to inhibit oscillation of the synthesizer between states and so that band-switching is not triggered by changes in vtune of short duration.

We next describe background to and then embodiments of preferred charge pump circuits suitable for use in the arrangements of Figures 2a and 2b. However the charge pump circuits we describe here do not need or rely upon bias voltage feedback from the VCO tuning voltage. Although desirable in the context of the circuits of Figures 2a and 2b, and in particular for the above described DAB receiver, in other configurations no such feedback is necessary.

Embodiments of the invention aim to provide a charge pump in which the tuning voltage output (vtune) has a wide range (that is the charge pump has a good compliance). In the preferred embodiments described below the tuning voltage output can range up to 40OmV below VDD and down to 200 rnV above VSS, which facilitates, in combination with the above described techniques, coverage of the very wide frequency range desirable for DAB using a single VCO.

Referring first to Figure 3 a, this shows an example of charge pump circuit 300 incorporating a charge steering technique, along similar lines to that shown in US 2004/004500 mentioned above. In this circuit a pair of current sources 302, 304 deliver respective positive (up) and negative (down) currents to an output 306 via a PMOS device 308 and an NMOS device 310 respectively switched by up _b (an active low up signal) and down signals. A second arm of the circuit comprises a PMOS device 312 and NMOS device 314 driven by respective up and down _b (an active low down signal) which are switched in a complementary fashion to devices 308 and 310. Thus when the down signal is active negative charge from sink 304 is steered to output 306 by device 310 and positive charge from source 302 is steered to a corresponding node 316 by device 312, and vice versa when the up signal is active. An operational amplifier 318 configured as a unity gain voltage follower is connected between output 306 and node 316 so that nodes 306 and 316 are held at the same voltage (vtune). This way the current generators 302, 304 see the same voltage, vtune, no matter where the current is steered to output 306 or node 316. In this way the positive and negative charge delivered is balanced providing that the antiphase up/down signals from the phase/frequency detector (PFD) are synchronised and the pump currents are equalled. This is achieved by steering the current so that the same current is flowing when the charge pump circuit is pumping either up or down. However a problem with this circuit is that although the switches 308, 310, 312, 314 see the same voltage on their source connections, this voltage changes and therefore the (fixed) pump currents are equal only in a narrow centre band of output (vtune) voltages, which constitutes an optimum region of operation of the circuit. Figure 3b illustrates a variation of the circuit of Figure 3a in which like elements are indicated by like reference numerals, intended to ensure equal pump currents over a wide vtune range. This is achieved by operational amplifier 318 which, in the circuit 350 of Figure 3b is configured in a differential mode to maintain substantially zero volts difference between nodes 306 and 316 by providing an output 320 which controls the bias on an additional pair of PMOS transistors 322, 324. A corresponding pair of NMOS transistors 326, 328 is provided in the other half of the charge pump circuit, these devices having control connections 330 set at a defined bias voltage by a bias circuit (not shown). In the arrangement of Figure 3b transistors 322, 324, 326 and 328 act as controllable current generators and switches 312 and 314 are both permanently on to provide a reference current through node 316. The OP amp-based biasing arrangement for transistors 322, 324 ensures that the up and down pump currents are equal since they must be equal in the left hand branch of the circuit) and this equality is maintained over a wide vtune range. Broadly speaking the operational amplifier 318 adjusts the bias on PMOS devices 322, 324 such that the voltage at node 316, which is determined by the currents flowing tlirough permanently on switches 312, 314, is the same as the vtune voltage at node 306 thus effectively forcing the up and down currents to be equal for all vtune values.

The circuit of Figure 3b is useful but still exhibits some problems. In particular the large voltage swing of the drain region of the biased devices creates an RC time constant which is dependent upon the vtune value such that well matched charge delivery is only obtained over the centre band region, hi other words the drains of the switches being switched for delivering charge vary between VDD and ground (VSS), according to vtune, so that the inipedence of these switches depends upon vtune and hence the time constant for charging/discharging an integrating load capacitor to which the charge pump is connected depends upon the value of vtune. For vtune values in the middle of the voltage range the impedences of the up and down switches are approximately matched and thus the charge/discharge characteristics of the circuit are also approximately matched in this region. However when vtune is close to either VDD or ground one of the switching devices is operating in a significantly different region of the device characteristic curve to the other and thus the up and down charge delivery ceases to be matched even though the up and down currents remain matched.

We next describe an improved circuit which addresses aforementioned problem.

Referring to Figure 4, this shows a charge pump circuit 400 for delivering a negative pump current (the circuit is a current sink), for use together with a similar circuit for delivering a positive pump current. The two circuits may be combined in a conventional manner although preferably an operational amplifier is used along similar lines to those shown in Figure 3b, to equalise up and down pump currents. Charge pump circuit 400 is configured to provide precisely controlled on and off switching characteristics over a large vtune range, through the use of a Wilson current mirror. As explained further below, the circuit is configured for a fast switch-off under control of NMOS device N4 but, more importantly, the circuit is configured to start up, that is switch on, in a controlled manner. This is because when transitioning from the off to the on state the circuit always starts from a known (bias) state, no matter what the value of the tune. This is achieved by ensuring that no transistors contributing to the switch- on characteristics are left floating or discharging; instead these devices are all clamped to particular voltages. The use of a Wilson current mirror enables the current mirror to be held in a known state even when the output is off.

The pump circuit 400 of Figure 4 is here referred to as an NMOS pump circuit and devices labelled as Nx are NMOS devices whilst devices labelled as Px are PMOS devices. In an equivalent PMOS pump circuit providing a positive pump current (that is operating as a current source) the NMOS and PMOS devices are exchanged. In a matched pair of NMOS and PMOS charge pump circuits matched transistors are employed (so that, for example, Nl in one circuit is equivalent to Pl in the other circuit). In this way the NMOS on/off switching profile can be well matched with that of the PMOS pump current circuit design and will have high PVT (process/voltage/temperature) independence providing parasitic capacitances are well matched. Referring now to the circuit 400 of Figure 4 in more detail, N5"s drain is the output current sink 402 of the charge pump. Devices N2/N3/N7 form a Wilson current mirror reference with Pl 1 as the reference source. Device N5's gate is controlled via the current mirror from the diode configured N3 device to provide an output for the current mirror. Node 404 provides an input to the current mirror and device Pl 1 is biased to provide a substantially constant current input to the circuit, adjustable by adjusting the voltage vpbias on the gate connection of Pl 1. Devices N4/P12 switch the Wilson current mirror on and off.

In circuit 400 the following devices are matched with one another:

N6 with N7

Nl with N2, N3 & N5

In the on-state (output current flowing) P12 is effectively a short circuit and N4 is open circuit so that the current mirror functions in a conventional manner, and because of the matching equal currents from Pl 1 flow through N2 and N6/N1. Half of current I_1n through device PI l flows through N6/N1 and half flows into the current mirror (through N2), and this determines the voltage at node 404, and hence on the gate of N7. In the off state (no output current flowing) N4 shorts the gate of N3 to VSS, turning the current mirror output off. Substantially all current I_1n through device Pl 1 flows through N6/N1 and thus the voltage at node 404, and hence on the gate of N7 is slightly increased because of the increased voltage drop across the two diode-connected transistors Nl and N6 due to the increased current.

It can be seen that, broadly speaking, cascoded transistor N7 of the Wilson mirror has its gate held at a fixed voltage when the circuit is in its off state (output current is off), and in this way the charging characteristic of the circuit can be much more precisely defined than if Nl and N6 were not present. More particularly the gate of N7 is held at substantially the same voltage when the circuit is in its off state and when the circuit is in its on state, apart from the small, above-mentioned second order effect. Cascoded devices Nl and N6 effectively act as a memory for the gate voltage on N7. As described later with reference to Figure 6 the small difference in gate voltages between the off and on states results in a small amount of controlled overshoot, but this is well- controlled.

As the circuit transitions from the on-state to the off-state the following events occur: The N6/N1 devices hold N7's gate (connected to node 404) at an appropriate voltage level (otherwise the gate would see VDD). The N4 device turns off the Wilson current mirror devices N2/N3/N5 by pulling their gates to VSS, and Pl 2 is switched off causing N7's drain to be pulled towards VSS. Thus all the current from Pl 1 starts to flow through the cascoded N1/N7 devices thereby increasing N7's gate voltage.

As the circuit transitions from the off-state to the on-state the following events occur: Switching device Pl 2 is switched on and switching device N4 is switched off, thus creating a current flow across N7. The gate voltage of N7 controls the current flow, which decreases as more current is steered through N2 via the loop gain action of N3/N2/N7 until equilibrium is reached, that is equal current flow through N6/N1 and N2. The current mirror ensures a substantially identical current flow profile at charge pump output 402.

These transitions result in a current switching profile in which the charge pump sink current is turned off rapidly and in which the charge pump sink current is turned on relatively slowly, from an initial N7 gate voltage condition which controls the overall current flow characteristics at charge pump output 402.

Figures 5a and 5b show, respectively, an NMOS charge pump current sink switching circuit 500 and a PMOS charge pump current source switching circuit 550, in which like elements to those of Figure 4 are indicated by like reference signs (bearing in mind that N and P devices are exchanged in Figure 5b as compared with Figure 5a). Preferably transistors N(P)I, N(P)2, N(P)3, N(P)S are fabricated according to I/O rules. Replicas of these circuits with matched devices may be used for bias voltage generation, as described further below.

In unmodified form the Wilson current mirror would exhibit an initial on-switching pump current spike of typically four times the final value, with associated ringing. The cascoded devices N6/N1 (and P6/P1 in the PMOS equivalent version) and their current sharing action with the N2 branch (and P2 branch in the PMOS circuit version) respectively produce a damping effect. Ringing tendencies are offset by the change in voltage seen on N7/P7's gates caused by the disproportionate amount of current flowing through the cascoded devices noted above.

The design therefore reduces current spikes and helps to ensure PMOS/NMOS switching symmetry by appropriately controlling the gate voltage of N7/P7 in the Wilson current mirrors during the on/off-state; also, the antiphase accuracy of the up/down signals from the PFD (phase-frequency detector) is no longer critical.

Referring to Figure 6, this shows transient responses 600, 602 for the positive and negative (source and sink) charge pump circuits of Figures 5b and 5a respectively. It can be seen that the current (on the Y-axis) rapidly achieve a steady state value with minimal overshoot, and that the switch off is rapid. It is also apparent that the positive and negative charge pump circuits are well matched.

Figure 7 shows a charge pump bias generation circuit 700 comprising an "up" charge pump 550 and a "down" charge pump 500 with their vtune outputs connected together and to one input of an operational amplifier 702. One of the charge pump circuits, in this case the PMOS circuit 550, is connected to a bias voltage vnbias and is further connected so that its "up" input is permanently on; likewise the other charge pump circuit is connected so that its control input (in this case "down") is also permanently on. The other input of operational amplifier 702 is connected to vtune and the output of the operational amplifier provides a bias voltage input for the second charge pump circuit, in this case a vpbias voltage for NMOS charge pump circuit 500. It will be appreciated that this arrangement is analogous to that shown in Figure 3b. Thus the voltages vnbias and vpbias from bias circuit 700 can be used to bias actual up and down charge pump circuits for providing a current output with matched up and down pump currents. As previously explained with reference to Figure 3b, the operational amplifier 702 ensures that the NMOS and PMOS current generator bias voltages generate equal and opposite currents in the corresponding NMOS and PMOS switching circuits. It will be appreciated that preferably, therefore, the circuits 500, 550 of bias generator 700 are matched to the corresponding circuits used for switching the output current.

Figure 8 shows a circuit diagram of a complete charge pump 800 incorporating a pair of charge pump switching circuits 500, 550 as previously discussed. These receive respective vnbias and vpbias signals from the bias circuit 700 of Figure 7. These switches have respective inputs up_swt and down_swt 802, 804 driven from a phase/frequency detector (pfd) 806, which in turn receives a reference clock input from reference divider 142 of Figure I c and a divided VCO clock input from PLL divider 136 of Figure Ic. The outputs of charge pump switching circuits 500, 550 are coupled together to provide a vtune output 808, typically provided to a capacitor 810 (or similar arrangement) as indicated for charge integration.

Figure 9 shows a block diagram of a complete DAB receiver 900 incorporating the radio receiver circuit of figure 1. In Figure 9 the IF output of the receiver circuit of figure 1 is provided to an analogue-to-digital converter 912 for digitisation and subsequent coded orthogonal frequency division multiplexed (COFDM) signal demodulation by COFDM demodulator block 914. The output of demodulator 914 is provided to a DAB protocol stack decoder 916, which in turn provides an MPEG datastream to MPEG audio decoder 918 which provides an audio output to stereo DAC 920 and audio amplifiers and speakers 922. A man machine interface (MMI) 924 interfaces with DAB protocol stack decoder 916 to provide a user keyboard 926 and display 928. These allow a user to interact with and control the receiver via the slave control processor and registers of receiver circuit 100.

Embodiments of the circuits and architectures have been described with particular reference to their application in the front end of a digital audio broadcast (DAB) radio receiver. However the skilled person will appreciate that applications of embodiments of the invention are not limited this and include digital radio broadcast receivers in general, for example DVB (digital video broadcast) and DMB (digital multimedia broadcast) receivers, as well as applications in other types of receiver and outside the field of receivers, for example in frequency synthesisers in general. No doubt many other effective alternatives will occur to the skilled person and it will be understood that the invention is not limited to the described embodiments but encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS:

1. A charge pump circuit for a phase locked loop, the circuit comprising: a current generator; a current mirror having an input coupled to said current generator, said current mirror having at least two series connected output transistors; and a charge pump output coupled to at least one of said output transistors; the circuit having an on state in which an output current is provided and an off state in which substantially no output current is provided; the charge pump circuit further comprising: at least one switching device to switch said circuit between said on state and said off state by controlling a first of said output transistors; and a biasing circuit to bias a second of said output transistors into an on-state when said charge pump circuit is in said off state.

2. A charge pump circuit as claimed in claim 1 wherein said biasing circuit is configured to provide approximately the same bias to said second output transistor when said circuit is in said off-state and when said circuit is in said on state.

3. A charge pump circuit as claimed in claim 1 or 2 wherein said biasing circuit comprises first and second series connected bias transistors.

4. A charge pump circuit as claimed in claim 3 wherein said first bias transistor is matched to said first output transistor and said second bias transistor is matched to said second output transistor.

5. A charge pump circuit as claimed in any one of claims 1 to 4 wherein said biasing circuit is connected to said current mirror input.

6. A charge pump circuit as claimed in any one of claims 1 to 5 wherein said current mirror comprises a Wilson current mirror comprising an input transistor and said first and second output transistors, and wherein said first output transistor comprises a diode-connected transistor, and wherein said second output transistor is connected to provide a feedback path from said first output transistor to said input transistor.

7. A charge pump circuit as claimed in claim 6 wherein said at least one switching device is configured to connect a control connection of said first output transistor to a first power supply line of said charge pump circuit.

8. A charge pump circuit as claimed in any one of claims 1 to 7 further comprising a second switching device connected in series with said series-connected output transistors to disconnect said output transistors from a second power supply line of said charge pump circuit when said circuit is in said off state.

9. A charge pump circuit as claimed in any one of claims 1 to 8 wherein said charge pump output comprises a third output transistor having a control connection coupled to a control connection of said first output transistor.

10. A charge pump circuit as claimed in any one of claims 1 to 9 wherein said current generator comprises a current control transistor connected between said current mirror input and a power supply line for said charge pump circuit.

11. A charge pump circuit as claimed in any preceding claim wherein said transistors comprise MOS devices.

12. A charge pump comprising a pair of charge pump circuits as claimed in any preceding claim, one of said charge pump circuits being configured to provide a positive current output, the other of said charge pump circuits being configured to provide a negative current output.

13. A charge pump as claimed in claim 13 further comprising a current control circuit to provide a pair of current control outputs for controlling said current generators of said pair of charge pump circuit, said current control circuit comprising a pair of replicas of said charge pump circuit, each said replica comprising at least a said current generator, a said current mirror, a said charge pump output and a said biasing circuit, each said replica current generator being controllable, said replicas having their respective charge pump outputs connected together, both said replica circuits being configured such that they are in said on state, and such that the current generator of one of said replica charge pump circuits is servoed to the current generator of the other said replica charge pump circuits.

14. A charge pump circuit, the circuit comprising: a current generator having an output; a Wilson current mirror having a current input connection coupled to said current generator output and having a current output connection, said current mirror comprising at least an input transistor coupled to said current input connection, an output transistor coupled to said current output connection, and a third transistor series connected between said output transistor and said output connection said third transistor being further coupled between said current input connection and said current output connection, to mirror a current at said current input connection to said current output connection to provide a mirrored current; a charge pump output coupled to said Wilson current mirror to provide an output current dependent upon said mirrored current; and wherein said charge pump circuit includes at least one switching device to switch said charge pump output current between an on state and an off state, said charge pump circuit being configured such that in said off state said output transistor is held in an off- condition and said third transistor is held in an at least partially on-condition.

15. A charge pump circuit as claimed in claim 14 wherein said charge pump circuit is configured such that said third transistor has substantially the same bias when said charge pump output is in said on-state and when said charge pump circuit is in said off state.

16. A charge pump circuit as claimed in claim 14 or 15 wherein said input transistor and said output transistor each have a control connection, said input and output transistor control connections being connected together and to said third transistor, and wherein said third transistor has a control connection connected to said current mirror current input connection.

17. A charge pump circuit as claimed in claim 16 further comprising a biasing circuit connected to said third transistor control connection.

18. A charge pump circuit as claimed in claim 17 wherein said biasing circuit comprises a pair of series connected devices connected between said third transistor control connection and a supply line of said charge pump circuit.

19. A charge pump circuit as claimed in claim 16, 17 or 18 wherein said at least one switching device comprises a transistor connected across said output transistor.

20. A charge pump circuit as claimed in claim 19 further comprising a switching device coupled in series with said output transistor and said third transistor.

21. A method of switching a current for a charge pump, the method comprising: generating a current; mirroring said current to a charge pump output using a current mirror; and switching said mirrored current by switching an output transistor of said current mirror; the method further comprising maintaining at least a portion of an output stage of said current mirror in a biased-on condition when said mirrored current is switched off.

22. A method as claimed in claim 21 comprising maintaining said current mirror output stage portion with approximately the same bias when the mirrored current is both on and off.

23. A method as claimed in claim 22 wherein said current mirror is a Wilson-type current mirror.

24. A current switching circuit for a charge pump, the circuit comprising: an input to receive an input current; means for a mirroring said current to a charge pump output using a current mirror; and means for switching said mirrored current by switching an output transistor of said current mirror; the circuit further comprising: means for maintaining at least a portion of an output stage of said current mirror in a biased-on condition when said mirror current is switched off.