WO2006086703A1

WO2006086703A1 - System for handling bad storage locations in memory

Info

Publication number: WO2006086703A1
Application number: PCT/US2006/004868
Authority: WO
Inventors: David Edward Trytko
Original assignee: Ampex Corporation
Priority date: 2005-02-11
Filing date: 2006-02-10
Publication date: 2006-08-17

Abstract

The present invention comprises memory systems, methods and apparatus including systems, methods and various apparatus for addressing memory devices that may include bad memory storage locations. A received logical memory address may comprise a block address and a page address. a lookup table identifies bad addresses/blocks. The method maps the logical block/address to a physical block/address, which is offset from the logical block/address by the number of bad blocks/addresses preceding it in the memory. The lookup table contents may be updated if further blocks/addresses become bad while the memory is in use.

Description

SYSTEM FOR HANDLING BAD STORAGE LOCATIONS IN MEMORY

FIELD OF THE INVENTION

The present invention relates generally to storage technology, and more particularly, to addressing memory devices having faulty or bad memory storage locations.

BACKGROUND OF THE INVENTION

With continuing advances in memory chip technology, increasingly more memory is being packed into increasingly smaller chips. One memory technology in substantial use today is flash memory. Flash memory devices are solid state, high density, non-volatile memory devices. The address range for a memory is typically separated into smaller segments of memory, which in a flash memory device are commonly referred to as blocks and pages. Each page segment typically has a storage capacity of 512 bytes, while each block segment typically has a storage capacity corresponding to 32 pages. However, the number of blocks per memory device, pages per block and bytes per page may vary between different types of memory devices.

One problem with flash memory devices is that often they have one or more faulty memory storage locations that return corrupted data during read or write operations. When a memory block within a flash memory device contains a faulty memory location, it is general practice to treat the entire block as a bad block. Each manufacturer typically specifies what it considers to be an acceptable number of bad blocks per memory device. The number and location of faulty blocks in a memory device typically is different for each memory device. Another problem that must be anticipated is that bad blocks may develop over time due to repetitively erasing, writing and reading from blocks while memory devices are in use. Combining multiple flash memory devices, manufacturers can build large solid state memory modules that can be used for a number of applications, including solid state recorders. However, when combining individual flash memory devices into larger memory modules, dealing with the faulty memory storage locations of the memory devices is a problem that must be overcome.

SUMMARY OF THE INVENTION

The present invention comprises memory systems, methods and apparatus including systems, methods and various apparatus for addressing memory devices that may include bad memory storage locations. In one embodiment, an address mapping device receives an address identifying a memory storage location within a memory and outputs a corresponding modified memory storage location address of a good, i.e., non-faulty memory location that compensates for faulty memory locations within the memory. In memories having addressing architectures which separate the storage locations of a memory into memory devices, blocks and pages, the address mapping device receives a device address identifying one of a plurality of memory devices and a block address. The address mapping device outputs a corresponding modified block address of a good memory location which compensates for the number and location of bad memory blocks within the memory device identified by the device address. The modified block address is used to address the memory device identified by the device address, whereby bad memory blocks within the memory device are skipped over in favor of good memory locations within the memory device.

The address mapping device can be implemented as a lookup table that includes entries that map input memory storage location addresses to modified memory storage location addresses. In embodiments having device, block and page memory addressing architectures, the address mapping device is a lookup table that includes an entry for each block memory location address of a plurality of memory devices. Each entry maps an input block memory location address to a modified block memory location address. In another embodiment, each entry maps an input block memory location address to an offset value. The offset value is the number of bad memory block locations between a first addressable memory location of the memory device and the memory location associated with the input block memory location address. The offset value output from the lookup table is added to the corresponding input block memory location address to create the modified block memory location address.

In another embodiment of the present invention, one or more entries in a lookup table may be updated to compensate for additional bad memory block locations that develop over time.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made to embodiments of the invention, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.

Figure 1 is a block diagram of a memory system and apparatus that includes a system and apparatus for addressing a memory device according to one embodiment of the invention.

Figure 2 is a block diagram of a lookup table 220 and an adder 230 for providing a modified block memory location address according to one embodiment of the invention.

Figure 3 is a block diagram of a lookup table 320 and two adders, 330 and 340, for providing a modified block memory location address according to one embodiment of the invention.

Figure 4 is a block diagram of a lookup table 420 and an adder 430 for providing a modified block memory location address according to one embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Memory methods, systems and apparatuses having the capability of handling faulty storage locations in a memory including solid state memory devices are described. For purposes of explanation, specific details are set forth in order to provide an understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these details. Furthermore, one skilled in the art will recognize that embodiments of the present invention, described below, may be implemented in a variety of mediums, including software, hardware, or firmware, or a combination thereof. Accordingly, the figures described below are illustrative of specific embodiments of the invention and are meant to avoid obscuring the invention.

Reference in the specification to "one embodiment," "a preferred embodiment" or "an embodiment" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Figure 1 is a block diagram of a memory system and apparatus according to one embodiment of the present invention. The embodiment of the memory system and apparatus of Figure 1 has a device, block and page memory addressing architecture. This embodiment includes memory devices 110A-H, a lookup table 120 and a demultiplexer 130. As illustrated, memory devices 110A-H are connected to a common data bus 140. In addition, each memory device 110A-H is connected to demultiplexer 130 and lookup table 120.

In one embodiment of the invention, a device address selects the memory device 110 that is active during a memory access. In the case of a read operation, data is output from the active memory device 110 over data bus 140. In the case of a write operation, data is input to the active memory device 110 over data bus 140. In the embodiment illustrated in Figure 1, a three-bit device address is used to address the eight memory devices 110A-H. As illustrated, the three-bit device address is input to demultiplexer 130. Based on this address, demultiplexer activates one of the memory devices 110A-H through connectors 150A-H. Upon selecting a particular memory device 11 OA-H, the page and the block memory storage location addresses are used to select the specific block and page memory storage location segments, within the active memory device. In one embodiment, the page address may be provided directly to each memory device 110A-H.

As discussed above, each memory device 110A-H may include bad memory blocks that need to be skipped when performing a memory access on a particular memory device. The number and locations of the bad memory blocks within each memory device 110A-H are likely to be different. To compensate for the bad memory blocks, the block address and the device address are mapped to a corresponding modified block address within the memory device containing the bad memory blocks as discussed further herein. In one embodiment of the invention, a portion of the memory blocks that make up each memory device 110A-H are set aside or reserved to compensate for a particular number of bad memory blocks within each memory device. Lookup table 120 manages the memory access by receiving an input block address along with a device address and outputting a modified block address that skips over bad blocks. In one embodiment, lookup table 120 includes a table of modified block addresses for each memory device 110 which links each input block address of the memory device to its corresponding modified block address. A separate table for each memory device 110 is included since the location and number of bad blocks are likely to be different for each memory device 110. One skilled in the art will recognize that there are number of ways to implement lookup table 120, including using a memory device, firmware, a software routine or combinations thereof. In one embodiment of the invention, memory devices 110A-H are NAND flash memory chips. As discussed above, flash memory devices typically have an address range that is separated into smaller segments of memory referred to as blocks and pages. The number of blocks per memory device may vary, but for example purposes, assume that each memory device 110 is comprised of 4096 blocks.

To account for bad blocks, a portion of the 4096 blocks are reserved to compensate for the bad blocks that may be present in each memory device. In one embodiment, a predetermined number of blocks may be set aside or reserved to cover for the bad blocks. For example, the number of reserved blocks may be based on the number of bad blocks that the manufacturer considers acceptable for a particular type of memory device. Each memory device distributed by the manufacturer should have that number or fewer bad blocks. Thus, reserving this number of blocks should be sufficient to compensate for the actual number of bad blocks that may be in each particular memory device. One advantage of this approach is that each memory device will have the same number of addressable memory blocks. In another embodiment, the actual number of bad blocks may be determined for each memory device. For example, a memory access may be performed on each memory location of a particular memory device to determine the number and location of bad memory locations on the device. Memory locations that return corrupted or otherwise incorrect data usually are unusable. The memory block that includes the bad memory location is treated as a bad memory block. A number blocks equivalent to the number of bad memory blocks determined for a particular memory device may be reserved in the memory device to compensate for the bad blocks.

For example purposes, assume that memory devices 110A-H all come from the same manufacturer who specifies that each memory device of this type will have fewer than 97 bad memory blocks. This means that 96 blocks may be reserved in each memory device to compensate for the number of bad blocks in the memory- device, leaving 4000 usable blocks of memory for data storage purposes. To ensure the addressing of memory devices 110A-H is transparent to an external device, such as a CPU, sending memory access requests, the external device simply addresses 4000 blocks in each of the memory devices 110A-H. It should be noted that in the embodiment described above, each memory device

110A-H may have a different number of actual bad memory blocks. Thus, some memory devices 110 may have fewer than 96 bad blocks. In this case, some reserved memory blocks will not be used by the memory device. In an alternative embodiment, the actual number of bad blocks may be determined for each individual memory device as discussed previously. In this embodiment, the number of blocks reserved in each memory device may differ depending on the number of actual bad memory blocks. As a result, the number of addressable memory locations may also differ for each of the memory devices.

To compensate for bad blocks within each memory device, the block and device addresses may be used as virtual addresses to lookup the actual addresses that compensate for bad blocks by skipping the bad blocks. Both the device address and the block address are used since the number and location of the bad blocks are likely to differ from memory device to memory device. In the embodiment illustrated in Figure 1, a lookup table 120 may receive the block address and the device address and output a corresponding modified block address for the particular memory device 110, thus mapping each available input block address, 0 to 3999, to a usable memory block within the particular memory device 110 corresponding to the device address.

One skilled in the art will recognize that there are a number of ways to implement a lookup table. In one embodiment, a NOR flash memory device may be used to implement the lookup tables of the present invention. NOR flash devices are non-volatile memory devices that do not have bad memory blocks, making them suitable for implementing a lookup table. Further, a lookup table implemented using a NOR flash device may be rewritten as additional bad blocks develop over time as discussed further herein. Other implementations for a lookup table are possible and are considered within the scope of the present invention.

Table 1 below illustrates part of a sample lookup table for a particular memory device. Lookup table 120 may include such a table for each memory device 11 OA-H. For each device, an input block address is associated with a corresponding modified block address. For ease of understanding, the input block addresses and the modified block addresses are displayed in base ten, rather than their 12-bit binary representation. However, in actual embodiments, each input and modified block address may be stored in binary form. For purposes of this example, the memory device has 96 bad blocks, including blocks 3 and 5.

Table 1

In this example, the modified block address is the same as the input block address for the first three input block addresses, 0, 1 and 2. This means that blocks 0, 1 and 2 are usable blocks within this memory device. However, input block address 3 is mapped to a modified block address of 4. This means that block 3 was a bad block which is skipped when performing a memory access. As a result, the modified block addresses for the remainder of input block addresses will be different from the input block addresses. As noted previously, this example assumes that the memory device has 96 bad blocks. As a result, the input block address 3999 maps to block 4095. Note, that if the memory device had fewer than 96 bad blocks, there would be reserved blocks that are unused.

One feature of the mapping depicted in this lookup table is that a modified block address is equal to the input block address, n, plus an offset, which represents the number of bad blocks found within the first n+1 blocks of the memory device. In other words, the offset represents the number of bad memory blocks between the first addressable memory location in the memory device and the memory block associated with the block address. For example, the input block address 5 is mapped to a modified block address 7. In this example, n = 5 and two bad blocks are found within the first 6 blocks, blocks 3 and 5. Thus, an offset of 2 must be added to n to obtain the modified block address. Because of this feature of the mapping depicted in lookup table illustrated in Table 1, the lookup table 120 may be simplified to reduce the amount of data that needs to be stored in the lookup table.

Figure 2 illustrates an alternative embodiment of the system and apparatus for addressing a memory device according to the invention that replaces lookup table 120 with a new lookup table 220 and an adder 230. Lookup table 220 is connected to one of the inputs to adder 230. Lookup table 220 receives a 12-bit block address and a device address as inputs. Lookup table 220 performs a lookup using these input addresses and outputs a corresponding 7-bit offset value to adder 230. Adder 230 receives the 12-bit block address at its second input and adds the 7-bit offset to the 12-bit block address received at its first input. The resulting 12-bits are the modified block address that is output to the memory devices 11 OA-H.

This embodiment reduces the amount of data stored in the lookup table since the lookup table stores a 7-bit offset value for each block address for each memory device, rather than a 12-bit modified block address. As discussed above, the block addresses are increased by an offset value in order to skip over the bad blocks. In the described example, a 7-bit offset is used to represent the 96 blocks reserved to handle a bad block. Thus, lookup table

220 includes a 7-bit offset value for each block address of each memory device. If a smaller or larger number of blocks are reserved to handle bad blocks, a different number of bits could be used to express the offset value that lookup table provides to adder 230. One skilled in the art will recognize that adder 230 may be implemented in a number of ways, including using off-the-shelf adders. However, as the number of input bits to an adder increases, the complexity and propagation delay of the adder increases. Thus, the embodiment of Figure 2 may be further improved upon by using two smaller adders to perform the same function as adder 230. Figure 3 illustrates an alternative embodiment of the system and apparatus for addressing a memory device according to the invention that includes two adders 330 and 340 and a lookup table 320. In this embodiment, lookup table 320 receives a 12-bit block address and a device address as inputs. Using these address values, lookup table 320 outputs a 7-bit offset value to adder 340 and also outputs a 1-bit carry bit to adder 330. hi addition to the 7- bit offset value, adder 340 receives the lower 7-bits of the block address as an input. Adder 340 adds the 7-bit offset value to the lower 7-bits of the block address and outputs the lower 7-bits of the 12-bit modified block address.

In some instances, adding the offset value to the lower 7-bits of the block address will result in a carry over condition, which occurs when adding the offset to the lower 7-bits of the block address exceeds the maximum number, 127 in base 10, capable of being represented as a 7-bit number. For example, suppose that five bad blocks are found between block addresses 0 and 126 in the memory device. When adding the offset value of five to the input memory address 126, the result is 131 in base 10. hi binary, 131 is represented as 10000011. This is an eight bit number, which can not be stored in the 7-bit modified address field of lookup table 320. Thus, the carry bit for this input address is set to one and the 7-bit modified

address field is set to 0000011.

Lookup table 320 handles these situations by outputting a carry over bit to adder 330. In one embodiment, lookup table 320 includes a carry over value for each block address of each memory device. If a carry over condition occurs, the carry over bit is one and if no carry over occurs, the carry over bit is zero. Adder 330 receives the carry bit and the upper 5 -bits of the block address as inputs, adds the carry bit to the upper block address bits and outputs the resulting upper 5-bits of the modified block address.

The embodiment of Figure 3 may be further improved by noticing that adder 340 receives two 7-bit inputs, adds them together and outputs a 7-bit output. Since lookup table 320 is already storing a 7-bit offset value corresponding to each block address of each memory device, the add operation performed by adder 340 may be predetermined and stored directly in the lookup table. This eliminates the need for adder 340, thus improving the speed and reducing the complexity of determining the modified block address. Figure 4 illustrates such an embodiment.

Figure 4 includes a lookup table 420 and an adder 430 that is coupled to receive a carry bit from lookup table 420. hi this embodiment, the add operations performed by adder 340 of Figure 3 have been predetermined and the 7-bit portions of the modified block addresses are stored directly in lookup table 420 for each corresponding input block address. In addition to the 7-bit portions of the modified block address, lookup table 420 may also include a carry bit corresponding to each input block address. As discussed above, a carry over condition occurs when adding the offset to the lower 7-bits of the input block address exceeds the maximum number, 127 in base 10, capable of being represented as a 7-bit number. The carry bit is output to adder 430 which adds the value of the carry bit to the upper five bits of the input block address to create the remainder of the modified block address.

Table 2 below is a visual representation of lookup table 420 according to one embodiment of the invention. For each block address of each memory device, a 7-bit value representing the lower 7-bits of the modified block address is stored in the lookup table 420 along with a carry bit. For ease of understanding, the device addresses, the input block addresses and the modified block addresses and the carry bit are displayed in base ten, rather than their binary representation. However, in the actual implementation, each input and modified block address would likely be stored in its binary form.

Table 2

The number of memory blocks and bad memory blocks used in the examples above are intended only as examples to help explain the invention. One skilled in the art will recognize that the invention is not limited to these examples. For example, if the number of reserved blocks increases or decreases, one skilled in the art will recognize that the number of bits representing the offset value may also increase or decrease. If 50 blocks are reserved in a particular memory device rather than 96, a 6-bit offset value would be sufficient to determine the modified block address. The 6-bits are needed in order to represent the 50 reserved blocks in binary.

As discussed previously, additional bad blocks may develop over time due to repetitively erasing, writing and reading to the memory device. In one embodiment of the invention, the contents of lookup tables 120, 220, 320 and 420 may be modified or completely replaced in response to the development of additional bad blocks. As additional bad blocks develop, the offset values for some or all of the input block addresses may change. To account for these changes, the entries in the lookup table may be updated by performing a write operation on the lookup table for each entry that needs to be updated. During each write operation, the address for the table entry is input to the lookup table and the corresponding updated table entry is input through the data bus of the lookup table.

While the present invention has been described with reference to certain embodiments, those skilled in the art will recognize that various modifications may be provided. The embodiments described above have been described using an example comprising a memory including eight distinct segments or memory devices that are being accessed. One skilled in the art will recognize that the invention is not limited to the number of distinct memory segments being accessed. The invention will work with any number of distinct memory segments or devices including one memory device having its storage locations organized into a number of separately addressable distinct memory segments, such as, for example, distinct memory partitions. In a partitioned memory, for example, the system and apparatus for addressing the memory could be arranged to compensate for the number and location of bad memory storage location addresses within the partitions of the memory.

Similarly, the present invention has been described using memory devices that contain a total of 4096 blocks with 4000 being accessible and 96 reserved to cover for bad blocks. These examples are used to help explain the invention and do not limit the scope of the invention. One skilled in the art will also recognize that there are a number of ways to implement the functionality of the lookup tables, adders and demultiplexers described above. Variations upon and modifications to the embodiments are provided for by the present invention.

Claims

What is claimed is:

1. A method for addressing a plurality of memory devices, each memory device having a plurality of addressable storage locations, comprising: receiving a device address which identifies one of the plurality of memory devices and a storage location address; and mapping the storage location address according to an offset value to create a modified storage location address, the offset value determined according to the number and location of bad storage locations within the one of the plurality of memory devices identified by the device address.

2. The method of claim 1 wherein the offset value represents the number of bad storage locations between a first addressable memory location and the storage location address of the one of the plurality of memory devices corresponding to the device address.

3. The method of claim 2 wherein mapping the storage location address according to an offset value to a modified storage location address comprises: adding the offset value associated with the storage location address to the storage location address to create the modified storage location address.

4. The method of claim 2 wherein mapping the storage location address according to an offset value to a modified storage location address comprises: adding the offset value associated with the storage location address to a portion of the storage location address to create a portion of the modified storage location address; and responsive to the addition of the offset value to the portion of the storage location address resulting in a carry over condition, adding a carry bit to a remainder of the storage location address to create a remainder of the modified storage location address.

5. A method for compensating for bad storage locations within a plurality of memory devices, comprising for each of the plurality of memory devices: determining a location of each bad storage location in the memory device; reserving within the memory device, a number of storage locations sufficient to compensate for each of the bad storage locations in the memory device; and mapping each storage location address of the memory device to a corresponding modified storage location address relative to the location of each of the bad storage locations in the memory device.

6. The method of claim 5 wherein mapping comprises: creating a lookup table comprising an entry for each storage location address of the memory device, wherein the lookup table outputs the modified storage location address corresponding to the storage location address upon receiving the storage location address as an input.

7. The method of claim 6, further comprising the step of: updating at least one entry in the lookup table responsive to a new bad storage location developing after the initial creation of the lookup table.

8. An apparatus for addressing a plurality of memory devices, each memory device having a plurality of addressable storage locations, comprising: an address mapping device for receiving a device address and a storage location address and outputting a corresponding modified storage location address, wherein the modified storage location address compensates for the number and location of bad storage locations in the one of the plurality of memory devices corresponding to the device address.

9. The apparatus of claim 8 further comprising: a memory device selector for receiving the device address and activating the one of the plurality of memory devices corresponding to the device address.

10. The apparatus of claim 9 wherein the memory device selector is a demultiplexer.

11. The apparatus of claim 8 wherein the address mapping device is a lookup table that maps each storage location address of each of the plurality of memory devices to a corresponding modified storage location address.

12. The apparatus of claim 11 wherein at least one modified storage location address in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

13. The apparatus of claim 8 wherein the modified storage location address is the storage location address plus an offset value representing the number of bad storage locations between a first addressable memory location and the storage location address of the one of the plurality of memory devices corresponding to the device address.

14. The apparatus of claim 8 wherein the address mapping device comprises: a lookup table that maps a storage location address for the one of the plurality of memory devices corresponding to the device address to an offset value, the offset value corresponding to the number of bad storage locations between a first addressable memory location and the storage location address of the one of the plurality of memory devices corresponding to the device address; and an adder for receiving the offset value from the lookup table and the storage location address and adding the offset value to the storage location address to create the modified storage location address.

15. The apparatus of claim 14 wherein at least one offset value in the lookup table s updated responsive to a formerly usable storage location becoming a bad storage location.

16. The apparatus of claim 8 wherein the address mapping device comprises: a lookup table that maps the storage location address for the one of the plurality of memory devices corresponding to the device address to a portion of the modified storage location address, the portion of the modified storage location address being a portion of the storage location address plus an offset value, the offset value representing the number of bad storage locations between a first addressable memory location and the storage location address of the one of the plurality of memory devices corresponding to the device address; and an adder for adding a carry bit to a remainder of the storage location address to create a remainder of the modified storage location address responsive to the addition of the offset value to the portion of the storage location address resulting in a carry over condition.

17. The apparatus of claim 16 wherein at least one portion of a modified storage location address in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

18. An apparatus for addressing a plurality of memory devices, each memory device having a plurality of addressable storage locations, one or more of which could be bad, comprising: means for receiving a device address and a storage location address and outputting a corresponding modified storage location address, wherein the modified storage location address compensates for the number and location of bad storage locations in the one of the plurality of memory devices corresponding to the device address; and means for receiving the device address and selecting the one of the plurality of memory devices corresponding to the device address.

19. A memory, comprising: a plurality of memory segments, each having a plurality of addressable storage locations; and an address mapping device for receiving a segment address identifying one of the plurality of memory segments and a storage location address identifying a first storage location and outputting a corresponding modified storage location address identifying a second storage location, wherein the modified storage location address compensates for the number and location of bad storage locations in the one of the plurality of memory segments identified by the received segment address.

20. The memory of claim 19 wherein the address mapping device is a lookup table that maps each storage location address of each of the plurality of memory segments to a corresponding modified storage location address.

21. The memory of claim 20 wherein at least one modified storage location address in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

22. The memory of claim 19 wherein the modified storage location address is the storage location address plus an offset value representing the number of bad storage locations between a first addressable memory location and the storage location address of the one of the plurality of memory segments corresponding to the segment address.

23. The memory of claim 19 wherein the address mapping device comprises: a lookup table that maps a storage location address for the one of the plurality of memory segments to an offset value, the offset value corresponding to the number of bad storage locations between a first addressable memory location and the first storage location of the memory segment identified by the segment address; and an adder for receiving the offset value and the storage location address and adding the offset value to the storage location address to create the modified storage location address.

24. The memory of claim 23 wherein the at least one offset value in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

25. The memory of claim 19 wherein the address mapping device comprises: a lookup table that maps the storage location address to a portion of the modified storage location address, the portion of the modified storage location address being a portion of the storage location address plus an offset value, the offset value representing the number of bad storage locations between a first addressable memory location and the first storage location of the memory segment identified by the segment address; and an adder for adding a carry bit to a remainder of the storage location address to create a remainder of the modified storage location address responsive to the addition of the offset value to the portion of the storage location address resulting in a carry over condition.

26. The memory of claim 25 wherein at least one portion of a modified storage location address in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

27. A method for addressing a plurality of memory _ segments, each memory segment having a plurality of addressable storage locations, comprising: receiving a segment address identifying one of the plurality of memory segments and a storage location address identifying a first storage location; and mapping the storage location address according to an offset value to create a modified storage location address identifying a second storage location, the offset value determined according to the number and location of bad storage locations within the memory segment identified by the segment address.

28. The method of claim 27 wherein the offset value represents the number of bad storage locations between a first addressable memory location of the memory segment and the first storage location of the memory segment.

29. The method of claim 28 wherein mapping the storage location address according to an offset value to a modified storage location address comprises: adding the offset Value associated with the storage location address to the storage location address to create the modified storage location address.

30. The method of claim 28 wherein mapping the storage location address according to an offset value to a modified storage location address comprises: adding the offset value associated with the storage location address to a portion of the storage location address to create a portion of the modified storage location address; and responsive to the addition of the offset value to the portion of the storage location address resulting in a carry over condition, adding a carry bit to a remainder of the storage location address to create a remainder of the modified storage location address.

31. A memory, comprising: a plurality of memory devices, each memory device having a plurality of addressable storage locations; an address mapping device for receiving a device address identifying a memory device and a storage location address identifying a first storage location and outputting a corresponding modified storage location address identifying a second storage location, wherein the modified storage location address compensates for the number and location of bad storage locations in the memory device identified by the received device address.

32. The memory of claim 31 wherein the address mapping device is a lookup table that maps each storage location address of each of the plurality of memory devices to a corresponding modified storage location address.

33. The memory of claim 32 wherein at least one modified storage location address in the lookup table is updated responsive to a formerly usable storage location becoming a bad storage location.

34. The memory of claim 31 wherein the modified storage location address is the storage location address plus an offset value representing the number of bad storage locations between a first addressable memory location and the first storage location of the memory device identified by the device address.

35. The memory of claim 31 wherein the address mapping device comprises: a lookup table that maps a storage location address for the one of the plurality of memory devices identified by the device address to an offset value, the offset value corresponding to the number of bad storage locations between a first addressable memory location and the first storage location of the memory device identified by the device address; and an adder for receiving the offset value from the lookup table and the storage location address and adding the offset value to the storage location address to create the modified storage location address.

36. The memory of claim 31 wherein the address mapping device comprises: a lookup table that maps the storage location address for the one of the plurality of memory devices identified by the device address to a portion of the modified storage location address, the portion of the modified storage location address being a portion of the storage location address plus an offset value, the offset value representing the number of bad storage locations between a first addressable memory location and the first storage location of the memory device identified by the device address; and an adder for adding a carry bit to a remainder of the storage location address to create a remainder of the modified storage location address responsive to the addition of the offset value to the portion of the storage location address resulting in a carry over condition.

37. A method for accessing a memory having a plurality of memory devices, each having a plurality of addressable storage locations, comprising: receiving a device address corresponding to one of the plurality of memory devices and a storage location address for effecting a data transfer; mapping the storage location address according to an offset value to a modified storage location address, the offset value determined according to the number and location of bad storage locations within the one of the plurality of memory devices identified by the received device address; and transferring data relative to the storage location identified by the received device address and the modified storage location address.

38. The method of claim 37 wherein the transferring step includes the step of storing data during a write access of the memory at the storage location identified by the modified storage location address and the received device address.

39. The method of claim 37 wherein the transferring step includes the step, of reading data during a read access of the memory at the storage location identified by the modified storage location address and the received device address: