WO2006081092A3 - Deterministic microcontroller with configurable input/output interface - Google Patents

Deterministic microcontroller with configurable input/output interface Download PDF

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Publication number
WO2006081092A3
WO2006081092A3 PCT/US2006/001573 US2006001573W WO2006081092A3 WO 2006081092 A3 WO2006081092 A3 WO 2006081092A3 US 2006001573 W US2006001573 W US 2006001573W WO 2006081092 A3 WO2006081092 A3 WO 2006081092A3
Authority
WO
WIPO (PCT)
Prior art keywords
output interface
deterministic
hardware
contexts
microcontroller
Prior art date
Application number
PCT/US2006/001573
Other languages
French (fr)
Other versions
WO2006081092A2 (en
Inventor
Andrew David Alsup
Taylor Wray
Original Assignee
Innovasic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/259,420 external-priority patent/US7516311B2/en
Priority claimed from US11/258,822 external-priority patent/US7562207B2/en
Priority claimed from US11/259,741 external-priority patent/US20060168420A1/en
Priority claimed from US11/259,755 external-priority patent/US20060168421A1/en
Application filed by Innovasic Inc filed Critical Innovasic Inc
Publication of WO2006081092A2 publication Critical patent/WO2006081092A2/en
Publication of WO2006081092A3 publication Critical patent/WO2006081092A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers

Abstract

A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.
PCT/US2006/001573 2005-01-27 2006-01-18 Deterministic microcontroller with configurable input/output interface WO2006081092A2 (en)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US64813805P 2005-01-27 2005-01-27
US60/648,138 2005-01-27
US11/259,420 US7516311B2 (en) 2005-01-27 2005-10-26 Deterministic microcontroller context arrangement
US11/259,741 2005-10-26
US11/259,755 2005-10-26
US11/258,822 US7562207B2 (en) 2005-01-27 2005-10-26 Deterministic microcontroller with context manager
US11/259,420 2005-10-26
US11/259,741 US20060168420A1 (en) 2005-01-27 2005-10-26 Microcontroller cache memory
US11/258,822 2005-10-26
US11/259,755 US20060168421A1 (en) 2005-01-27 2005-10-26 Method of providing microcontroller cache memory

Publications (2)

Publication Number Publication Date
WO2006081092A2 WO2006081092A2 (en) 2006-08-03
WO2006081092A3 true WO2006081092A3 (en) 2007-10-25

Family

ID=36740953

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2006/001573 WO2006081092A2 (en) 2005-01-27 2006-01-18 Deterministic microcontroller with configurable input/output interface
PCT/US2006/001575 WO2006081094A2 (en) 2005-01-27 2006-01-18 Deterministic microcontroller
PCT/US2006/001574 WO2006081093A2 (en) 2005-01-27 2006-01-18 Configurable application specific standard product with configurable i/o

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2006/001575 WO2006081094A2 (en) 2005-01-27 2006-01-18 Deterministic microcontroller
PCT/US2006/001574 WO2006081093A2 (en) 2005-01-27 2006-01-18 Configurable application specific standard product with configurable i/o

Country Status (1)

Country Link
WO (3) WO2006081092A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11086623B2 (en) 2017-03-20 2021-08-10 Intel Corporation Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US11275588B2 (en) 2017-07-01 2022-03-15 Intel Corporation Context save with variable save state size
CN112860444B (en) * 2021-04-26 2021-08-20 腾讯科技（深圳）有限公司 Memory calling information determining method and device, storage medium and electronic equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context
US6553487B1 (en) * 2000-01-07 2003-04-22 Motorola, Inc. Device and method for performing high-speed low overhead context switch

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305446A (en) * 1990-09-28 1994-04-19 Texas Instruments Incorporated Processing devices with improved addressing capabilities, systems and methods
US5426769A (en) * 1993-08-26 1995-06-20 Metalink Corp. System and method for producing input/output expansion for single chip microcomputers
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US6401154B1 (en) * 2000-05-05 2002-06-04 Advanced Micro Devices, Inc. Flexible architecture for an embedded interrupt controller
US20030195989A1 (en) * 2001-07-02 2003-10-16 Globespan Virata Incorporated Communications system using rings architecture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context
US6553487B1 (en) * 2000-01-07 2003-04-22 Motorola, Inc. Device and method for performing high-speed low overhead context switch

Also Published As

Publication number Publication date
WO2006081094A3 (en) 2009-04-09
WO2006081093A2 (en) 2006-08-03
WO2006081094A2 (en) 2006-08-03
WO2006081093A3 (en) 2007-05-24
WO2006081092A2 (en) 2006-08-03

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