WO2006066211A2 - Active and passive semiconductor device package - Google Patents
Active and passive semiconductor device package Download PDFInfo
- Publication number
- WO2006066211A2 WO2006066211A2 PCT/US2005/045939 US2005045939W WO2006066211A2 WO 2006066211 A2 WO2006066211 A2 WO 2006066211A2 US 2005045939 W US2005045939 W US 2005045939W WO 2006066211 A2 WO2006066211 A2 WO 2006066211A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- components
- substrate
- package
- integrated circuit
- passive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/759—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent discrete passive device
Definitions
- This invention relates generally to the field of semiconductor devices and, more particularly, to a package that integrates passive and active devices with or without a lead frame.
- a packaged integrated circuit may generally include semiconductor chips and their associated components embedded within a molding.
- the packaged integrated circuits may be connected to a printed circuit board of an electronic device. Through the printed circuit board, the packaged integrated circuit may be connected to other chips and to external inputs and outputs.
- a component package comprises a plurality of components and mold compound.
- the plurality of components is disposed on a zero plane of a removable substrate.
- the removal substrate is operable to hold the plurality of components in position.
- At least one of the plurality of components is wire bonded to at least another of the plurality of components with a wire bond.
- the mold compound is disposed around the plurality of components, encapsulating the plurality of components. A portion of the plurality of the components disposed upon the zero plane of the removable substrate are exposed upon removal of the substrate from the component package.
- a technical advantage of one embodiment may include the capability to reduce space requirements for a design with passives.
- FIG. IA show an isometric view of a package portion, according to an embodiment of the invention
- FIG. IB shows a passive component with a wire bond termination, according to an embodiment of the invention
- FIG. 1C shows a top cut away view of a package after a molding process of the package portion of FIG. IA, according to an embodiment of the invention
- FIG. ID shows a bottom view of the package of FIG. 1C with a substrate removed, according to an embodiment of the invention
- FIG. IE shows a board layout, complementary to the package of FIG. ID, according to an embodiment of the invention
- FIG. 2A shows an isometric view of a package portion, according to another embodiment of the invention.
- FIG. 2B shows a top cut away view of a package after a molding process of the package portion of FIG. 2A, according to an embodiment of the invention
- FIG. 2C shows a bottom view of the package of FIG. 2B with the substrate removed, according to an embodiment of the invention
- FIG. 2D shows a board layout, complementary to the package of FIG. 2C, according to an embodiment of the invention
- FIG. 3 A shows an isometric view of a package portion, according to yet another embodiment of the invention.
- FIG. 3B shows a top cut away view of a package after a molding process of the package portion of FIG. 3A, according to another embodiment of the invention
- FIG. 3C shows a bottom view of the package of FIG. 3B with the substrate removed, according to another embodiment of the invention.
- FIG. 3D shows a board layout, complementary to the package of FIG. 3C, according to an embodiment of the invention
- FIG. 4A shows an isometric view of a package portion, according to yet another embodiment of the invention
- FIG. 4B shows a bottom view of a package after a molding process of the package portion of FIG. 4A and removal of the substrate, according to an embodiment of the invention
- FIG. 4C shows a board layout, complementary to the package of FIG. 4B, according to an embodiment of the invention.
- teachings of some embodiments of the invention recognize configurations that integrate passive components in a mold compound in a manner that allows passive components terminations to be used as an attachment means instead of an intermediate lead frame, thereby reducing and/or eliminating the critical passives for the board designer to layout. Teaching of some embodiments of the invention additionally recognize configurations that reduce the total "real estate" on a board.
- FIG. IA show an isometric view of a package portion 205, according to an embodiment of the invention.
- the package portion 205 of FIG. IA includes a plurality of components 210.
- the plurality of components 210 are shown disposed on top of a substrate 190.
- the substrate 190 may be a polyimide-based adhesive or tape operable to hold the component 210 in place and to withstand operating temperatures. "Withstanding operating temperatures” may generally refer to an ability of the substrate 190 to hold the components in place 210 during an operation in which the substrate 190 will be utilized.
- the substrate 190 may hold the components 210 in place during an injection molding process, described in further details below.
- a suitable adhesive or tape is Kapton® tape.
- Kapton® tape has been described as a suitable substrate 190, other embodiments may utilize other suitable substrates 190 operable to hold components 210 in place and withstand operating temperatures.
- the substrate 190 creates a substantially planar surface upon which the components 210 are disposed. Accordingly, the substrate 190 may be considered the zero plane and the components 210, thus, are all positioned on the zero plane. With such a configuration, a vertical height in a package 200 may be reduced.
- the components 210 in the embodiment of FIG. IA are passive components 30 and a die or integrated circuit 20.
- the passive components 30 may include, but are not limited to capacitors, inductors, and resistors.
- the integrated circuit 20, alone or in combination with the passive components 30, may include a variety of different features, including, but not limited to, analog and/or digital circuits such as digital to analog converters, computer processor units, amplifiers, digital signal processors, controllers, transistors, or other semiconductor features.
- the integrated circuit 20 may comprise a variety of materials including silicon, gallium arsenide, or other suitable materials.
- the passive components have a wire bond 40 positioned therebetween. Accordingly, the passive components 30 include a wire bond termination 35 as shown in FIG. IB.
- the package portion 205 may be forwarded to a wire bonding process that places the wire bonds 40 between the components 210. Then, the package portion 205 may be forwarded to a molding process to place molding 50 (not explicitly shown) around the components 210 in order to form a package 200 as shown in FIG. 1C.
- a molding process is an injection molding process. However, other suitable molding process may be utilized to place mold compound 50 around the components 210.
- FIG. 1C shows a top cut away view of a package 400 after a molding process of the package portion 405 of FIG. IA, according to an embodiment of the invention
- a mold compound 50 generally surrounds and holds the integrated circuit 20, passive components 30, and the wire bonds 40 in position. Accordingly, after the molding process, the substrate 190 may be removed, exposing the integrated circuit 20 and passive components 30 as shown in FIG. ID.
- Any suitable mold compound operable to encapsulate components 210 may be utilized. Examples include, but are not limited to, a "green" mold compound that does not contain bromine (Br) or antimony (Sb). Although such mold compounds have been described, other suitable mold compounds operable to hold the components 210 in place may be utilized.
- a plurality of packages 200 may be coupled to one another, during processing, and separated from one another after processing, using suitable separation processes, including, but not limited to, sawing or punching.
- the package 200 as shown in FIG. 1C may includes a pull back feature - that is, placement of components 210 at a distance from an edge 220 of the package 200. Such a pull back features helps ensure that the components 210 will not become damages during separation of the packages 200.
- FIG. ID shows a bottom view of the package 200 of FIG. 1C with the substrate 190 removed, according to an embodiment of the invention. With the substrate 190 removed, the components 210 are all exposed at the zero plane.
- a metal may be placed on a backside 22 of the integrated circuit 20 to facilitate a soldering or other suitable coupling process.
- an insulation material may be placed on the backside 22 of the integrated circuit 20 to facilitate configurations in which insulation may be desired.
- FIG. IE shows a board layout 60, complementary to the package 200 of FIG. ID, according to an embodiment of the invention. Portions 62 of the board layout 60
- FIG. 2A shows an isometric view of a package portion 305, according to another embodiment of the invention.
- the package portion 305 includes components 310.
- Components 310 may include similar or different components than the components 210 shown in FIG. IA.
- the components 310 are shown as an integrated circuit 20, passive components 30, and bond pads 80. To facilitate communication amongst the components 310, wire bonds 40 are positioned therebetween.
- wire bonds 40 are shown between the integrated circuit 20 and a bond pad 80 and between the integrated circuit 20 and a passive component 30.
- the components 310 and a lead frame 110 are positioned on top of a substrate 190, which may be made of similar or different materials than the substrate 190 described with reference to FIG. IA.
- the package portion 305 may be packaged into a package 300 in a similar manner to that described above with reference to FIG. IA ⁇ that is, placing the components 310 on the substrate 190, wire bonding the components 310 in the applicable locations, placing molding around the components 310, and separating the package 300 from other packages when the packages are assembled in a group.
- FIG. 2B shows a top cut away view of a package 300 after a molding process of the package portion 305 of FIG. 2 A, according to an embodiment of the invention.
- the package 300 may be a package separated from an assembly of multiple packages as described above.
- a mold compound 50 surrounds and holds the integrated circuit 20, passive components 30, pads 80, and wire bonds 40 in position.
- the substrate 190 may be removed, exposing the integrated circuit 20, passive components 30, and pads 80 as shown in FIG. 2C.
- the mold compound 50 may be made of any suitable material operable to hold the components 310 in position.
- the package 300 may include a pull back feature.
- FIG. 2C shows a bottom view of the package 300 of FIG. 2B with the substrate 190 removed, according to an embodiment of the invention. With the substrate 190 removed, the components 210 are all exposed at the zero plane. Similar to that described with reference to FIG. ID, a metal may be placed on a backside 22 of the integrated circuit 20 to facilitate a soldering or other suitable coupling process. Alternatively, an insulation material may be placed on the backside 22 of the integrated circuit 20 to facilitate configurations in which insulation may be desired.
- FIG. 2D shows a board layout 80, complementary to the package 300 of FIG. 2C, according to an embodiment of the invention.
- Portions 82 of the board layout 80 correspond to the passive components 30, portion 84 of the board layout 80 corresponds to the integrated circuit 20, and portions 86 of the board layout 80 correspond to the bond pads 80. Similar to that described above with reference to FIG. IE, a variety of techniques may be utilized to establish communication between the package 300 and the board layout 80, including, but not limited to soldering. Additionally, in some embodiments the substrate 190 may be retained for shipping and removed upon arrival at a location at which the package 300 is installed on the board layout 80.
- FIG. 3A shows an isometric view of a package portion 405, according to yet another embodiment of the invention. In this embodiment, the package portion 405 includes components 410. Components 410 may include similar or different components than the components 210 shown in FIG. IA. In this embodiment, the components 410 are shown as a passive component 90, passive components 30, and an integrated circuit 100.
- the passive component 90 may be similar or different than passive components 30.
- passive components 90 may include wire bond terminations 95.
- the integrated circuit 100 may be coupled to the top of the passive component 90.
- the integrated circuit 100 may be attached to the top of the passive component 90, utilizing a variety of attachment mediums, including epoxy, polyimide, other adhesive chemistries, mixture of such chemistries, solder, a gold-silicon Eutectic layer, or other suitable material and/or materials for bonding the integrated circuit 100 to the passive component 90.
- wire bonds 40 are positioned therebetween. For example, wire bonds 40 are shown between the integrated circuit 100 and the passive component 30 and between the passive component 90 and the integrated circuit 40.
- the passive component 90 and the passive components 30 are positioned on top of a substrate 190, which may be made of similar or different materials than that described with reference to FIGS. IA.
- the package portion 405 may be packaged into a package 400 in a similar manner to that described above with reference to FIGS. IA and 2 A ⁇ that is, placing the components 410 on the substrate 190 and/or on top of one another (e.g., placing the integrated circuit 100 on the passive component 90 using techniques described above or other suitable techniques), wire bonding the components 410 in the applicable locations, placing molding around the components 410, and separating the package 400 from other packages when the packages are assembled in a group.
- FIG. 3B shows a top cut away view of a package 400 after a molding process of the package portion 405 of FIG. 3A, according to another embodiment of the invention.
- the package 400 may be a package separated from an assembly of multiple packages as described above.
- a mold compound 50 surrounds and holds the integrated circuit 100, passive components 30, and passive component 90 in position.
- the substrate 190 may be removed, exposing the passive components 30 and passive component 90 as shown in FIG. 3C.
- FIG. 3C shows a bottom view of the package 400 of FIG. 3B with the substrate 190 removed, according to another embodiment of the invention. With the substrate 190 removed, the components passive components 30 and passive component 90 are exposed at the zero plane. Similar to that described with reference to FIG. 1C, a metal may be placed on a backside 22 of the integrated circuit 20 to facilitate a soldering or other suitable coupling process. Alternatively, an insulation material may be placed on the backside 22 of the integrated circuit 20 to facilitate configurations in which insulation may be desired.
- FIG. 3D shows a board layout 120, complementary to the package 400 of FIG. 3C, according to an embodiment of the invention.
- Portions 122 of the board layout 120 corresponds to the passive component 90 and portion 124 of the board layout 120 corresponds to the passive components 30.
- a variety of techniques may be utilized to establish communication between the package 400 and the board layout 120, including, but not limited to soldering.
- the substrate 190 may be retained for shipping and removed upon arrival at a location at which the package 400 is installed on the board layout 120.
- FIG. 4A shows an isometric view of a package portion 505, according to yet another embodiment of the invention.
- the package portion 505 includes components 510.
- Components 510 may include similar or different components than the components 510 shown in FIG. 3 A.
- the components 510 are shown as a passive component 90, passive components 30, an integrated circuit 100, and bond pads 80.
- wire bonds 40 are positioned therebetween.
- wire bonds 40 are shown between the integrated circuit 100 and passive component 30, between the passive component 90 and the integrated circuit 40. Similar to that described above with reference to FIGS.
- the integrated circuit 100 may be attached to the top of the passive component 90 and the passive component 90, passive components 30, bond pads 80, and a lead frame 110 are positioned on top of a substrate 190, which may be made of similar or different materials than that described with reference to FIGS. IA.
- the package portion 505 may be packaged into a package 500 in a similar manner to that described above with reference to FIGS.
- IA, 2A, and 3 A that is, placing the components 510 on the substrate 190 and/or on top of one another (e.g., placing the integrated circuit 100 on the passive component 90 using techniques described above or other suitable techniques), wire bonding the components 510 in the applicable locations, placing molding around the components 510, and separating the package 500 from other packages when the packages are assembled in a group.
- FIG. 4B shows a bottom view of the package 500 after a molding process of the package portion 505 of FIG. 4A and removal of the substrate 190, according to an embodiment of the invention.
- the package 500 may be a package separated from an assembly of multiple packages as described above.
- a mold compound 50 surrounds and holds the integrated circuit 100, passive components 30, passive component 90, and bond pads 80 in position. Similar to that described with reference to FIG. IA, the mold compound 50 may be made of any suitable material operable to hold the components 510 in position. Additionally, the package 500 may include a pull back feature.
- the substrate 190 may be removed, exposing the passive components 30, passive component 90, and bond pads 80 at the zero plane.
- FIG. 4C shows a board layout 160, complementary to the package 500 of FIG. 4B, according to an embodiment of the invention.
- Portions 162 of the board layout 160 correspond to the passive component 90
- portions 164 of the board layout 160 correspond to the passive components 30, and portions 166 of the board layout 160 correspond to the bond pads 80.
- a variety of techniques may be utilized to establish communication between the package 500 and the board layout 160, including, but not limited to soldering.
- the substrate 190 may be retained for shipping and removed upon arrival at a location at which the package 500 is installed on the board layout 160.
- components have been described have been described above with reference to FIGS. 1A-4C as passive components and integrated circuits, other components may additionally be incorporated into the package.
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007547003A JP2008524859A (en) | 2004-12-17 | 2005-12-19 | Active and passive semiconductor device packages |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63747904P | 2004-12-17 | 2004-12-17 | |
| US60/637,479 | 2004-12-17 | ||
| US11/132,577 | 2005-05-18 | ||
| US11/132,577 US20060134828A1 (en) | 2004-12-17 | 2005-05-18 | Package that integrates passive and active devices with or without a lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2006066211A2 true WO2006066211A2 (en) | 2006-06-22 |
| WO2006066211A3 WO2006066211A3 (en) | 2007-03-01 |
Family
ID=36588634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2005/045939 Ceased WO2006066211A2 (en) | 2004-12-17 | 2005-12-19 | Active and passive semiconductor device package |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20060134828A1 (en) |
| JP (1) | JP2008524859A (en) |
| TW (1) | TW200629517A (en) |
| WO (1) | WO2006066211A2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
| US9147664B2 (en) | 2013-10-11 | 2015-09-29 | Mediatek Inc. | Semiconductor package |
| US9806053B2 (en) | 2013-10-11 | 2017-10-31 | Mediatek Inc. | Semiconductor package |
| US9392696B2 (en) | 2013-10-11 | 2016-07-12 | Mediatek Inc. | Semiconductor package |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
| US5894108A (en) * | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
| DE10144462C1 (en) * | 2001-09-10 | 2002-11-28 | Infineon Technologies Ag | Electronic component used as a semiconductor component comprises a passive component, and a semiconductor chip electrically connected to a wiring structure |
| US6879034B1 (en) * | 2003-05-01 | 2005-04-12 | Amkor Technology, Inc. | Semiconductor package including low temperature co-fired ceramic substrate |
| US7205178B2 (en) * | 2004-03-24 | 2007-04-17 | Freescale Semiconductor, Inc. | Land grid array packaged device and method of forming same |
-
2005
- 2005-05-18 US US11/132,577 patent/US20060134828A1/en not_active Abandoned
- 2005-12-19 JP JP2007547003A patent/JP2008524859A/en not_active Abandoned
- 2005-12-19 TW TW094145142A patent/TW200629517A/en unknown
- 2005-12-19 WO PCT/US2005/045939 patent/WO2006066211A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20060134828A1 (en) | 2006-06-22 |
| TW200629517A (en) | 2006-08-16 |
| JP2008524859A (en) | 2008-07-10 |
| WO2006066211A3 (en) | 2007-03-01 |
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