WO2006050439A2

WO2006050439A2 - Multichip semiconductor package

Info

Publication number: WO2006050439A2
Application number: PCT/US2005/039684
Authority: WO
Inventors: Akira Matsunami
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2004-11-01
Filing date: 2005-11-01
Publication date: 2006-05-11
Anticipated expiration: 2007-05-01
Also published as: US20060091516A1; WO2006050439A3

Abstract

A multichip semiconductor device has first and second semiconductor assemblies superposed in fixed vertically stacked relationship within a common package encapsulation (131). The first assembly has a chip (101) mounted on first leadframe (103, 104) presenting externally accessible input/output lead contacts (104). The second assembly has a chip (110) mounted on a second leadframe (114) presenting externally accessible input/output lead contacts (114a) outwardly of the first assembly contacts. In one embodiment, bond pads (102) of the first ship (101) face bond pads (112) of the second chip (110), and bond wires (106, 116) to each leadframe extend into a gap between the chips. Encapsulation material (130) fills the gap. Lead contacts (114) of the second leadframe may have extending lead portions with ends formed coplanar with the first leads (104).

Description

MULTICHIP SEMICONDUCTOR PACKAGE

The present invention relates to integrated circuit semiconductor device package apparatus and methods; and, in particular, to apparatus and methods for multiple integrated circuit chips in a single package. BACKGROUND

It is advantageous for many applications of semiconductor devices to arrange the needed devices in close proximity. When only two, or few more, semiconductor chips are needed, various arrangements have been proposed to achieve the desired proximity, and to enable a minimization of required space. Typically, these arrangements are planar assemblies of semiconductor chips on a substrate, with or without a specific encapsulation. For these arrangements, the term "multichip module" is commonly used. For an encapsulated assembly, the term "multichip package" is used. For many years, there has been a limited market for multichip modules and multichip packages, but driven by the expansion of integrated circuit applications into small, often handheld, products, this market is growing.

Numerous multichip packages are described in publications and patents. For the most part, the chips are assembled side by side on a planar substrate and interconnected by means of this substrate. Such side-by-side arrangements are, however, take up more board area than arrangements in which the chips are superposed in vertical stacked configurations. In many current vertically stacked proposals, though, the chips are interconnected by techniques that are not cost-effective in fabrication (beam lead technology, tape automated bonding, multi¬ level substrates, etc.). Moreover, their interconnections typically present pin-out limitations.

A number of multichip arrangements are described in Venkateshwaran et al. U.S. Patent No. 6,316,822, issued November 13, 2001, entitled "Multichip Assembly Semiconductor." The embodiments show vertically stacked, superposed chips with connections to a common, single leadframe structure. Such arrangements do not give a high package pin density. Next to small package area, the potential for a high number of different input/output connections is, however, an important product consideration for multichip assemblies. Other multichip arrangements are described in Watanabe et al. U.S. Patent No. 5,910,685, issued June 8, 1999, entitled "Semiconductor Memory Module Having Double- Sided Stacked Memory Chip Layout." This patent shows vertically stacked chip arrangements with overlying chip structures that have separate lead patterns, that connect for common attachment to a mounting base plate. Again, the lead pattern arrangements provide limited pin densities and limited input/output possibilities.

There is, thus, a need for a multichip package which provides increased input/output possibilities in a space efficient way, and for methods to fabricate such multichip packages in straightforward, inexpensive ways. SUMMARY

In one aspect of the invention, a multichip semiconductor device is provided having superposed first and second semiconductor assemblies within a common encapsulation. In one form, a first semiconductor assembly has a chip with a surface including bond pads, and a leadframe. The chip is attached to the leadframe and the bond pads are respectively electrically conductively connected to leads of the leadframe. Similarly, a second semiconductor assembly has a second chip with a surface including bond pads, and a second leadframe. The second chip is attached to the second leadframe and the bond pads of the second chip are respectively electrically conductively connected to leads of the second leadframe. The second assembly is vertically superposed with the first assembly, and a package outline is defined by encapsulation material which is formed about the two assemblies to fixing their relative positions.

The connections between the leads and the bond pads may be established in the multichip device through wire bonds. In one example, the first leadframe has a leadless leadframe configuration and the second leadframe has a leaded leadframe configuration. The assemblies may be oriented so that the bond pad surfaces of the first and second chips face one another, the wire bond loops being located within the gap spacing the two facing surfaces. The leads of the first and second leadframes may be configured to have exposed portions which are coplanar.

In a modified form, the device may have the package outline formed by the encapsulation material so that at least a portion of the second chip is exposed, and a heat sink may be attached to the exposed portion. The first leadframe may include a chip mount, with the first chip attached to the chip mount; and the package outline may be formed to leave a portion of the chip mount exposed. A second heat sink may then be attached to the exposed portion of the first leadframe chip mount. In another aspect of the invention, a method of making a multichip semiconductor device is provided.

A first semiconductor assembly is formed by providing a first chip having a surface including bond pads, and a first leadframe. The first chip is attached to the first leadframe and the bond pads are respectively electrically conductively connected to leads of thie first leadframe. A second semiconductor assembly is formed by providing a second chip having a surface including bond pads, and a second leadframe. The second chip is attached to the second leadframe and the bond pads are respectively electrically conductively connected to leads of the second leadframe. The first and second assemblies are placed in vertically superposed positions; and a package outline is formed about the superposed chips, to fix relative positions of the first and second assemblies with an encapsulation material.

The superposition of the first and second assemblies may be achieved during the loading process of the mold cavity, especially for devices having the first assembly using a leadframe of the leadless category. After the molding step, the forming of the leads of the second leadframe provides lead ends coplanar with the leadless leadframe of the first assembly, resulting in a multichip device suitable for an area-conserving attachment to external parts. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross section of a multichip semiconductor device according to an embodiment of apparatus aspects of the invention.

FIG. 2 is a top view of a mount surface for attachment of a multichip device of the type shown in FIG. 1.

FIG. 3 is a schematic cross section of a multichip semiconductor device according to a modified form of the embodiment of FIG. 1. FIGS. 4A and 4B illustrate process steps for fabricating a first semiconductor integrated circuit assembly of a multichip semiconductor device embodiment of FIGS. 1 or 3, according to an embodiment of method aspects of the invention.

FIGS. 5 A and 5B illustrate process steps for fabricating a second assembly of the multichip semiconductor device. FIG. 6 illustrates process steps for the stacking and encapsulation of the first and second assemblies of FIGS. 4A, 4B, 5 A and 5B. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1 shows an example embodiment of a multichip semiconductor device 100, in accordance with the principles of the invention.

The device 100 comprises a stacked arrangement of two semiconductor integrated circuit chip assemblies, presented in a common package. The first assembly comprises a first integrated circuit chip 101, which has a first surface 101a and a plurality of bond pads 1O2. The first assembly further has a first leadframe comprising a chip mount pad 103 and a plurality of leads 104. In the example of FIG. 1, leads 104 are configured as metal pieces shaped for a leadframe designed for a so-called "leadless device" (such as commercially used in quad flat no lead packages which have no lead portions extending outwardly from the encapsulation outline of the package). Leads 104 provide the input/output terminals for the first semiconductor assembly and may be attached to external parts (for example, by pressure contact or by soldering to an underlying portion of a printed circuit board). For the given leadless configuration example, leads 104 are advantageously presented coplanar with a planar base of an encapsulation of a package of the device 100.

For typical implementations, chip 101 may be made of silicon. Alternative implementations may include silicon germanium, gallium arsenide or other semiconductor materials. A typical current chip thickness might be within a range from about 100 to 300 μm. The first leadframe may be made of copper or copper alloy. Other alternatives include aluminum and invar. A typical current leadframe thickness for the illustrated leadless configuration might be within a range from about 100 to 200 μm. For the illustrated implementation, the surface 101a (upper surface in FIG. 1) may be an "active" surface on which are formed the bond pads 102 and "active" circuit and/or operating discrete components. The opposite surface (lower surface in FIG. 1) may be a "passive" surface "with no electrically active components formed thereon. Other surface configurations are possible. Surface 101b of chip 101 is shown attached to the chip pad 103 using conventional chip attach material 105, such as adhesive epoxy or polyimide (which may be silver-filled for better thermal conductivity).

For the shown example, bond pads 102 are located on upper surface 101a and are electrically conductively connected to leads 104. A preferred method of connection in the given example is by ball bonding of wires 106, such as using automated bonding techniques resulting in low loop heights. Alternatively, low-looped ribbon bonding using wedge stitching may be employed. An appropriate material for the wires or ribbons comprises gold or gold alloys. Alternatives include copper and aluminum.

The second integrated circuit chip assembly comprises a chip 110, which has a surface 110a and a plurality of bond pads 112. The second assembly further has a second leadframe comprising a plurality of leads 114. The illustrated configuration for the second leadframe does not have a chip mount pad; although such a pad is usable in some configurations. In the example shown in FIG. 1, leads 114 provide the input/output terminals for the second assembly. Leads 114 have outer lead ends 114a which are shaped to provide attachment to externals parts (by soldering or pressure contacts). For the illustrated example, the second lead ends 1 14a are advantageously configured to be coplanar with the first leads 104, in the plane of the base of the encapsulated package. This provides ease of alignment with and electrical attachment to, for example, corresponding contact locations on a printed circuit board or other mounting substrate. For typical implementations, as with chip 101, chip 110 may likewise be made of silicon or, alternatively, of silicon germanium, gallium arsenide or other semiconductor materials. Likewise, too, a typical suitable chip thickness might be within a range from about 100 to 300 μm. The material of the second leadframe may be the same or different from the material of the first leadframe. Possible materials include copper, copper alloy, aluminum and invar, at thicknesses within a range from about 100 to 200 μm. For the illustrated implementation, the surface 110a (lower surface in FIG. 1) may be an "active" surface on which are formed the bond pads 112 and "active" circuit and/or operating discrete components. The opposite surface (upper surface in FIG. 1) may be a "passive" surface with no electrically active components formed thereon, or may also be an "active" surface. Other surface configurations are possible. (For example, while placing the bond pads 112 on the under surface in the shown configuration provides some advantages that may not otherwise be realized, the bond pads 112 could be placed on the upper surface 110b. This may result in a higher profile to the encapsulated package, however.)

Bond pads 112 are electrically conductively connected to surfaces of inner lead ends 114b of leads 114. A preferred method of connection in the given example is by ball bonding of wires 116, especially by automated bonding techniques resulting in low loop heights. Alternatively, low-looped ribbon bonding using wedge stitching may be employed. Appropriate wire or ribbon materials for wires or ribbons 116 are the same as those given for wires or ribbons 106, above. In the illustrated example, inner lead ends 1 14b have surfaces (upper surfaces in FIG. 1) configured and located to present a planar platform for attachment of portions of surface 110a of chip 110 by means of an adhesive insulator layer 115. A usable insulator material may be polyimide in a layer thickness range of about 1 μm.

As FIG. 1 shows, the second assembly is superposed over the first assembly, in a vertically stacked, generally aligned relationship. For the given example, second chip (active) surface 110a faces first chip (active) surface 101a across a gap with spacing 120 between surfaces 110a, 101a. For practical reasons, the gap 121 separating the bonding loops of wires 116 and 106 is of more consequence for controlling the vertical alignment of the first assembly and the second assembly. Major contributions to this control are the bending and forming of the second leadframe leads 114 and the loop height control of wires 116 and 106. As shown in FIG. 1, an encapsulation material 130 fixes the relative positions of the two assemblies including the dimension of the spacing of the chips 101, 1 10 across the gap 120. Although not necessary for fixing the relative positions, the material 130 is preferably flowed into and around the chips 101, 110 to fill the gap 120 and also to protect the active chip surfaces and bonding wires, substantially completely filling any voids within the outline 131 of the presented package. A preferred technique to accomplish this comprises placing the second assembly over the first assembly within a mold cavity which has an inner surface that defines the package outline 131. An epoxy molding compound, such as one filled with inorganic anhydrides, is then flowed into the cavity to fill the gap 120 and surround the portions of the first and second assemblies located within the cavity. When the molding compound cures (hardens) and the device is removed from the mold, it has the external package outline 130 with unexposed parts of the two assemblies relatively fixed by embedment in the cured material. For the shown example, lead ends 1 14a and adjacent portions of leads of leadframe 114 are left out of the mold cavity and, thus, remain exposed to extend out of the package outline 131 (similar to lead extensions left exposed in current surface mount leaded packages). The metal pieces of leads 104, on the other hand, are placed against the inside of the mold cavity, so are accessible but do not extend from the final package outline 131. Using the advanced controls available in such a transfer molding technique, tight control over the (vertical) device thickness 140 is achievable. Total device thicknesses 140 of less than 1 mm are able to be accomplished.

FIG. 2 is a top view of an external surface of a printed circuit board or other mount 200 onto which the described multichip device 100 may be attached. The illustrated mount 200 comprises an insulating substrate 201 with an outer, generally rectangular array of metallic contact pads 202 and an inner, generally concentric, generally rectangular array of contact pads 203. The example multichip device 100 may be attached to the mount 200 by solder reflow with, for example, a solder made of tin or a tin alloy. The outer pads 202 are configured, dimensioned and located to align with and contact lead ends 114a (see FIG. 1). The inner pads 203 are configured, dimensioned and located to align with and contact lead portions 104. Substrate 201 (FIG. 2) may have a planar configuration FIG. 2 to match a previously described coplanar configuration of leads 114a and 104. Substrate 201 may, alternatively, have a non-planar surface configuration to match other non-planar arrangements of the contacting portions of lead ends 114a and leads 104. For example, mount 200 may have a vertically stepped elevation from inner rectangular array of pads 203 to outer rectangular array of pads 202, or vice versa. In which case, the respective planarities of the lead ends 114a and the leads 104 (that is, exposed metal pieces) will likewise be vertically offset in a corresponding, complementary way. FIG. 3 illustrates an example of a modified form 300 of the embodiment of the multichip semiconductor 100 device of FIG. 1. As with the device 100 of FIG. 1, the device 300 presents a stacked arrangement of first and second semiconductor integrated circuit chip assemblies, with first and second chips 101, 110 fixed in spaced, superposed relationships within a common package outline by encapsulation material 330. And, as before, first chip 101 is mounted on a leadless type leadframe carrier with non-extending exposed metal surfaces 104 (in, for example, a quad flat pack type rectangular configuration), while second chip 110 is mounted on a leaded leadframe carrier with extending lead portions (in, for example, a rectangular configuration of greater diameter than the quad flat pack configuration). In departure from the device 100, however, the encapsulation material 330 has been applied in device 300 so that at least a portion of the (upper) surface 1 10b of the second chip 110 is left exposed at the exterior of the package outline. This can be accomplished, for example, by placing the upper surface of the chip 1 IO in contact with the upper wall of the mold cavity during a transfer mold encapsulation process. A heat sink 340 may then be attached to the exposed surface portion of chip 110 by a suitable adhesive attach material 341, which is advantageously thin and metal-filled (preferably silver-filled) to encourage heat transmission.

The thermal performance of multichip device 300 may be even further improved by the concurrent addition of a cooled or heat sink external part 350 in contact with a similarly exposed portion of chip pad 103 of the first leadframe. In this case, botli chips 101 and 1 10 can be made to experience steep temperature gradients to the environment and thus enjoy excellent cooling and thermal operational performance.

FIGS. 4 A, 4B, 5 A, 5B and 6 illustrate process steps in an example method for fabricating first and second assemblies and combining them into a multichip semiconductor device such as the device 100 or 300 described above. Because the chips 101 and 1 10 are superposed in vertical relationships to each other and not mounted side ^"by side, the fabrication of first and second assemblies can proceed separately until the point of stacking and encapsulation.

As shown in FIG. 4 A, in the fabrication of the first assembly, first chip 101 is mounted onto first leadframe 401, which may be of the type such as used conventionally for development of a single chip, leadless semiconductor integrated circuit package. Leadframe 401 is provided with a chip mount pad 103 and a plurality of leads (namely, metal contact shoes) 104. As described previously with reference to FIG. 1, chip 101 is provided with surfaces 101a, 101b and a plurality of bond pads 102. In the illustrated example, bond pads 102 are located on one surface 101a and the opposite surface 101b is attached to a facing surface of chip mount pad 103 using, for example, a polymer adhesive 105. Then, as shown in FIG. 4B, electrical connectivity of bond pads 102 with leads 104 is established by means of wires 106 connected by wire ball bonding between bond pads 102 and stitch sites 106b of respective leads 104. Stitch sites 106b of leads 104 may have prior processing to prepare them as suitable sites for stitch attachment, as for instance by deposition of a silver or palladium spot on an otherwise copper leadframe. Although the illustrated bonding is "downhill" between like facing surfaces (upwardly facing surface to upwardly facing surface) along the chip sides to leads 104, the loop height 402 is preferably kept low in order to provide a thin overall device contour in the final assembly of the multichip device.

FIG. 5 A illustrates the fabrication of the second assembly of the device. Here, second chip 110 is mounted onto a second leadframe 501, which may be of a type such as used conventionally for development of a single chip, leaded flat mount package. As described previously with reference to FIG. 1, chip 110 is provided with surfaces 110a, 110b and a plurality of bond pads 112. Leadframe 501 is provided with a plurality of leads 114, configured with a step 510 formed when the leadframe is originally stamped or punched from metal sheet material. Step 510 (which is small and may not be present in some embodiments) raises inner end portions 114b of leads 114 to present a planar platform onto which chip 110 is affixed. In the illustrated example, bond pads 112 are located on one surface 110a and peripheral portions of the same surface 110a are attached to facing surfaces of inner lead ends 114b by means of an adhesive insulator layer 115.

Following attachment of chip 110 to leadframe inner ends 114b, the second assembly is inverted (see FIG. 5B) to establish electrical connectivity of bond pads 112 with leads 114. This may be done, for example, by a wire bonding operation, wherein wires 106 (FIG. 1) are connected between chip bond pads 112 surface 110a of chip 110 and stitch sites located on same facing surfaces of inner ends 114b (surfaces opposite layer 115). Again, loop height 502 is kept low in order to provide a thin overall device contour in the final assembly of the multichip device.

FIG. 6 illustrates the alignment of the second assembly with the first assembly in a cavity 601 of a transfer mold having bottom half and top half mating mold parts 602a, 602b which are brought together for the molding process. The first assembly (that with chip 101) is placed on the bottom of the mold cavity of the bottom mold lialf 602a, with the bottom surface of leadframe 401 (see FIG. 4A) in contact with the bottom (for example, made of steel) surface of mold half 602a within cavity 601. The surface 101a of first chip 101 (surface with the bond pads 102) is facing upward. The second assembly (that with chip 110) is then placed over the first assembly, with surface 110a of chip 110 (surface with the bond pads 112) facing downward towards the surface 101a of chip 101. For the illustrated example, bottom surfaces of the metal shoe leads 104 of the "leadless" leadframe 401 are likewise in contact with the bottom surface of mold half 602a within cavity 601. The outer lead ends 114a of leads 114 rest on a top surface outside cavity 601 of the bottom mold half 602a. The position of the second assembly is adjusted until chip 1 10 is generally centered above and aligned with chip 101. The upper mold half 602b is then closed and pressed against bottom mold half 602a. A molding compound is transferred into cavity 601 to fill the cavity and any assembly gaps.

In the illustrated embodiment, step 510 of leadframe 501 (FIG. 5A) is useful to facilitate alignment of the second assembly over the first assembly, and to raise the chip 1 10 above the joinder line of the mold halves 602a, 602b. This provides a "balanced" distribution of molded material above and below the leads 114 at a mold centerline, from which outer portions of the leads 114 are left to extend outside the cavity 601. This feature helps to equalize the internal stress distribution in a molded package after the volumetric shrinkage of the molding compound during the curing cycle.

After completing the molding process, the encapsulated multichip product is taken from the press for curing the compound and forming the outer leads 114a. For the embodiment illustrated in FIG. 6, the outer leads 114a are pressed into the gull wing shape shown in FIG. 1.

As already mentioned, the material of the semiconductor chip may comprise silicon, silicon germanium, gallium arsenide, or any other semiconductor or compound material used in integrated circuit manufacturing. Also, the chips of trie first and second assemblies may have significantly different sizes, different numbers of input/output connections, etc.

Moreover, although the examples illustrate two-chip embodiments, the same principles apply to multichip packages having more than two chips, with additional chips having separate leadframes or additional chips located on the same leadframes. Also, the configurations the portions of leads left exposed outside the molding compound outline may be different angled or formed.

Those skilled in the art to which the invention relates will appreciate that yet other modifications, additions, substitutions and variations τnary be made to the described embodiments, without departing from the scope of the invention, and that the reference to certain example embodiments is not intended to limit the invention to just those that are described.

Claims

1. A multichip semiconductor device comprising: a first semiconductor assembly comprising a first chip having a surface including first bond pads; and a first leadframe having first leads; said first chip being attached to said first leadframe and said first bond pads being respectively electrically conductively connected to said first leads; a second semiconductor assembly comprising a second chip having a surface including second bond pads; and a second leadframe having second leads; said second chip being attached to said second leadframe and said second bond pads being respectively electrically conductively connected to said second leads; said second assembly being vertically superposed with said first assembly; and encapsulation material forming a package outline and fixing relative positions of said first and second assemblies.

2. The device of Claim 1, wherein said connections are wire bonds.

3. The device of Claim 1 or 2, wherein said first leadframe comprises a leadless leadframe configuration and said second leadframe comprises a leaded leadframe configuration.

4. The device of any of Claims 1 to 3, wherein said surface including said first bond pads faces said surface including said second bond pads.

5. The device of any of Claims 1 to 4, wherein said leads of said first leadframe and said leads of said second leadframe have exposed portions which are coplanar.

6. The device of any of Claims 1 to 5, wherein said package outline forming said encapsulation material leaves a portion of said second chip exposed; and further comprising a heat sink attached to said exposed portion of said second chip.

7. The device of Claim 6, wherein said first leadframe includes a chip mount; said first chip is attached to said chip mount; said package outline forming said encapsulation material leaves a portion of said chip mount exposed; and further comprising a second heat sink attached to said exposed portion of said chip mount.

8. A method of making a multichip semiconductor device comprising: forming a first semiconductor assembly by providing a first chip having a surface including first bond pads, and a first leadframe having first leads; attaching said first chip to said first leadframe; and respectively electrically conductively connecting said first bond pads to said first leads; forming a second semiconductor assembly by providing a second chip having a surface including second bond pads, and a second leadframe having second leads; attaching said second chip to said second leadframe; and respectively electrically conductively connecting said second bond pads to said second leads; vertically superposing said second assembly with said first as sembly; and forming a package outline and fixing relative positions of said first and second assemblies with an encapsulation material.

9. The method of Claim 8, wherein said connecting step is done by wire bonding.

10. The method of Claim 8 or 9, wherein said package outline step provides presents said first leadframe in a leadless leadframe configuration and said second leadframe in a leaded leadframe configuration.

11. The method of any of Claims 8 to 10, wherein said superposing step positions said surface including said first bond pads to face said surface including said second bond pads.

12. The method of any of Claims 8 to 11, further comprising forming said leads of said first leadframe and said leads of said second leadframe to have exposed portions which are coplanar.

13. The method of any of Claims 8 to 12, wherein said package outline forming is done so that said encapsulation material leaves a portion of said second chip exposed; and further comprising attaching a heat sink to said exposed portion of said second chip.

14. The method of Claim 13, wherein said first leadframe includes a chip mount; said first chip is attached to said chip mount; said package outline forming step is done so that said encapsulation material leaves a portion of said chip mount exposed; and further comprising attaching a second heat sink to said exposed portion of said chip mount.