WO2006039677A2

WO2006039677A2 - Semiconductor doping using substrate tilting

Info

Publication number: WO2006039677A2
Application number: PCT/US2005/035562
Authority: WO
Inventors: Said Ghneim; James D. Bernstein; Lance S. Robertson; Jiejie Xu; Jeffrey Loewecke
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2004-10-01
Filing date: 2005-10-03
Publication date: 2006-04-13
Anticipated expiration: 2007-04-01
Also published as: US7232744B2; CN101061573A; JP2008515243A; US20060073685A1; WO2006039677A3

Abstract

Provided are a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device utilizing such implantation. The method for implanting a dopant, among other steps, includes: tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose with the substrate (310) tilted in the first direction; then, tilting the substrate (310) in a second direction, counter to the first direction, and implanting another portion of the implant dose with the substrate (310) tilted in the second direction.

Description

SEMICONDUCTOR DOPING USING SUBSTRATE TILTING

This relates, generally, to methods of doping semiconductor substrates; and, more specifically, to a method for implanting dopants by varying the tilt angle of substrates relative to the implantation source. BACKGROUND

Implantation of dopants in integrated circuit fabrication requires precise control of beam incidence angle. While a number of different types of beam incidence angle error exist, three of the more common types are cone angle error, beam steering error and parallelism error across the wafer. Cone angle error is typically a result of cone angle effects caused by the geometry of the wafer scanning system. Cone angle error may vary across the wafer. For example, the beam angle error may be about -x degrees at one wafer edge, about zero degrees at the wafer center, and about +x degrees at the opposing edge. Steering error, on the other hand, is introduced while tuning the beam between lots, implant batches, or whenever tuning occurs, and tends to be a uniform across the wafer. Parallelism error, however, leads to random beam incidence angle errors across the width of the wafer. The random nature of this error makes it especially difficult to correct.

Unfortunately, without precise control of beam incidence angle, various different problems degrade the transistors of the integrated circuit. As an example, transistor asymmetry, variation and depressed multiprobe yield (MPY) often result due to beam incidence angle error. The beam angle incidence angle error may also lead to gate shadowing and to an asymmetric dopant distribution, both of which are undesirable. FIG. 1 illustrates an example of gate shadowing on a transistor device 100. The transistor device 100 includes a gate structure 120, having a height (h), located over a substrate 110. The transistor device 100 is subjected to an implant process 130 to form implant regions 140. As illustrated, the gate structure 120 height (h) shadows or shields a portion of substrate 110 from implantation due to the incidence angle (θ) of the implant beam, thereby causing a difference in topography of implant regions 140 located on different sides of gate structure 120. For example, one implant region 140 (shown on the left side in FIG. 1) begins a distance (d) from the sidewall of gate structure 120, whereas the other implant region 140 (shown on the right side in FIG. 1) begins immediately adjacent to the sidewall of gate structure 120. While the distance (d) can be estimated using the equation d = h tan (θ), it nevertheless creates an unintended undoped region defined by the distance (d) that may lead to operational problems in the fabricated transistor 100. Accordingly, a method for implanting dopants within a substrate is needed that does not experience the drawbacks of the prior art methods and devices. SUMMARY

The invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device wherein the substrate tilt angle is varied during doping. In an embodiment, a method for implanting a dopant includes orienting substrate at a first angle in a first direction (for example, x degrees clockwise) about an axis relative to an implant source; implanting a portion of an implant dosage with the substrate oriented at the first angle; orienting the substrate at a second angle in a second direction, opposite the first direction (for example, x degrees counterclockwise) about the axis relative to the implant source; and implanting another portion of the implant dosage with the substrate oriented at the second angle. The second angle may optionally be chosen to be equal and opposite to the first angle. The first and second angles may optionally be chosen to have a separation of about 90 degrees.

In a modified implementation, the method may include orienting the substrate again at a third angle in the first direction about the axis relative to the implant source; implanting a third portion of the implant dosage with the substrate oriented at the third angle; orienting the substrate at a fourth angle in the second direction, opposite to the first direction, about the axis relative to the implant source; and implanting a fourth portion of the implant dosage with the substrate oriented at the fourth angle. The third and fourth angles may optionally be chosen to be respectively the same as the first and second angles. The first, second, third and fourth implantation portions may optionally comprise implantations for equal (that is, one-quarter of total) implantation dosages, rates or time periods.

The substrate may be located on a platen, and the orienting steps may be accomplished by tilting the platen about an axis. The invention further provides a method for manufacturing a semiconductor device, using the described doping implantation method. In one implementation, a method for manufacturing a semiconductor device, comprises forming a gate structure over a substrate, and forming implants within the substrate proximate the gate structure, for the formation of source and drain regions of a MOS transistor device.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are described herein, with reference to accompanying drawings, wherein:

FIG. 1 (Prior Art) illustrates an example of gate shadowing during doping known doping in the manufacture of a transistor device;

FIG. 2 is a graph, illustrating the impact that beam incidence angle error has on the drive current of an n-channel metal oxide semiconductor (NMOS) device, for both vertical transistors and horizontal transistors on the same wafer;

FIGS. 3 - 6 are schematic illustrations, showing top and cross-section views, in steps of an example process in which a plurality of substrates are subjected to doping in accordance with principles of the invention; and

FIG. 7 is a cross-section view of an integrated circuit (IC) incorporating semiconductor devices fabricated according to a doping process utilizing the principles of the invention. DETAILED DESCRIPTION The invention is based in part on the recognition that beam incidence angle error often has a different affect on vertical transistors located on a semiconductor wafer than similar horizontal transistors located on the same semiconductor wafer. FIG. 2 shows a graph 200 illustrating the impact that beam incidence angle error has on the drive current of an n-channel metal oxide semiconductor (NMOS) device for both vertical transistors and horizontal transistors on the same wafer. As the beam incidence angle error increases from about -0.5 degrees to about 3.0 degrees, the respective drive currents of the vertical transistors and horizontal transistors are affected differently.

Specifically, in the example of FIG. 2, the horizontal transistors are substantially affected by the beam incidence angle error, whereas the vertical transistors are not. The opposite effect would occur if the beam incidence angle error were in a direction normal to what it is given in the example of FIG. 2. Unfortunately, the disparate change in drive current between the vertical transistors and horizontal transistors makes accommodating the change in drive current difficult.

In combining the aforementioned recognition with the appreciation that beam incidence angle error tends to vary across the wafer, the invention recognizes that benefits can be achieved by orienting an implantable substrate about an axis in a direction relative to an implant source; implanting a portion of an implant dosage with the substrate so oriented; then orienting the substrate in the opposite direction; and implanting another portion of the implant dosage with the substrate oriented in the opposite direction.

The novel implant process reduces transistor asymmetry by reducing implant shadowing due to the beam incidence angle error. It improves transistor asymmetry for both NMOS and PMOS transistors. Additionally, it attempts to make both the vertical and horizontal transistors have substantially similar dopant profiles, and thus drive currents. These benefits lead to, among others, improved transistor matching circuitry and improved SRAM balance.

FIGS.3-6 schematically illustrate top and cross-section views of steps in the fabrication of an example dopant dosage implantation according to an illustrative embodiment of the invention. FIG. 3 shows a top view 300 and two cross-section views 340, 370 of a plurality of substrates 310 located on or over an implant platen 305, as they are being subjected to an implant from an implantation source 320. The top view 300 and two cross-section views 340, 370 represent snapshots in time of the implant platen 305 and substrates 310 as they rotate about a center point of the implant platen 305. As those skilled in the art are aware, the implant platen 305 in the embodiment of FIG. 3 typically rotates in a clockwise or counterclockwise direction at a high rate of speed as the implant source 320 slowly scans across the implant platen 305 from side to side.

The embodiment of FIG. 3 show only four substrates 310 are located on or over the implant platen 305. The actual number of substrates 310 can be fewer or more than those shown. Also, the implant platen 305 is illustrated in FIG. 3 as a disk, but may have other shapes as a matter of design choice.

As is often the case with modern integrated circuits, each of the substrates 310 in the example embodiment of FIG. 3 has both vertical (v) and horizontal (h) transistors. This is, of course, not a requirement and the benefits of the invention are applicable also to those situations where only vertical (v) or horizontal (h) transistors exist.

As indicated above, it is often the case where the implant source 320 has an implant angle error associated therewith. This implant angle error is illustrated in FIG. 3 as (α). The implant angle error (α) should generally be kept as low as possible; however, even larger angles of error (α) can be dealt with using implementations of the invention. In a typical case, the implant angle error (α) may range up to about 5 degrees.

The inventive method of the present invention is configured to reduce the effect of the implant angle error (α) by partially implanting the substrates 310 a number of different times in a number of different configurations until a given implant dose is attained. With that in mind, the substrates 310 are oriented about an axis in a first direction with relative the implant source 320. In the embodiment illustrated in FIG. 3, the substrates 310 are tilted (pivoted) about a y-axis counterclockwise by an angle (θ). After the substrates 310 are tilted, one-quarter of the implant dosage is implanted into the substrates 310. This can be determined by imparting equal implantation partial dosages, rates or time periods.

The tilt angle (θ) of the substrate 310 may vary greatly. In an example embodiment of the invention, the tilt angle (θ) is substantially equal to the implant angle error (α) of the implant source 320. In this embodiment, the tilt angle (θ) would, but for a small region of less doped substrate common to both the vertical (v) and horizontal (h) transistors, substantially eliminate the effect of the implant angle error (α). Nevertheless, an exemple embodiment suggests that the tilt angle (θ) be up to about 5 degrees, and particularly between about 1 degree and about 3 degrees. Other tilt angles (θ) are within the scope of the invention.

Additionally, the tilt angle (θ) may be achieved using a number of different processes. For example, one embodiment of the invention tilts the entire implant platen 305 to effectuate the tilt of the substrates 310. Another different embodiment of the invention tilts each individual substrate 310 on the implant platen 305, keeping the angle of the implant platen 305 itself unchanged. Other ways for tilting the substrates 310 relative to the implantation source can be used. As shown by the cross-section view 340, the implant angle error (α) may not substantially affect the horizontal transistor (h). For example, implant regions 380 formed as a result of the first portion of the implant dose are located equidistant from the gate of the horizontal transistor (h). On the other hand, as shown by the cross-section view 370, the implant angle error (α) will substantially affect the vertical transistor (v). The gate shadowing caused by the combination of the implant angle error (α) and tilt angle (θ) causes the implant regions 380 of the vertical transistor (v) to be not located equidistant from the gate of the vertical transistor (v). For instance, as illustrated in FIG. 3, one implant region 380 is removed from the gate structure of the vertical transistor (v) and the other implant region 380 is located adjacent the gate structure of the vertical transistor (v). What results is a lighter doped region 390 located proximate the gate structure of the vertical transistor (v), the lighter doped region 390 having less dopant therein. At the stage shown in FIG. 3, the lighter doped region 390 may have substantially no dopant therein. The implant regions 380 located in the substrate 310 at this stage contain only one-quarter of the total desired implant dosage.

FIG. 4 illustrated views 300, 340, 370 (similar to those of FIG. 3) after the substrates 310 have been tilted about the same axis, but in an opposite direction. In the embodiment illustrated in FIG. 4, the substrates 310 are tilted about the y-axis clockwise by the angle (θ). In an exemplary embodiment, the tilt angle (θ) used in FIG. 4 is substantially identical in value, but opposite in direction, to the tilt angle (θ) used in FIG. 3. After the substrates 310 are tilted this second time, another one-quarter of the implant dose is implanted into the substrates 310.

As shown by the cross-sectional view 340, the implant angle error (α) again does not substantially affect the horizontal transistor (h). For example, implant regions 380 formed as a result of the second portion of the implant dose are still located equidistant from the gate of the horizontal transistor (h). This time, however, as shown by the cross-section view 370, the implant angle error (α) does not substantially affect the vertical transistor (v), as the implant angle error (α) is substantially offset by the tilt angle (θ). What results is a full one-quarter implant dosage reaching the implant regions 380 of the substrate 310, as well as a full one-quarter implant dosage reaching the lighter doped region 390. Accordingly, the implant regions 380 of both the vertical transistor (v) and the horizontal transistor (h) at this stage cumulatively have a one-half implant dosage and the lighter doped region 390 located proximate the gate of the vertical transistor (v) has a one-quarter implant dosage.

FIG. 5 illustrates similar views 300, 340, 370, after the substrates 310 have been rotated by a specific angle and then tilted about the same axis as in FIGS.3 and 4. In the embodiment illustrated in FIG.4, the substrates 310 are rotated about the z-axis by about 90 degrees in a clockwise direction and are tilted about the y-axis counterclockwise by the angle (θ). It should be noted that the substrates 310 can, optionally, beneficially be rotated by about 90 degrees in either the clockwise or counterclockwise direction from the position they occupied in FIGS.3 and 4. After the substrates 310 are rotated and tilted this third time, another one-quarter of the implant dosage is implanted into the substrates 310.

As shown by the cross-section view 340, the implant angle error (α) does now substantially affect the horizontal transistor (h). The gate shadowing caused by the combination of the implant angle error (α) and tilt angle (θ) causes the implant regions 380 of the horizontal transistor (h) to not be located equidistantly from the gate of the horizontal transistor (h). For instance, as illustrated in FIG. 5, one implant region 380 is removed from the gate structure of the horizontal transistor (h) and the other implant region 380 is adjacent the gate structure of the horizontal transistor (h). What results is a lighter doped region 510 located proximate the gate structure of the horizontal transistor (h) having only a one-half dosage, whereas the implant regions 380 of the horizontal transistor (h) have cumulatively a three-quarter dosage. On the other hand, the vertical transistors (v) are not substantially affected by the implant angle error (α) in this configuration. Accordingly, the implant regions 380 of the vertical transistors (v) now cumulatively have a three-quarter implant dosage and the lighter doped region 390 cumulatively has a one-half implant dosage.

FIG. 6 shows views 300, 340, 370, after the substrates 310 have been tilted about the same axis but in the opposite direction. In the embodiment illustrated in FIG. 6, the substrates 310 are tilted about the y-axis clockwise by the angle (θ). After the substrates 310 are tilted this fourth time, another one-quarter of the implant dosage is implanted into the substrates 310.

As shown by the cross-section view 340, the implant angle error (α) this time does not substantially affect the horizontal transistor (h), as the implant angle error (α) is substantially offset by the tilt angle (θ). What results is a full one-quarter implant dosage reaching the implant regions 380 of the substrate 310, as well as a full one-quarter implant dosage reaching the lighter doped region 510. Additionally, as shown by the cross-section view 370, the implant angle error (α) again does not substantially affect the vertical transistor (v). What results is a full one-quarter implant dosage reaching the implant regions 380 of the vertical transistor (v) as well as a full one-quarter implant dosage reaching the lighter doped region 390. Accordingly, the implant regions 380 of both the vertical transistor (v) and the horizontal transistor (h) at this stage have cumulatively a full implant dosage, and the lighter doped region 390 located proximate the gate of the vertical transistor (v) and the lighter doped region 510 located proximate the gate of the horizontal transistor (h) each have cumulatively a three-quarter implant dosage.

Ideally, as illustrated in FIG. 6, the resulting vertical transistors (v) and horizontal transistors (h) have substantially identical dopant profiles. Accordingly, the resulting vertical transistors (v) and horizontal transistors (h) have substantially identical drive currents. Not only do the resulting vertical transistors (v) and horizontal transistors (h) have substantially identical drive currents, the lighter doped regions 390, 510, each have at least three-quarters of the desired dose. Further, the inventive aspects of the present invention are particularly useful for forming lightly doped source/drain extension implants.

FIG. 7 shows is a cross-section view of an integrated circuit (IC) 700, incorporating semiconductor devices 710 constructed according to the principles of the present invention: The IC 700 may include devices, such as transistors used to form CMOS devices, BiCMOS devices, Bipolar devices, or other types of devices. The IC 700 may further include passive devices, such as inductors or resistors, or it may also include optical devices or optoelectronic devices. Those skilled in the art are familiar with these various types of devices and their manufacture. In the particular embodiment illustrated in FIG. 7, the IC 700 includes semiconductor devices 710 having dielectric layers 720 located thereover. Additionally, interconnect structures 730 are located within the dielectric layers 720 to interconnect various devices, thus, forming the operational integrated circuit 700.

Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the scope of the invention in its broadest form.

Claims

CLAIMS:

1. A method for implanting a dopant in a substrate, comprising: orienting a substrate at a first angle in a first direction about an axis relative to an implant source; implanting a portion of an implant dosage with the substrate oriented at the first angle; orienting the substrate at a second angle in a second direction, opposite to the first direction, about the axis relative to the implant source; and implanting another portion of the implant dosage with the substrate oriented at the second angle.

2. The method of Claim 1, wherein the second angle is equal and opposite to the first angle.

3. The method of Claim 1 or 2, wherein the first and second angles are separated by about 90 degrees.

4. The method of any of Claims 1 - 3, further comprising: orienting the substrate again at a third angle in the first direction about the axis relative to the implant source; implanting a third portion of the implant dosage with the substrate oriented at the third angle; orienting the substrate at a fourth angle in the second direction, opposite to the first direction, about the axis relative to the implant source; and implanting a fourth portion of the implant dosage with the substrate oriented at the fourth angle.

5. The method of Claim 4, wherein the third and fourth angles are respectively the same as the first and second angles.

6. The method of Claim 4 or 5, wherein the first, second, third and fourth portions comprise implantations for equal implantation partial dosages, rates or time periods.

7. The method of Claim 1 — 6, wherein the substrate is located on a platen, and the orienting steps are accomplished by tilting the platen about the axis.

8. A method for manufacturing a semiconductor device, comprising forming at least one implant using the method for implanting a dopant as in any of Claims 1 - 7.

9. The method of Claim 8, further comprising forming a gate structure over a substrate, and wherein the method of implanting a dopant is used for at least part of the formation of source and drain regions of a MOS transistor device.