WO2006035377A2 - Integrated sicr metal thin film resistors for sige rf-bicmos technology - Google Patents

Integrated sicr metal thin film resistors for sige rf-bicmos technology Download PDF

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WO2006035377A2
WO2006035377A2 PCT/IB2005/053126 IB2005053126W WO2006035377A2 WO 2006035377 A2 WO2006035377 A2 WO 2006035377A2 IB 2005053126 W IB2005053126 W IB 2005053126W WO 2006035377 A2 WO2006035377 A2 WO 2006035377A2
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Prior art keywords
sicr
thin film
deposition
film
metal thin
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PCT/IB2005/053126
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French (fr)
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WO2006035377A3 (en
Inventor
Hongjiang Sun
Kaman Lau
Peggie Mcdonald
Nancy E. Bell
Tayel Nesheiwat
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Koninklijke Philips Electronics, N.V.
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Priority to JP2007534144A priority Critical patent/JP2008515215A/en
Priority to EP05784383A priority patent/EP1938361A2/en
Publication of WO2006035377A2 publication Critical patent/WO2006035377A2/en
Publication of WO2006035377A3 publication Critical patent/WO2006035377A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates in general to semiconductor devices. More particularly, the present invention is directed to the formation of integrated SiCr metal thin film resistors for SiGe RF-BiCMOS (Radio Frequency Bipolar Complementary Metal Oxide Semiconductor) technology.
  • SiGe RF-BiCMOS Radio Frequency Bipolar Complementary Metal Oxide Semiconductor
  • the present invention provides integrated SiCr metal thin film resistors for SiGe RF BiCMOS technology.
  • the use of integrated SiCr thin film resistors increases packaging density and reduces the parasitic effect induced from surface mount configurations at high frequencies.
  • the sheet resistance of SiCr thin film resistors can be varied in a wide range of about 400 - 2500 ohms/square with less than 2% uniformity by selectively controlling SiCr deposition conditions.
  • SiCr thin film resistors formed in accordance with the present invention have linear and quadratic coefficients of TCR less than about 100 ppm/°C and -0.9 ppm/°C 2 , respectively.
  • a first aspect of the present invention is directed to a method for forming an SiCr metal thin film resistor, comprising: depositing a film of SiCr on a planarized surface of a dielectric substrate; annealing the SiCr film; applying a photoresist to the SiCr film; patterning the photoresist using a single mask to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor; wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 ohms/square.
  • a second aspect of the present invention is directed to a semiconductor structure comprising: an SiCr metal thin film resistor having a sheet resistance of greater than about 400 ohms/square.
  • a third aspect of the present invention is directed to a method for forming an SiCr metal thin film resistor, comprising: depositing a film of SiCr on a planarized surface of a dielectric substrate; annealing the SiCr film; applying a photoresist to the SiCr film; patterning the photoresist using a single mask to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor; wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 - 2500 ohms/square, a temperature coefficient of resistance (TCR) linear and quadratic coefficients of less than about 100 ppm/°C and -0.9 ppm/°C 2 , respectively, and a resistivity in a range of about 3,588 - 13,000 ⁇ -cm.
  • TCR temperature coefficient of resistance
  • FIG. 1 is an SEM (scanning electron microscope) cross-section of an SiCr thin film resistor produced in accordance with an embodiment of the present invention.
  • FIGS. 2-8 illustrate a process for forming an SiCr thin film resistor in accordance with an embodiment of the present invention.
  • FIGS. 9 and 10 illustrate the sheet resistance of SiCr films under different annealing conditions.
  • FIG. 1 1 illustrates the influence of argon flow on SiCr film deposition.
  • FIG. 12 illustrates SiCr sheet resistance as a function of deposition RF power.
  • FlG. 13 illustrates SiCr sheet resistance as a function of reciprocal thickness.
  • FIG. 14 illustrates the measured resistance of various SiCr thin film resistors fabricated in accordance with the present invention.
  • FIG. 15 illustrates TCl and TC2 coefficients of TCR as a function of anneal temperature.
  • FIG. 16 illustrates the normalized TCR of SiCr and polysilicon resistors as a function of temperature.
  • FIG. 17 illustrates the normalized resistance of SiCr and polysilicon resistors as a function of bias.
  • FIG. 1 there is illustrated an SEM (scanning electron microscope) cross-section of an SiCr metal thin film resistor 10 produced in accordance with an embodiment of the present invention.
  • the SiCr thin film resistor 10 is formed on a high-density planarized dielectric substrate 12 comprising, for example, silicon dioxide (SiO 2 ).
  • the SiCr thin film resistor 10 is directly connected to an upper metal level 14 by vias 16.
  • FIGS. 2-8 A method for forming an SiCr thin film resistor 10 in accordance with an embodiment of the present invention is illustrated with reference to FIGS. 2-8.
  • a high-density dielectric substrate 12 which includes various metal layers 14 (e.g., M2, M3) interconnected by vias 16.
  • the metal layers 14 and vias 16 are formed using conventional photolithographic techniques.
  • the dielectric substrate 12 can be formed, for example, using a high density plasma (HDP) chemical vapor deposition (CVD) process.
  • HDP high density plasma
  • CVD chemical vapor deposition
  • PETEOS plasma enhanced tetraethylorthosilicate
  • SACVD selective area chemical vapor deposition
  • the dielectric substrate 12 is planarized (FIG. 3) prior to the deposition of an SiCr film. Planarization may be provided, for example, using known CMP (chemical- mechanical polishing) techniques. Thereafter, a film of SiCr 18 is deposited on the planarized surface 20 of the dielectric substrate 12.
  • the SiCr RlE (reactive ion etch) process window in a later step is improved because the SiCr is deposited on the planarized surface 20 of the dielectric substrate 12.
  • the SiCr film 18 is deposited on the planarized surface 20 of the dielectric substrate 12 using PVD (physical vapor deposition) of a SiCr target 21 (shown in phantom) in argon/oxygen gases.
  • PVD physical vapor deposition
  • high Si contents are used with Cr in the target 21 , for example, 72 wt% Si and 28 wt% Cr.
  • the deposition rate of the SiCr film 18 can be varied, depending on the RF power, gas flow, and chamber pressure used during deposition.
  • the thickness of the SiCr film 18 can be varied to achieve a desired sheet resistance value of the SiCr film 18.
  • a post-deposition anneal is then performed in a temperature range of 380 - 500 0 C.
  • a single mask step is used to define the SiCr thin film resistor. This provides an advantage over other materials typically used to fabricate integrated metal thin film resistors, including TaN, NiCr, and TaSi, which require more than one masking level.
  • a layer of photoresist 22 is applied to the SiCr film 18 and patterned using a single mask 23 (shown in phantom). The photoresist 22 can be applied, for example, using spin coating or other suitable techniques. The resultant structure is illustrated in FIG. 4.
  • a plasma dry etching of the SiCr thin film 18 is then performed using a mixed chemistry of C1 2 /BC1 3 /SF 6 to form an SiCr thin film resistor 10.
  • Other suitable etchant chemistries including, for example, CF 4 /CHF 3 , can also be used.
  • the resultant structure after stripping the photoresist 22 is illustrated in FIG. 5.
  • the sheet resistance of the SiCr thin film resistor 10 can be varied in a wide range of about 400 - 2500 ohms/square with less than 2% uniformity by selectively controlling SiCr deposition conditions.
  • the SiCr thin film resistor 10 formed in accordance with the present invention has linear and quadratic coefficients of TCR less than about 100 ppm/°C and -0.9 ppm/°C 2 , respectively.
  • an additional dielectric layer 24 is then deposited (e.g., using an HDP-CVD process) on the planarized surface 20 of the dielectric substrate 12 and the SiCr thin film resistor 10.
  • the dielectric layer 24 is then planarized and patterned using known techniques. Thereafter, as shown in FIGS. 7 and 8, metal plugs 16 are formed in a known manner to connect the SiCr thin film resistor 10 with later formed top metal interconnects 14.
  • a DOE Design of Experiments of the SiCr deposition was performed.
  • the purpose of the DOE was to understand the process conditions for SiCr deposition and anneal in order to establish a manufacturable process.
  • the SiCr film thickness was varied as necessary to achieve the desired sheet resistance.
  • the DOE involved various SiCr deposition process parameters such as RF power, gas flow, and deposition pressure followed by various anneals temperatures.
  • Table 1 lists the process window of the SiCr deposition DOE and how each process parameter affected the deposition of the SiCr film. It was found that a low power, low pressure, and adequate Ar/O ratio are needed to maintain a stable SiCr deposition process.
  • FIGS. 9 and 10 show sheet resistance (Rs) data of SiCr films: as-deposited and after anneal at different temperatures.
  • Rs changed as the anneal temperature. This change indicates that the crystallization of SiCr was advanced by the thermal anneal.
  • the results demonstrate that the SiCr film as deposited is a composite amorphous/crystalline.
  • the thermal anneal temperature changes resistance and thus suitability for use in an integrated passives structures.
  • the resistivity varied in a range of 5,000 - 13,000 ⁇ -cm.
  • FIG. 11 summarizes the influence of the argon flow on SiCr film deposition, while maintaining all other SiCr deposition parameters unchanged (SiCr film annealed at 420 0 C for 60 minutes).
  • the Rs and thickness of the SiCr film linearly changed as the argon flow.
  • the correlation between Rs and thickness as a function of argon flow indicates that the argon flow does not affect the composition of SiCr film.
  • FIG. 12 shows Rs as a function of deposition RF power. As RF power increases, the Rs of the SiCr film decreased in the range of 1000 - 2000 ohms/square. Thus, RF power affects the Rs of the SiCr film.
  • This correlation allows the fabrication of a wide range of SiCr thin film resistors without changing the composition of the SiCr target (i.e., by changing the deposition RF power).
  • the deposition time was varied to change the SiCr film thickness.
  • the Rs of the SiCr film changed as a function of the reciprocal thickness for different RF deposition powers (using data from Halo generator deposition).
  • the extrapolated resistivity of SiCr film ranged from about 3588 - 13,000 ⁇ -cm.
  • Low RF power SiCr deposition showed a higher resistivity than a high RF power deposition.
  • the data indicates that RF power affects the composition (e.g., the resistivity) of SiCr film.
  • FIG. 14 shows the measured resistance of various SiCr thin film resistors (in the range of 1.7x4 ⁇ m 2 to 9.8x400 ⁇ m 2 ) that were fabricated in accordance with the present invention.
  • the SiCr thin film resistors show a good linear resistance variation as a function of width and length in a wide range up to 100k ohms.
  • the SiCr thin film resistors also exhibit low TCR value, high resistivity and much improved matching as compared to implanted silicon or polysilicon resistors. Electrical characterization of SiCr thin film resistors fabricated in accordance with the present invention demonstrated voltage linearity better than 20 ppm/V and TCR of less than 100 ppm/°C.
  • TCR is defined as:
  • FIG. 15 demonstrates TCl and TC2 as a function of the anneal temperature. As can be seen in FIG. 15, as the anneal temperature increases, TCl linearly increases and TC2 decreases over the range. When increasing the anneal treatment from 400 0 C to 450 0 C, TCl changed from 103 ppm/°C at 400 0 C to 126 ppm/°C at 450 0 C and TC2 from -0.99 to -1.04 ppm/°C 2 . Thus, the lower the anneal temperature, the better the TCR value. Optimal TCR was achieved at a temperature of about 400C. Rs also increases as a function of anneal temperature.
  • FIG. 16 compares the normalized SiCr TCR with polysilicon resistors as a function of temperature (-50 0 C to 150 0 C).
  • SiCr film data was taken from the 9.8x400 ⁇ m SiCr thin film resistor, with the SiCr thin film resistor fabricated in accordance with the present invention under optimized PVD deposition conditions.
  • anneal temperature is an important factor for controlling TCR and stabilizing the SiCr thin film resistor.
  • the SiCr thin film resistor has a positive linear coefficient TCl whereas polysilicon resistors have a negative coefficient TCl.
  • FIG. 17 shows the normalized resistance of SiCr and polysilicon resistors as a function of bias. Bias voltage was varied in a range of -10 to 10 V, with the SiCr data also taken from the 9.8x400 ⁇ m SiCr thin film resistor. The electrical properties are summarized in Table 2, which clearly shows that SiCr thin film resistors produced in accordance with the present invention demonstrate much improved electrical properties over polysilicon resistors.
  • the present invention can be used to produce SiCr thin film resistors having the following characteristics: 1) a wide Rs range of 400 - 2500 ohms/sq and a high resistivity range of 3588 - 13,000 ⁇ -cm.

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Abstract

The present invention provides integrated SiCr metal thin film resistors (10) for SiGe RF BiCMOS technology. The use of integrated SiCr thin film resistors (10) increases packaging density and reduces the parasitic effect induced from surface mount configurations at high frequencies. In accordance with the present invention, the sheet resistance (Rs) of SiCr thin film resistors can be varied in a wide range of about 400 - 2500 ohms/square with less than 2% uniformity by selectively controlling SiCr deposition conditions. In addition, SiCr thin film resistors formed in accordance with the present invention have linear and quadratic coefficients of TCR less than about 100 ppml°C and -0.9 ppm/°C2, respectively.

Description

INTEGRATED SiCr METAL THIN FILM RESISTORS FOR SiGe RF-BiCMOS TECHNOLOGY
The present invention relates in general to semiconductor devices. More particularly, the present invention is directed to the formation of integrated SiCr metal thin film resistors for SiGe RF-BiCMOS (Radio Frequency Bipolar Complementary Metal Oxide Semiconductor) technology.
The emergence of wireless communications and the startling growth of corresponding high-frequency usage into the millimeter wave regime have brought new demands not only for increased performance but also for simultaneous decreases in the size of packages and modules. These demands require a highly integrated package and module technology for high-frequency applications. The use of integrated passive components such as thin film resistors can significantly reduce the surface-mount parasitic effect at high frequencies, increase packaging density, and improve manufacturability. This drives the need for improvements in RF and analog performance of the passive components necessary for system level integration of wireless applications. Future technology generations require integrated RF thin film resistors with high precision resistivity, low TCR (Temperature Coefficient of Resistance), high linearity, low noise, and improved matching as compared to implanted silicon or polysilicon resistors. The materials usually used to produce integrated metal thin-film resistors such as TaN, NiCr, and TaSi however, have a significant drawback in that their sheet resistance values are limited to less than 150 - 200 ohms/square.
The present invention provides integrated SiCr metal thin film resistors for SiGe RF BiCMOS technology. The use of integrated SiCr thin film resistors increases packaging density and reduces the parasitic effect induced from surface mount configurations at high frequencies. In accordance with the present invention, the sheet resistance of SiCr thin film resistors can be varied in a wide range of about 400 - 2500 ohms/square with less than 2% uniformity by selectively controlling SiCr deposition conditions. In addition, SiCr thin film resistors formed in accordance with the present invention have linear and quadratic coefficients of TCR less than about 100 ppm/°C and -0.9 ppm/°C2, respectively.
A first aspect of the present invention is directed to a method for forming an SiCr metal thin film resistor, comprising: depositing a film of SiCr on a planarized surface of a dielectric substrate; annealing the SiCr film; applying a photoresist to the SiCr film; patterning the photoresist using a single mask to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor; wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 ohms/square. A second aspect of the present invention is directed to a semiconductor structure comprising: an SiCr metal thin film resistor having a sheet resistance of greater than about 400 ohms/square.
A third aspect of the present invention is directed to a method for forming an SiCr metal thin film resistor, comprising: depositing a film of SiCr on a planarized surface of a dielectric substrate; annealing the SiCr film; applying a photoresist to the SiCr film; patterning the photoresist using a single mask to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor; wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 - 2500 ohms/square, a temperature coefficient of resistance (TCR) linear and quadratic coefficients of less than about 100 ppm/°C and -0.9 ppm/°C2, respectively, and a resistivity in a range of about 3,588 - 13,000 μΩ-cm.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
FIG. 1 is an SEM (scanning electron microscope) cross-section of an SiCr thin film resistor produced in accordance with an embodiment of the present invention.
FIGS. 2-8 illustrate a process for forming an SiCr thin film resistor in accordance with an embodiment of the present invention.
FIGS. 9 and 10 illustrate the sheet resistance of SiCr films under different annealing conditions.
FIG. 1 1 illustrates the influence of argon flow on SiCr film deposition. FIG. 12 illustrates SiCr sheet resistance as a function of deposition RF power.
FlG. 13 illustrates SiCr sheet resistance as a function of reciprocal thickness.
FIG. 14 illustrates the measured resistance of various SiCr thin film resistors fabricated in accordance with the present invention. FIG. 15 illustrates TCl and TC2 coefficients of TCR as a function of anneal temperature.
FIG. 16 illustrates the normalized TCR of SiCr and polysilicon resistors as a function of temperature.
FIG. 17 illustrates the normalized resistance of SiCr and polysilicon resistors as a function of bias.
It should be noted that the drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention.
Referring to FIG. 1, there is illustrated an SEM (scanning electron microscope) cross-section of an SiCr metal thin film resistor 10 produced in accordance with an embodiment of the present invention. The SiCr thin film resistor 10 is formed on a high-density planarized dielectric substrate 12 comprising, for example, silicon dioxide (SiO2). The SiCr thin film resistor 10 is directly connected to an upper metal level 14 by vias 16.
A method for forming an SiCr thin film resistor 10 in accordance with an embodiment of the present invention is illustrated with reference to FIGS. 2-8.
In FIG. 2, there is illustrated a high-density dielectric substrate 12, which includes various metal layers 14 (e.g., M2, M3) interconnected by vias 16. The metal layers 14 and vias 16 are formed using conventional photolithographic techniques. The dielectric substrate 12 can be formed, for example, using a high density plasma (HDP) chemical vapor deposition (CVD) process. Other suitable techniques including, for example, plasma enhanced tetraethylorthosilicate (PETEOS) and selective area chemical vapor deposition (SACVD), can also be used.
The dielectric substrate 12 is planarized (FIG. 3) prior to the deposition of an SiCr film. Planarization may be provided, for example, using known CMP (chemical- mechanical polishing) techniques. Thereafter, a film of SiCr 18 is deposited on the planarized surface 20 of the dielectric substrate 12. The SiCr RlE (reactive ion etch) process window in a later step is improved because the SiCr is deposited on the planarized surface 20 of the dielectric substrate 12.
The SiCr film 18 is deposited on the planarized surface 20 of the dielectric substrate 12 using PVD (physical vapor deposition) of a SiCr target 21 (shown in phantom) in argon/oxygen gases. In order to obtain high resistivity and low TCR, high Si contents are used with Cr in the target 21 , for example, 72 wt% Si and 28 wt% Cr. The deposition rate of the SiCr film 18 can be varied, depending on the RF power, gas flow, and chamber pressure used during deposition. The thickness of the SiCr film 18 can be varied to achieve a desired sheet resistance value of the SiCr film 18. A post-deposition anneal is then performed in a temperature range of 380 - 5000C.
Next, as shown in FlG. 4, a single mask step is used to define the SiCr thin film resistor. This provides an advantage over other materials typically used to fabricate integrated metal thin film resistors, including TaN, NiCr, and TaSi, which require more than one masking level. A layer of photoresist 22 is applied to the SiCr film 18 and patterned using a single mask 23 (shown in phantom). The photoresist 22 can be applied, for example, using spin coating or other suitable techniques. The resultant structure is illustrated in FIG. 4.
A plasma dry etching of the SiCr thin film 18 is then performed using a mixed chemistry of C12/BC13/SF6 to form an SiCr thin film resistor 10. Other suitable etchant chemistries including, for example, CF4/CHF3, can also be used. The resultant structure after stripping the photoresist 22 is illustrated in FIG. 5. In accordance with the present invention, the sheet resistance of the SiCr thin film resistor 10 can be varied in a wide range of about 400 - 2500 ohms/square with less than 2% uniformity by selectively controlling SiCr deposition conditions. In addition, the SiCr thin film resistor 10 formed in accordance with the present invention has linear and quadratic coefficients of TCR less than about 100 ppm/°C and -0.9 ppm/°C2, respectively.
As shown in FIG. 6, an additional dielectric layer 24 is then deposited (e.g., using an HDP-CVD process) on the planarized surface 20 of the dielectric substrate 12 and the SiCr thin film resistor 10. The dielectric layer 24 is then planarized and patterned using known techniques. Thereafter, as shown in FIGS. 7 and 8, metal plugs 16 are formed in a known manner to connect the SiCr thin film resistor 10 with later formed top metal interconnects 14. Example
A DOE (Design of Experiments) of the SiCr deposition was performed. The purpose of the DOE was to understand the process conditions for SiCr deposition and anneal in order to establish a manufacturable process. The SiCr film thickness was varied as necessary to achieve the desired sheet resistance. The DOE involved various SiCr deposition process parameters such as RF power, gas flow, and deposition pressure followed by various anneals temperatures. Table 1 lists the process window of the SiCr deposition DOE and how each process parameter affected the deposition of the SiCr film. It was found that a low power, low pressure, and adequate Ar/O ratio are needed to maintain a stable SiCr deposition process.
Table 1
Figure imgf000007_0001
FIGS. 9 and 10 show sheet resistance (Rs) data of SiCr films: as-deposited and after anneal at different temperatures. For both processes, Rs changed as the anneal temperature. This change indicates that the crystallization of SiCr was advanced by the thermal anneal. The results demonstrate that the SiCr film as deposited is a composite amorphous/crystalline. The thermal anneal temperature changes resistance and thus suitability for use in an integrated passives structures. For SiCr film deposited without a Halo generator, the resistivity varied in a range of 5,000 - 13,000 μΩ-cm.
It was found that at low power and at low pressure, an adequate Ar/O flow ratio is necessary to maintain a stable SiCr deposition process window. The oxygen content is an important parameter to achieve a stable SiCr deposition with low TCR value, although the process window for oxygen flow rate is narrow. High oxygen content will lead to a high anneal temperature that is needed to convert the SiCr film, which makes the resistivity conversion more difficult. SiCr deposition was unstable at a high oxygen flow or at a higher oxygen ratio that was larger than 10%. It should be noted that the Rs increased with thermal anneal as shown in FIG. 10 as contrasted to Rs values as shown in FIG. 9. The difference between the two results from the use of a Halo generator in the low RF power SiCr deposition process. For both SiCr deposition processes, within-in-wafer uniformity was improved after anneal. For the Halo generator, the wafer-to-wafer SiCr thickness variation was much improved and the within-in-wafer uniformity was reduced from 4 - 5% to less than 2% (1 sigma). It was determined that use of the Halo generator influenced the SiCr film in four ways: (1) improved the SiCr film uniformity; (2) improved TCR; (3) stabilized the deposition process; and (4) changed the resistivity.
FIG. 11 summarizes the influence of the argon flow on SiCr film deposition, while maintaining all other SiCr deposition parameters unchanged (SiCr film annealed at 4200C for 60 minutes). As shown, the Rs and thickness of the SiCr film linearly changed as the argon flow. The correlation between Rs and thickness as a function of argon flow indicates that the argon flow does not affect the composition of SiCr film. FIG. 12 shows Rs as a function of deposition RF power. As RF power increases, the Rs of the SiCr film decreased in the range of 1000 - 2000 ohms/square. Thus, RF power affects the Rs of the SiCr film. This correlation allows the fabrication of a wide range of SiCr thin film resistors without changing the composition of the SiCr target (i.e., by changing the deposition RF power). To determine the influence of RF deposition power on SiCr film property, the deposition time was varied to change the SiCr film thickness. As shown in FIG. 13, the Rs of the SiCr film changed as a function of the reciprocal thickness for different RF deposition powers (using data from Halo generator deposition). The extrapolated resistivity of SiCr film ranged from about 3588 - 13,000 μΩ-cm. Low RF power SiCr deposition showed a higher resistivity than a high RF power deposition. The data indicates that RF power affects the composition (e.g., the resistivity) of SiCr film.
FIG. 14 shows the measured resistance of various SiCr thin film resistors (in the range of 1.7x4 μm2 to 9.8x400 μm2) that were fabricated in accordance with the present invention. The SiCr thin film resistors show a good linear resistance variation as a function of width and length in a wide range up to 100k ohms. The SiCr thin film resistors also exhibit low TCR value, high resistivity and much improved matching as compared to implanted silicon or polysilicon resistors. Electrical characterization of SiCr thin film resistors fabricated in accordance with the present invention demonstrated voltage linearity better than 20 ppm/V and TCR of less than 100 ppm/°C.
As known in the art, TCR is defined as:
R^ = l + TC. χ (T - 27) + TC2 χ (T - 27)2
R(ITC) ' 2
TCR gives information about how much nominal resistance can be changed with temperature. FIG. 15 demonstrates TCl and TC2 as a function of the anneal temperature. As can be seen in FIG. 15, as the anneal temperature increases, TCl linearly increases and TC2 decreases over the range. When increasing the anneal treatment from 4000C to 4500C, TCl changed from 103 ppm/°C at 4000C to 126 ppm/°C at 4500C and TC2 from -0.99 to -1.04 ppm/°C2. Thus, the lower the anneal temperature, the better the TCR value. Optimal TCR was achieved at a temperature of about 400C. Rs also increases as a function of anneal temperature. Factors believed to contribute the change of SiCr film electrical properties include film oxidation and composite. The anneal treatment oxidizes the film and alters the composite of amorphous and crystallization. 4000C anneal treatment increased the SiCr resistance by less than 4%. The stability of SiCr film with respect to the temperature change, is desirable for wireless applications. FIG. 16 compares the normalized SiCr TCR with polysilicon resistors as a function of temperature (-500C to 1500C). SiCr film data was taken from the 9.8x400 μm SiCr thin film resistor, with the SiCr thin film resistor fabricated in accordance with the present invention under optimized PVD deposition conditions. As shown in FIG. 16, anneal temperature is an important factor for controlling TCR and stabilizing the SiCr thin film resistor. The SiCr thin film resistor has a positive linear coefficient TCl whereas polysilicon resistors have a negative coefficient TCl.
FIG. 17 shows the normalized resistance of SiCr and polysilicon resistors as a function of bias. Bias voltage was varied in a range of -10 to 10 V, with the SiCr data also taken from the 9.8x400 μm SiCr thin film resistor. The electrical properties are summarized in Table 2, which clearly shows that SiCr thin film resistors produced in accordance with the present invention demonstrate much improved electrical properties over polysilicon resistors.
Table 2
Figure imgf000010_0001
In summary, it has been found that the present invention can be used to produce SiCr thin film resistors having the following characteristics: 1) a wide Rs range of 400 - 2500 ohms/sq and a high resistivity range of 3588 - 13,000 μΩ-cm.
2) a low TCR value, < 100 ppm/°C TCl and -0.9 ppm/°C2 TC2.
3) desirable resistivity and TCR can be obtained/adjusted by controlling deposition/anneal conditions. The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.

Claims

CLAIMS:
1. A method for forming an SiCr metal thin film resistor (10), comprising: depositing a film (18) of SiCr on a planarized surface of a dielectric substrate
(12); annealing the SiCr film; applying a photoresist (22) to the SiCr film; patterning the photoresist using a single mask (23) to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor (10); wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 ohms/square.
2. The method of claim 1, further comprising: depositing an additional dielectric layer (24) over the SiCr metal thin film resistor; planarizing a surface of the additional dielectric layer; and forming conductive vias (16) from the SiCr metal thin film resistor to the surface of the additional dielectric layer.
3. The method of claim 1, further comprising:
> selectively controlling the deposition and anneal conditions for the SiCr film to provide a sheet resistance in the range of about 400 - 2500 ohms/square.
4. The method of claim 1, further comprising: selectively controlling the deposition and anneal conditions for the SiCr film to provide temperature coefficient of resistance (TCR) linear and quadratic coefficients of less than about 100 ppm/°C and -0.9 ppm/°C2, respectively.
5. The method of claim 1, further comprising: selectively controlling the deposition and anneal conditions for the SiCr film to provide a resistivity in a range of about 3,588 - 13,000 μΩ-cm.
6. The method of claim 1, wherein the deposition conditions comprise deposition power, chamber pressure, and gas flow during deposition.
7. The method of claim 1, wherein the anneal conditions comprise anneal temperature.
8. The method of claim 1 , further comprising: selectively controlling deposition conditions to vary a thickness of the SiCr film.
9. The method of claim 1 , wherein the film of SiCr is deposited on the planarized surface of the dielectric substrate using an SiCr target (21) in argon/oxygen gases, wherein the SiCr target comprises about 72 wt% Si and 28 wt% Cr.
10. A semiconductor structure comprising: an SiCr metal thin film resistor (10) having a sheet resistance of greater than about 400 ohms/square.
1 1. The semiconductor structure of claim 10, wherein the SiCr metal thin film resistor has temperature coefficient of resistance (TCR) linear and quadratic coefficients of less than about 100 ppm/°C and -0.9 ppm/°C2, respectively.
12. The semiconductor structure of claim 10, wherein the SiCr metal thin film resistor has a sheet resistance in the range of about 400 - 2500 ohms/square.
13. The semiconductor structure of claim 10, wherein the SiCr metal thin film resistor has a resistivity in a range of about 3,588 - 13,000 μΩ-cm.
14. A method for forming an SiCr metal thin film resistor (10), comprising: depositing a film (18) of SiCr on a planarized surface of a dielectric substrate
(12); annealing the SiCr film; applying a photoresist (22) to the SiCr film; patterning the photoresist using a single mask (23) to define an SiCr thin film resistor; and etching the SiCr film to form the SiCr metal thin film resistor (10); wherein deposition and anneal conditions for the SiCr film are selectively controlled to provide a sheet resistance of greater than about 400 - 2500 ohms/square, a temperature coefficient of resistance (TCR) linear and quadratic coefficients of less than about 100 ppm/°C and -0.9 ppm/°C2, respectively, and a resistivity in a range of about 3,588 - 13,000 μΩ-cm.
15. The method of claim 14, wherein the deposition conditions comprise deposition power, chamber pressure, and gas flow during deposition.
16. The method of claim 14, wherein the anneal conditions comprise anneal temperature.
17. The method of claim 14, further comprising: selectively controlling deposition conditions to vary a thickness of the SiCr film.
18. The method of claim 14, wherein the film of SiCr is deposited on the planarized surface of the dielectric substrate using an SiCr target (21) in argon/oxygen gases, wherein the SiCr target comprises about 72 wt% Si and 28 wt% Cr.
PCT/IB2005/053126 2004-09-28 2005-09-22 Integrated sicr metal thin film resistors for sige rf-bicmos technology WO2006035377A2 (en)

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