WO2006033086A2 - Method of making shallow semiconductor junctions - Google Patents

Method of making shallow semiconductor junctions Download PDF

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Publication number
WO2006033086A2
WO2006033086A2 PCT/IB2005/053157 IB2005053157W WO2006033086A2 WO 2006033086 A2 WO2006033086 A2 WO 2006033086A2 IB 2005053157 W IB2005053157 W IB 2005053157W WO 2006033086 A2 WO2006033086 A2 WO 2006033086A2
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Prior art keywords
major surface
phosphorous
doping
peak
nm
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PCT/IB2005/053157
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French (fr)
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WO2006033086A3 (en )
Inventor
Raymond J. Duffy
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Koninklijke Philips Electronics N.V.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Phosphorous ions 6 are implanted into a first major surface 4 of a silicon body 2 to render the first major surface amorphous. Then the silicon body is annealed at a temperature of not greater than 800°C. It has been discovered that the phosphorous 6 diffuses towards the first major surface 4 making the junction shallower.

Description

1 PHGB040196

DESCRIPTION

METHOD OF MAKING SHALLOW SEMICONDUCTOR JUNCTIONS

The invention relates to a method of making shallow junctions to semiconductors.

Electrical contacts to the source and drain of semiconductor devices are conventionally made by implanting ions into the appropriate region of the semiconductor devices. Arsenic or phosphorus implants are used as n-type dopants and boron implants as p-type. However, such implantation causes significant crystal damage, including silicon interstitials, the latter being silicon atoms displaced by the ion bombardment. In order to repair the damage to the crystal structure and to activate the dopants, high temperature annealing is carried out. However, this annealing causes the dopants to diffuse resulting in a deep source or drain junction.

As semiconductor device sizes get smaller and smaller the thickness of regions in semiconductor needs to get thinner, especially the low doped source and drain regions in field effect transistors. It therefore becomes increasingly necessary to make very shallow junctions in order to be able to contact such thin regions.

Both n and p-type junctions are required. Arsenic is often favoured as a dopant for forming highly active very shallow and very steep n-type doping profiles in silicon due to its relatively high solubility, heavy mass an low diffusivity. Boron may be used for p-type doping.

A number of approaches to producing such shallow junctions have been proposed.

One approach is to use rapid thermal annealing, especially spike annealing or impulse annealing, to minimise diffusion. A number of such processes, and their disadvantages, are discussed in

WO2004/010470, which also proposes a solution in the form of a two step annealing process, the first being a fast anneal and the second a longer 2 PHGB040196

anneal at a lower temperature. This is said to significantly increase dopant stability.

A different approach is proposed in US 6,074,937. In this, multiple ion implantations are carried out to form a non-amorphous region well below the surface, and a vacancy rich region between the non-amorphous region and the surface. Then, boron is implanted in such a way that the silicon interstitials are formed at a similar depth to the vacancy rich region. The intention is that during subsequent thermal annealing the vacancies absorb the silicon interstitials. However, this approach is complicated and requires multiple implantations that all need to be very precisely controlled.

A paper by Downey and Jones, "The role of extended defects on the formation of ultra-shallow junctions in ion implanted 11B+, 49BF2, 75As+ and 31P+", 1999 IEEE, shows that ion implants at energies below a threshold do not create interstitials, and it is suggested that by implanting below this energy there is complete freedom of rapid thermal annealing conditions. Further, studies of the rapid thermal annealing and in particular spike anneals showed how the annealing process can be optimised for 11B+ and 49BF2 implants. The paper accordingly suggested implantation below the threshold energy to avoid diffusion effects caused by interstitials. Specific proposals for forming shallow junctions using boron dopant are presented by Downey in US 6,069,062 and US 6,087,247.

However, all of these processes simply reduce the effects of the thermal annealing. A further line of enquiry has been suggested by Duffy et al in "Boron uphill diffusion during ultrashallow junction formation", Applied Physics Letters, Volume 82 number 21 (2003), and Wang et al in "Interface induced uphill diffusion of boron, an effective approach for ultrashallow junction", in IEEE electronic device letters volume 22 number 2 (2001). In his paper, boron is shown to produce shallower junctions after annealing using an anomalous "transient enhanced annealing". 3 PHGB040196

However, in CMOS devices ultrashallow profiles are needed for both n- type dopants as well as p-type dopants.

There thus remains a need for an improved method of forming shallow junctions to semiconductors.

According to the invention there is provided a method of forming a junction to a semiconductor device at a first major surface, comprising: rendering the semiconductor device amorphous at the first major surface and implanting phosphorus into the semiconductor device at the first major surface using ion implantation; and annealing the semiconductor device at a temperature of not greater than 800°C and diffusing the implanted phosphorous preferentially towards the first major surface.

The inventor has discovered that by rendering the silicon surface amorphous and then annealing at a lower temperature than used for rapid thermal annealing the dopant ions diffuse towards the surface, which can in turn make the diffused junction shallower. As will be appreciated, in conventional devices diffusion spreads the implanted dopant atoms and hence makes the junction deeper. As far as the inventor is aware, this is the first time that preferential diffusion towards the surface making the junction shallower has been observed for phosphorus, or indeed any n-type dopant, in silicon. In the prior art, annealing has been observed to make the junction deeper as dopants diffuse away from the surface. Accordingly, the method according to the invention allows shallower junctions to be obtained. The first major surface is preferably rendered amorphous by the implantation of phosphorous. Results presented later show that this gives better results than rendering the surface amorphous and then implanting phosphorous. However amorphisation can also be performed by pre-implanting with a heavy neutral element such as Si, Ge, Sn or Pb. 4 PHGB040196

In particular embodiments the step of implanting phosphorous atoms implants phosphorous atoms having a doping profile having an initial peak concentration at a depth in the range 0 nm to 5 nm at or below the first major surface and having a doping concentration at a depth of 3 nm below the initial peak of at least 10% of the initial peak doping concentration, and the step of annealing diffuses the phosphorous atoms to have a doping having an annealed peak concentration at a depth in the range 0 nm to 2 nm at or below the first major surface and having a doping concentration at a depth of 3 nm below the annealed peak of less than 10% of the annealed peak doping concentration.

Thus, in the annealed state, the doping concentration at a depth of 3nm below the peak is very much less than that at the peak. Accordingly, very shallow junctions are obtained.

The step of implanting phosphorous may implant phosphorous atoms to have a doping profile having an initial peak doping concentration of 1x1020 cm" 3 to 1 x 1022 cm"3, and the step of annealing may diffuse the phosphorous atoms to have a doping having an annealed peak concentration at least 1.5 times the initial peak concentration.

Thus, the method according to the invention can increase the doping concentration at the peak just below the surface significantly. The phosphorous may be implanted at an energy in the range 0.5 to 5keV, and in preferred embodiments 1 KeV to 2 KeV, or in particular embodiments at an energy in the range 1.3 KeV to 1.7 KeV. The step of implanting phosphorous may be carried out with a dose of 1x1014 cm"2 to 1x1016 cm"2, in particular embodiments with a dose of 3x1014 cm"2 to 1.5x1015 cm"2. The step of annealing may be carried out at a temperature of 650 to 7500C for a period in the range ten seconds to two hours.

In another aspect, the invention relates to a shallow junction semiconductor comprising: a silicon body having a first major surface; and a shallow junction highly doped with phosphorous at the first major surface, wherein the phosphorous doping has a doping profile with an 5 PHGB040196

annealed peak concentration at a depth in the range 0 nm to 2 nm at or below the first major surface and a doping concentration at a depth of 3 nm below the annealed peak of less than 10% of the annealed peak doping concentration.

For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a schematic drawing of a semiconductor device after an ion implantation step in a method according to the invention; Figure 2 is a graph of the doping profile as a function of depth for different annealing times in a first embodiment of a method according to the invention;

Figure 3 is a graph of the doping profile as a function of depth for different annealing times in a second embodiment of a method according to the invention; and

Figure 4 is a graph of the doping profile as a function of depth for different annealing times in a third embodiment of a method according to the invention.

A silicon semiconductor substrate 2 having a first major surface 4 was placed in an ion implanter and phosphorous ions 6 were implanted to form an initial doping profile 8 represented schematically by the dotted lines (Figure 1). A first experiment was carried out implanting phosphorous ions with an energy of 1.5keV at a first dose of 4x1014 cm'2 into a 200mm Czorchralski grown <100> oriented p-type silicon wafer. This step both rendered the wafer amorphous at the first major surface and implanted phosphorous.

The resulting initial doping profile is shown by the solid line in Figure 2.

It will be noted that the doping profile has a peak approximately 1 nm below the surface with a concentration of a little over 1021 cm'3, and that there is a fairly long tail with the doping at a depth of 5nm being over 5x1020 cm"3 and the doping not falling below 1020 cm"3 until a depth of about 7nm.

A second experiment was carried out at a second dose of 1x1015 cm"2 and the resulting initial doping profile is shown by the solid line in Figure 3. 6 PHGB040196

The results are very similar except that the doping concentrations are higher.

It will be noted that the doping profile has a peak approximately 1nm below the surface with a concentration of a little over 2x1021 cm'3, and that there is a fairly long tail with the doping at a depth of 5nm being approximately 1021 cm"3 and the doping not falling below 1020 cm'3 until a depth of about 8nm.

Annealing was then performed at a temperature of 700 0C for periods between 10 s and 2 hours in an inert nitrogen ambient. This results in an annealed doping profile. As shown by arrow 10 in Figure 1 , the doping diffuses preferentially towards first major surface 4. The dopant profiles shown in the figures were using a 2MeV He+ beam. obtained using time of flight secondary ion mass spectrometry (SIMS)

Figure 2 shows the annealed doping profile for an annealing time of 10s

(circles) and 2 hours (crosses). It will be seen that even after 10s a significant increase is obtained in the peak doping concentration and a reduction is obtained in the doping concentrations at depths below 2nm, and these effeccts are much larger after two hours. Indeed, after two hours the annealed peak doping concentration exceeds 2x1021 cm"3 and has already fallen to less than

1021 cm"3 at a depth of 3.5nm below the surface.

Note that the depth of the amorphous layer at the first major surface as implanted was about 7nm, so movement of phosphorous towards the surface also occurs below the amorphous-crystalline interface.

Similar results were obtained in the second experiment as shown in

Figure 3 for an annealing time of 10s (circles), 15 minutes (dashes signs) and

2 hours (crosses). It will be seen that the annealing is substantially complete after 15 minutes by which time the annealed peak doping concentration is already over 3x1021 cm"3 and the doping concentration at 5nm is only around

1020 cm"3 at a depth of 5nm.

The surface was examined in a transmission electron microscope after

10s, 15 minute and 2 hours annealing times and it was observed that after 10s annealing there remained a large number of small silicon interstitial defects.

No discernable defects were observed after 15 minutes or two hours. 7 PHGB040196

Without wishing to be bound by theory the inventor assumes that the phosphorous dopant atoms may be trapped preferentially near the first major surface.

It will therefore be seen that in both experiments the doping atoms preferentially diffused towards the first major surface. The inventor is unaware of any previous evidence that phosphorous can drive a preferential diffusion movement towards the surface.

The annealed diffusion profiles combine high dopant concentration and shallowness and may accordingly be used for making shallow contacts, for example to thin semiconductor devices.

For example, as shown in Figure 1 , the doping regions 8 may define source and drain regions and a gate insulator 12 and gate 14 provided between the source and drain regions to finish the transistor. The skilled person will be aware of many different semiconductor structures, and details, and any of these may be adopted.

In a third embodiment, a preamorphising implant (PAI) was used. The PAI was of germanium of dose 1.2x1015 cm"2 and energy of 15keV. This was followed by a phosphorous dose of 4x1014 cm'2 as for the first embodiment. The results are presented in Figure 4. It can be seen from Figure 4 that a similar effect occurs as in the first and second embodiments, but that the effect is significantly less. The use of the logarithmic scale on the figures makes the differences between Figures 2 and 4 less immediately appararent. Nevertheless, the difference is quite significant. For example after 2 hours the position of the concentration of 1020 cm"3 has shifted 1.5nm towards the surface in Figure 4 (third embodiment) but has shifted 3.5nm towards the surface in Figure 2 (first embodiment).

Thus the results suggest that the results are best with a self- amorphising phosphorous implant as in the first and second embodiments where the phosphorous itself renders the surface amorphous, but that some useful effect is still obtained using a pre-amorphising implant as in the third embodiment. 8 PHGB040196

The invention is not limited to the embodiments discussed above, but parameters, especially process parameters, may be varied if required to obtain different required doping concentrations and depths. Instead of silicon substrates, SiGe, Ge or even IN-V substrates may be used.

Claims

9 PHGB040196CLAIMS
1. A method of forming a junction to a semiconductor device at a first major surface (4), comprising: rendering the semiconductor device amorphous at the first major surface (4) and implanting phosphorus (6) into the semiconductor device at the first major surface using ion implantation; and annealing the semiconductor device at a temperature of not greater than 8000C and diffusing the implanted phosphorous preferentially towards the first major surface.
2. A method according to claim 1 including wherein rendering the semiconductor device amorphous at the first major surface (4) and implanting phosphorous (6) are carried out in a single step by implanting phosphorous (6) into the first major surface to render the semiconductor device amorphous at the first major surface (4).
3. A method according to claim 1 or 2 wherein the semiconductor device has a silicon substrate (2).
4. A method according to any preceding claim wherein: the step of implanting phosphorous atoms (6) implants phosphorous atoms having a doping profile having an initial peak concentration in the range 0 nm to 5 nm at or below the first major surface (4) and having a doping concentration at a depth of 3 nm below the initial peak of at least 10% of the initial peak doping concentration, and the step of annealing diffuses the phosphorous atoms (6) to have a doping having an annealed peak concentration at a depth in the range 0 nm to 2 nm at or below the first major surface (4) and having a doping concentration at a depth of 3 nm below the annealed peak of less than 10% of the annealed peak doping concentration. 10 PHGB040196
5. A method according to any preceding claim wherein: the step of implanting phosphorous atoms (6) implants phosphorous atoms to have a doping profile having an initial peak doping concentration of 1x1020 cm" 3 to 1 x 1022 cm"3, and the step of annealing diffuses the phosphorous atoms (6) to have a doping having an annealed peak concentration at least 1.5 times the initial peak concentration.
6. A method according to any preceding claim wherein the step of implanting phosphorous (6) is carried out by ion implantation at an energy in the range 1 KeV to 2 KeV.
7. A method according to any preceding claim wherein the step of implanting phosphorous (6) is carried out with a dose of 1x1014 cm"2 to 1x1016 cm"2.
8. A method according to any preceding claim wherein the step of annealing is carried out at a temperature of 650 to 75O0C for a period in the range five minutes to two hours.
9. A method according to any preceding claim wherein the phosphorous is implanted into source and drain regions of the semiconductor device and wherein an insulated gate is provided between the source and the drain regions to form an insulated gate transistor.
10. A shallow junction semiconductor comprising: a silicon body (2) having a first major surface (4); and a shallow junction highly doped with phosphorous (6) at the first major surface, wherein the phosphorous doping has a doping profile with an annealed peak concentration at a depth in the range 0 nm to 2 nm at or below the first major surface (4) and a doping concentration at a depth of 3 nm below 11 PHGB040196
the annealed peak of less than 10% of the annealed peak doping concentration.
PCT/IB2005/053157 2004-09-25 2005-09-23 Method of making shallow semiconductor junctions WO2006033086A3 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057700A1 (en) * 2016-10-13 2018-04-20 Commissariat A Lenergie Atomique Et Aux Energies Alternatives Process for manufacturing a device having an oxide layer based on oxide of phosphorus on the surface of a semiconductor material

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4584026A (en) * 1984-07-25 1986-04-22 Rca Corporation Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
US6225176B1 (en) * 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
US6472282B1 (en) * 2000-08-15 2002-10-29 Advanced Micro Devices, Inc. Self-amorphized regions for transistors
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6630386B1 (en) * 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4584026A (en) * 1984-07-25 1986-04-22 Rca Corporation Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
US6225176B1 (en) * 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
US6630386B1 (en) * 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6472282B1 (en) * 2000-08-15 2002-10-29 Advanced Micro Devices, Inc. Self-amorphized regions for transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057700A1 (en) * 2016-10-13 2018-04-20 Commissariat A Lenergie Atomique Et Aux Energies Alternatives Process for manufacturing a device having an oxide layer based on oxide of phosphorus on the surface of a semiconductor material
FR3057699A1 (en) * 2016-10-13 2018-04-20 Commissariat A Lenergie Atomique Et Aux Energies Alternatives Method of fabricating an oxide layer, at room temperature by ion implantation, a base of phosphorus oxide on the surface of a semiconductor material

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GB0421407D0 (en) 2004-10-27 grant
WO2006033086A3 (en) 2006-09-08 application

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