WO2006025034A2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2006025034A2
WO2006025034A2 PCT/IB2005/052872 IB2005052872W WO2006025034A2 WO 2006025034 A2 WO2006025034 A2 WO 2006025034A2 IB 2005052872 W IB2005052872 W IB 2005052872W WO 2006025034 A2 WO2006025034 A2 WO 2006025034A2
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WO
WIPO (PCT)
Prior art keywords
diode
component
electrode
semiconductor
region
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Application number
PCT/IB2005/052872
Other languages
French (fr)
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WO2006025034A3 (en
Inventor
Steven T. Peake
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Koninklijke Philips Electronics N.V.
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Publication of WO2006025034A2 publication Critical patent/WO2006025034A2/en
Publication of WO2006025034A3 publication Critical patent/WO2006025034A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to semiconductor devices, and more particularly to improving the on-state characteristics of semiconductor devices.
  • the present invention provides a semiconductor device including a semiconductor body, the body comprising a unipolar semiconductor component body having at least two main electrodes in contact therewith, and a PiN diode body with one electrode in contact therewith connected to a main electrode of the s component body.
  • a bias potential is applied to the other electrode of the diode such that it is forward biased when the component is in its on-state.
  • the PiN diode serves to improve the on-state characteristics of the semiconductor component.
  • the semiconductor component may be a MOS device, or a Schottky diode, for 0 example.
  • the semiconductor component body is a trench- gate MOS field effect transistor (hereinafter "TrenchMOS device") body.
  • the diode area of the device may be demarcated from the transistor area by a trench extending into the semiconductor body from its top major surface.
  • An electrode may 5 be provided in the trench which is connected to the gate of the TrenchMOS device.
  • the electrode may be connected to the source of the TrenchMOS device, as this has been found to reduce the power dissipation of the device.
  • the semiconductor component body is a planar gate field effect transistor body.
  • the device may include a terminal connected to the other electrode of the PiN diode which is electrically separate from the terminals connected to the main electrodes of the component body.
  • the other electrode of the PiN diode may be connected to the gate of the transistor via resistance means. In such a configuration, a separate, dedicated terminal is not required for the PiN diode.
  • Figure 1 is a cross-sectional side view of part of a semiconductor body comprising trench-gate transistor cell areas and a PiN diode area in accordance with an embodiment of the invention
  • Figure 2 is a cross-sectional side view of part of a semiconductor body comprising planar gate transistor cell areas and a PiN diode area in accordance with a second embodiment of the invention
  • Figure 3 is a graph of simulated specific on-resistance against diode anode voltage for a number of devices having the configuration shown in Figure 1 ;
  • Figure 4 is a graph showing a plot of simulated specific on-resistance against nominal breakdown voltage for a device having the configuration shown in Figure 1 , at different diode anode voltages;
  • Figure 5 shows a circuit diagram of a three terminal semiconductor device comprising a field effect transistor and a PiN diode according to a third embodiment o of the invention.
  • Figures 1 and 2 are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the 5 drawings. The same reference signs have generally been used to refer to corresponding or similar features in each embodiment.
  • Figure 1 illustrates a first exemplary embodiment of a semiconductor device according to the invention.
  • the active area of a device semiconductor body 10 comprises a unipolar semiconductor component, in the form of trench-gate o transistor cells 8, and at least one PiN diode cell 6.
  • the semiconductor body has top and bottom major surfaces 10a, 10b, respectively.
  • the trench-gate cell configuration shown in Figure 1 by way of example is known in itself and may be fabricated in a known manner. Source and drain regions, 13 and 14, 14a, respectively, of a first conductivity type (n-type in this example) are separated by a channel-accommodating body region 15 of the opposite second conductivity type (that is, p-type in this example).
  • a gate 11 is present in a trench 20 which extends through the regions 13 and 15 into an underlying portion of the drain drift region 14.
  • the gate is insulated from the semiconductor body 10 by a layer 17 of insulating material.
  • the application of a voltage signal to gate 11 in the on-state of the device serves in a known manner for inducing a conduction channel 12 in the region 15 and for controlling current flow in this conduction channel 12 between the source and drain regions 13 and 14, 14a.
  • An insulating overlayer 18 is provided over the gate 11.
  • the source region 13 is contacted by a first main, source electrode (not shown, but illustrated schematically by source terminal 21) at the top major surface 10a of the device body.
  • the drain region comprises a drain drift region 14 formed by an epitaxial layer on a drain contact, substrate region 14a.
  • the drain drift region 14 and substrate region 14a are of the same conductivity type (n-type in this example), with the substrate region being more highly doped than the drain drift region.
  • the substrate region 14a is contacted at the bottom major surface 10b of the device body by a second main, drain electrode (not shown, illustrated by drain terminal 24), which also forms the cathode of the PiN diode.
  • the lateral extent of the source regions 13 away from the gate trenches 20 is defined by a so-called moat etch step, which defines a groove 25 extending from the top major surface 10a into the channel- accommodating region 15. It will be appreciated that this is merely an optional feature of the transistor structure, and that the scope of the present invention is not limited to the specific transistor arrangement illustrated.
  • a second embodiment is shown in Figure 2, in which the semiconductor component body is a planar gate field effect transistor body.
  • the active area of the device comprises planar gate transistor cells 29, together with at least one PiN diode cell 6.
  • the planar gate cell configuration of Figure 2 is that of a known vertical DMOS transistor and may be fabricated in a known manner.
  • the gate, conduction channel, source regions, channel-accommodating body region and gate insulating layer are identified by reference numerals 11', 12', 13', 15' and 17', respectively.
  • a PiN diode is formed by anode region 27, drain drift region 14, and drain contact region 14a.
  • Anode region 27 is of the second conductivity type (p-type in this example, in which the PiN diode is combined with an n-channel MOSFET) and its peak p-type doping level is higher than that of the channel-accommodating region 15'.
  • the drain contact region 14a forms the cathode region of the diode, and the drain electrode is connected to the cathode region of the diode.
  • Anode region 27 extends to the top major surface 10a of the device body and is contacted there by an anode electrode (not shown, but represented schematically by anode terminal 23).
  • anode electrode not shown, but represented schematically by anode terminal 23.
  • TrenchMOS device illustrated in Figure 1 the p-region of the diode and the channel- accommodating region of the MOSFET are isolated from each other by a trench 7.
  • An electrode 9 is provided in the trench between the diode and MOSFET which is connected to the gate terminal 22 of the MOSFET. Alternatively, the electrode may be connected to the source of the MOSFET, which serves to achieve a greater reduction in the total power dissipation of the device.
  • the on-state characteristics of the PiN diode serve to improve the on-state characteristics of the associated semiconductor component, and in particular its specific on-resistance.
  • the anode voltage of the PiN diode is made positive with respect to its cathode and hence the drain of the TrenchMOS device or planar gate FET, respectively.
  • the pn junction formed between anode region 27 and the drain drift region 14 becomes forward biased, and minority carriers (holes in this example) are injected into the drift region. If the anode voltage is increased further, the injected minority carrier density increases, until high-level injection occurs. High-level injection occurs when the injected minority carrier density exceeds the background doping of the drift region.
  • the proposed structure enables the achievement of low on-state voltage drops o and the current carrying capability at high voltages found in bipolar devices, without suffering the secondary breakdown that is inherent in bipolar devices when supporting high currents and voltages simultaneously.
  • the cells may have a square geometry, a close- packed hexagonal geometry, or an elongate stripe geometry.
  • a device may comprise many hundreds of parallel cells. Simulations have suggested that diode cells in a device of the invention may only need to occupy 1-2% of the active area of a device. The diode area could extend around the perimeter of the component area, or be localised in a particular convenient region (or regions) of the semiconductor body.
  • diode cells are provided adjacent to a large proportion (and preferably, substantially all) of the component cells of the device.
  • the device could be arranged so that each component cell is in contact with a diode cell.
  • each component stripe could have a diode cell stripe extending alongside it.
  • the active area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes (also not shown).
  • various known circuits (such as gate-control circuits) may be integrated with the device in an area of the body 10 between the active cellular area and the peripheral termination scheme.
  • the circuit elements may be fabricated with their own layout in this circuit area using some of the same masking and doping steps as are used for the active area.
  • Anode region 27 of the PiN diode shown in Figures 1 and 2 is formed by implantation of acceptor dopant ions, for example, of boron, using a dedicated implantation mask.
  • the peak doping level of the anode region is around 1 x 10 19 atoms/cm 3 or more. Preferably, it is around 5 x 10 19 atoms/cm 3 .
  • the associated trench-gate device may be configured to block voltages in the range 40-1000 volts for example.
  • a high dopant concentration in the anode region serves to minimise power dissipation. It leads to increased conductivity modulation, and a smaller total diode area can be used as the lateral extent of the conductivity modulation increases with the dopant concentration level.
  • Figure 3 shows a graph illustrating a simulated plot of specific on-resistance against anode voltage for a number of devices having the configuration shown in Figure 1.
  • the devices have differing doping levels in the drain drift region, giving different breakdown voltage ratings.
  • the gate electrode was biased at 10 volts, and the anode bias was increased from 0.4 volts to 1.1 volts. It can be seen that anode voltages of around 0.9 volts and above create sufficient minority carrier injection into the drain region from the anode region to cause a substantial reduction in on-resistance.
  • the graph of Figure 4 shows plots of specific on-resistance against nominal breakdown voltage for a device of the configuration shown in Figure 1 , with the diode anode electrode grounded and biased at 1.1 volts, respectively. It can be seen that where the anode bias is 1.1 volts, the specific on-resistance of the device varies approximately linearly with nominal breakdown voltage. Furthermore, the on- state performance benefits of the device increase with increasing breakdown voltage.
  • the anode electrode of the PiN diode may be biased independently of the electrodes of the associated semiconductor component in the semiconductor body. In that case, the device may include an additional terminal connected to the anode of the PiN diode.
  • the anode electrode 32 of the PiN diode 34 may be connected to the gate 36 of the transistor via resistance means 38. Incorporation of the PiN diode does not therefore require an additional device terminal.
  • the value of the resistance may be in the range 10 to 10 6 Ohms, for example, and in use the value is selected to apply the desired voltage to the anode of the PiN diode. Preferably, resistance is in the region of 10 Ohms.
  • electrons are the majority carriers, and an electron inversion channel 12 is induced in p-type region 15 by the gate 11.
  • a p-channel component can be combined with a PiN diode having an n-type region at the top major surface of the semiconductor body, over a p-type drain drift region and drain contact region.

Abstract

A semiconductor device comprises a unipolar semiconductor component and a PiN diode. The semiconductor body of the device comprises a component body of the component having at least two main electrodes (21, 24) in contact therewith, and a diode body of the PiN diode, the diode body having two electrodes (23, 24) in contact therewith. One of the diode electrodes (24) is connected to a main electrode of the component body, and a bias potential is applicable to the other diode electrode (23) such that it is forward biased when the component is in its on state. The PiN diode serves to improve the on-state characteristics of the semiconductor component. The semiconductor component may be a MOS device, or a Schottky diode, for example.

Description

DESCRIPTION
SEMICONDUCTOR DEVICE
s The present invention relates to semiconductor devices, and more particularly to improving the on-state characteristics of semiconductor devices.
In many semiconductor devices, a significant cause of power losses is conduction losses associated with the on-state resistance of the device. 0
The present invention provides a semiconductor device including a semiconductor body, the body comprising a unipolar semiconductor component body having at least two main electrodes in contact therewith, and a PiN diode body with one electrode in contact therewith connected to a main electrode of the s component body. In use, a bias potential is applied to the other electrode of the diode such that it is forward biased when the component is in its on-state. The PiN diode serves to improve the on-state characteristics of the semiconductor component.
The semiconductor component may be a MOS device, or a Schottky diode, for 0 example.
In a preferred embodiment, the semiconductor component body is a trench- gate MOS field effect transistor (hereinafter "TrenchMOS device") body. The diode area of the device may be demarcated from the transistor area by a trench extending into the semiconductor body from its top major surface. An electrode may 5 be provided in the trench which is connected to the gate of the TrenchMOS device. Alternatively, the electrode may be connected to the source of the TrenchMOS device, as this has been found to reduce the power dissipation of the device.
In another embodiment, the semiconductor component body is a planar gate field effect transistor body. o The device may include a terminal connected to the other electrode of the PiN diode which is electrically separate from the terminals connected to the main electrodes of the component body. Alternatively, in embodiments where the component is a transistor, the other electrode of the PiN diode may be connected to the gate of the transistor via resistance means. In such a configuration, a separate, dedicated terminal is not required for the PiN diode.
5 Embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings wherein:
Figure 1 is a cross-sectional side view of part of a semiconductor body comprising trench-gate transistor cell areas and a PiN diode area in accordance with an embodiment of the invention; o Figure 2 is a cross-sectional side view of part of a semiconductor body comprising planar gate transistor cell areas and a PiN diode area in accordance with a second embodiment of the invention;
Figure 3 is a graph of simulated specific on-resistance against diode anode voltage for a number of devices having the configuration shown in Figure 1 ; s Figure 4 is a graph showing a plot of simulated specific on-resistance against nominal breakdown voltage for a device having the configuration shown in Figure 1 , at different diode anode voltages; and
Figure 5 shows a circuit diagram of a three terminal semiconductor device comprising a field effect transistor and a PiN diode according to a third embodiment o of the invention.
It should be noted that Figures 1 and 2 are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the 5 drawings. The same reference signs have generally been used to refer to corresponding or similar features in each embodiment.
Figure 1 illustrates a first exemplary embodiment of a semiconductor device according to the invention. The active area of a device semiconductor body 10 comprises a unipolar semiconductor component, in the form of trench-gate o transistor cells 8, and at least one PiN diode cell 6. The semiconductor body has top and bottom major surfaces 10a, 10b, respectively. The trench-gate cell configuration shown in Figure 1 by way of example is known in itself and may be fabricated in a known manner. Source and drain regions, 13 and 14, 14a, respectively, of a first conductivity type (n-type in this example) are separated by a channel-accommodating body region 15 of the opposite second conductivity type (that is, p-type in this example). A gate 11 is present in a trench 20 which extends through the regions 13 and 15 into an underlying portion of the drain drift region 14. The gate is insulated from the semiconductor body 10 by a layer 17 of insulating material. The application of a voltage signal to gate 11 in the on-state of the device (via a gate terminal shown schematically as terminal 22) serves in a known manner for inducing a conduction channel 12 in the region 15 and for controlling current flow in this conduction channel 12 between the source and drain regions 13 and 14, 14a. An insulating overlayer 18 is provided over the gate 11.
The source region 13 is contacted by a first main, source electrode (not shown, but illustrated schematically by source terminal 21) at the top major surface 10a of the device body. The drain region comprises a drain drift region 14 formed by an epitaxial layer on a drain contact, substrate region 14a. The drain drift region 14 and substrate region 14a are of the same conductivity type (n-type in this example), with the substrate region being more highly doped than the drain drift region. The substrate region 14a is contacted at the bottom major surface 10b of the device body by a second main, drain electrode (not shown, illustrated by drain terminal 24), which also forms the cathode of the PiN diode.
In the illustrated configuration, the lateral extent of the source regions 13 away from the gate trenches 20 is defined by a so-called moat etch step, which defines a groove 25 extending from the top major surface 10a into the channel- accommodating region 15. It will be appreciated that this is merely an optional feature of the transistor structure, and that the scope of the present invention is not limited to the specific transistor arrangement illustrated.
A second embodiment is shown in Figure 2, in which the semiconductor component body is a planar gate field effect transistor body. The active area of the device comprises planar gate transistor cells 29, together with at least one PiN diode cell 6. The planar gate cell configuration of Figure 2 is that of a known vertical DMOS transistor and may be fabricated in a known manner. The gate, conduction channel, source regions, channel-accommodating body region and gate insulating layer are identified by reference numerals 11', 12', 13', 15' and 17', respectively. In the embodiments shown in Figures 1 and 2, a PiN diode is formed by anode region 27, drain drift region 14, and drain contact region 14a. Anode region 27 is of the second conductivity type (p-type in this example, in which the PiN diode is combined with an n-channel MOSFET) and its peak p-type doping level is higher than that of the channel-accommodating region 15'. Thus, the drain contact region 14a forms the cathode region of the diode, and the drain electrode is connected to the cathode region of the diode.
Anode region 27 extends to the top major surface 10a of the device body and is contacted there by an anode electrode (not shown, but represented schematically by anode terminal 23). In the preferred embodiment of a device combining a PiN diode and
TrenchMOS device illustrated in Figure 1 , the p-region of the diode and the channel- accommodating region of the MOSFET are isolated from each other by a trench 7. An electrode 9 is provided in the trench between the diode and MOSFET which is connected to the gate terminal 22 of the MOSFET. Alternatively, the electrode may be connected to the source of the MOSFET, which serves to achieve a greater reduction in the total power dissipation of the device.
As will be discussed below, the on-state characteristics of the PiN diode serve to improve the on-state characteristics of the associated semiconductor component, and in particular its specific on-resistance. In use of the embodiments of Figures 1 and 2, the anode voltage of the PiN diode is made positive with respect to its cathode and hence the drain of the TrenchMOS device or planar gate FET, respectively. Above a certain anode voltage, the pn junction formed between anode region 27 and the drain drift region 14 becomes forward biased, and minority carriers (holes in this example) are injected into the drift region. If the anode voltage is increased further, the injected minority carrier density increases, until high-level injection occurs. High-level injection occurs when the injected minority carrier density exceeds the background doping of the drift region.
If the injected minority carrier density is substantially greater than the drift region doping level, charge neutrality of the drift region requires that the
5 concentration of minority and majority carriers in it is equal. To equalise the minority and majority carrier density, majority carriers (electrons in this example) are injected into the drift region from the drain contact region 14a. This phenomenon is called conductivity modulation and is used in bipolar technologies to achieve high current carrying capability at low drift region voltage drops. o Whereas in MOS technologies, the on-state voltage drop across the drift region causes the specific on-resistance to increase with forward blocking voltage not linearly, but as a power function, conductivity modulation allows the on-state voltage drop of bipolar technology to be approximately linearly proportional to forward blocking voltage. This mechanism is exploited by the present invention. s By merging a PiN diode with a unipolar semiconductor device, the increase in majority current density due to the application of a sufficient anode voltage to the diode results in a drift region that exhibits a voltage drop substantially independent of the background doping concentration.
The proposed structure enables the achievement of low on-state voltage drops o and the current carrying capability at high voltages found in bipolar devices, without suffering the secondary breakdown that is inherent in bipolar devices when supporting high currents and voltages simultaneously.
It will be appreciated that before a device of the form described herein can block any forward voltage, excess minority carriers must be swept out before 5 depletion regions can evolve. Thus for high frequency applications, it may for example be necessary to apply a negative anode bias prior to forward blocking to extract the minority carriers resulting in a reduced storage time for these carriers.
No plan view of the cellular layout geometry is shown in the drawings, as the structure proposed herein may be formed in a range of quite different, known cell o geometries. Thus, for example, the cells may have a square geometry, a close- packed hexagonal geometry, or an elongate stripe geometry. A device may comprise many hundreds of parallel cells. Simulations have suggested that diode cells in a device of the invention may only need to occupy 1-2% of the active area of a device. The diode area could extend around the perimeter of the component area, or be localised in a particular convenient region (or regions) of the semiconductor body. It is considered that implementation of the claimed invention will be particularly effective if diode cells are provided adjacent to a large proportion (and preferably, substantially all) of the component cells of the device. For example, the device could be arranged so that each component cell is in contact with a diode cell. In an elongate stripe geometry, each component stripe could have a diode cell stripe extending alongside it. The active area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes (also not shown). Furthermore, various known circuits (such as gate-control circuits) may be integrated with the device in an area of the body 10 between the active cellular area and the peripheral termination scheme. Typically, the circuit elements may be fabricated with their own layout in this circuit area using some of the same masking and doping steps as are used for the active area.
Anode region 27 of the PiN diode shown in Figures 1 and 2 is formed by implantation of acceptor dopant ions, for example, of boron, using a dedicated implantation mask. Typically, the peak doping level of the anode region is around 1 x 1019 atoms/cm3 or more. Preferably, it is around 5 x 1019 atoms/cm3. The associated trench-gate device may be configured to block voltages in the range 40-1000 volts for example. A high dopant concentration in the anode region serves to minimise power dissipation. It leads to increased conductivity modulation, and a smaller total diode area can be used as the lateral extent of the conductivity modulation increases with the dopant concentration level.
Figure 3 shows a graph illustrating a simulated plot of specific on-resistance against anode voltage for a number of devices having the configuration shown in Figure 1. The devices have differing doping levels in the drain drift region, giving different breakdown voltage ratings. In each case, the gate electrode was biased at 10 volts, and the anode bias was increased from 0.4 volts to 1.1 volts. It can be seen that anode voltages of around 0.9 volts and above create sufficient minority carrier injection into the drain region from the anode region to cause a substantial reduction in on-resistance.
The graph of Figure 4 shows plots of specific on-resistance against nominal breakdown voltage for a device of the configuration shown in Figure 1 , with the diode anode electrode grounded and biased at 1.1 volts, respectively. It can be seen that where the anode bias is 1.1 volts, the specific on-resistance of the device varies approximately linearly with nominal breakdown voltage. Furthermore, the on- state performance benefits of the device increase with increasing breakdown voltage. The anode electrode of the PiN diode may be biased independently of the electrodes of the associated semiconductor component in the semiconductor body. In that case, the device may include an additional terminal connected to the anode of the PiN diode. Alternatively, as illustrated by the circuit diagram shown in Figure 5, in embodiments where the component is a MOS transistor 30, the anode electrode 32 of the PiN diode 34 may be connected to the gate 36 of the transistor via resistance means 38. Incorporation of the PiN diode does not therefore require an additional device terminal. The value of the resistance may be in the range 10 to 106 Ohms, for example, and in use the value is selected to apply the desired voltage to the anode of the PiN diode. Preferably, resistance is in the region of 10 Ohms. In the particular examples described above in relation to Figures 1 and 2, electrons are the majority carriers, and an electron inversion channel 12 is induced in p-type region 15 by the gate 11. Forward biasing of the PiN diode injects holes into the drift region. By using opposite conductivity type dopants, it will be appreciated that a p-channel component can be combined with a PiN diode having an n-type region at the top major surface of the semiconductor body, over a p-type drain drift region and drain contact region.
From the present disclosure, many other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve other features which are already known in the art and which may be used instead of or in addition to features already disclosed herein. Although Claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention. Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The Applicants hereby give notice that new Claims may be formulated to such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom.

Claims

1. A semiconductor device comprising a unipolar semiconductor component and a PiN diode, the device including a semiconductor body (10), the body
5 comprising a component body of the component having at least two main electrodes (21, 24) in contact therewith, and a diode body of the PiN diode, the diode body having two electrodes (23, 24) in contact therewith, wherein one of the diode electrodes (24) is connected to a main electrode of the component body, and a bias potential is applicable to the other diode electrode (23) such that it is forward biased when the Q component is in its on state.
2. A device of claim 1 including a terminal (23) connected to the other diode electrode which is arranged to be biased independently of the main electrodes (21 , 24) of the component body. 5
3. A device of claim 1 wherein the component is a transistor (30), and the other diode electrode (23) is connected to the gate electrode (36) of the transistor via resistance means (38).
o 4. A device of any preceding claim wherein the component is a MOS device.
5. A device of any preceding claim wherein the component is a trench-gate FET. 5
6. A device of claim 5 wherein a diode area (6) of the device is demarcated from the transistor area (8) by a trench (7) extending into the semiconductor body (10) from its top major surface (10a).
0 7. A device of claim 6 wherein an electrode (9) is provided in the trench (7) which is connected to the gate electrode (11 ) of the FET.
8. A device of claim 6 wherein an electrode is provided in a perimeter trench which is connected to the source electrode (21 ) of the FET.
9. A device of any of claims 1 to 4 wherein the component is a planar gate FET.
10. A device of claim 1 or claim 2 wherein the component is a Schottky diode.
PCT/IB2005/052872 2004-09-03 2005-09-01 Semiconductor device WO2006025034A2 (en)

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