WO2006012110A2 - Integrated transistor module and method of fabricating same - Google Patents

Integrated transistor module and method of fabricating same Download PDF

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Publication number
WO2006012110A2
WO2006012110A2 PCT/US2005/021877 US2005021877W WO2006012110A2 WO 2006012110 A2 WO2006012110 A2 WO 2006012110A2 US 2005021877 W US2005021877 W US 2005021877W WO 2006012110 A2 WO2006012110 A2 WO 2006012110A2
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WIPO (PCT)
Prior art keywords
low
transistor
land
side land
integrated
Prior art date
Application number
PCT/US2005/021877
Other languages
French (fr)
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WO2006012110A3 (en
Inventor
Rajeev D. Joshi
Jonathan A. Noquil
Consuelo N. Tangpuz
Original Assignee
Fairchild Semiconductor Corporation
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Filing date
Publication date
Application filed by Fairchild Semiconductor Corporation filed Critical Fairchild Semiconductor Corporation
Priority to KR1020067027196A priority Critical patent/KR101167742B1/en
Priority to CN2005800211001A priority patent/CN101015056B/en
Priority to JP2007518193A priority patent/JP4999684B2/en
Priority to DE112005001457T priority patent/DE112005001457T5/en
Publication of WO2006012110A2 publication Critical patent/WO2006012110A2/en
Publication of WO2006012110A3 publication Critical patent/WO2006012110A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates generally to semiconductor devices. More particularly, the present invention relates to an integrated transistor module that is suitable for use as a building block for other devices, including synchronous buck converters.
  • Synchronous buck converters shift DC voltage levels in order to provide power to programmable grid arrays integrated circuits, microprocessors, digital signal processing integrated circuits and other circuits, while stabilizing battery outputs, filtering noise, and reducing ripple.
  • Synchronous buck converters are also used to provide high-current multiphase power in a wide range of date communications, telecom, point-of-load and computing applications.
  • Fig. 1 shows a simplified schematic diagram of a typical synchronous buck converter.
  • Synchronous buck convert (SBC) 10 includes a high-side metal oxide
  • MOSFET 12 00010495 semiconductor field effect transistor (MOSFET) 12 and a low-side MOSFET 14.
  • the drain D of low-side MOSFET 14 is electrically connected to the source S of high-side MOSFET 12.
  • Most commercial-produced MOSFETs are vertical devices, and are packaged such that the external points of connection to the gate, drain and source are on the same geographic plane of the device.
  • connection between the source S and drain D of the high and low-side MOSFETs 12 and 14, respectively, in SBC 10 must have a very low inductance in order for SBC 10 to be used at moderate to high operating/switching frequencies.
  • MOSFETs 12 and 14 are configured as discrete devices, the design of the circuit board layout of SBC 10 must be optimized to reduce parasitic inductances.
  • SBC 10 can be configured as a fully-integrated synchronous buck converter in a single package and which is designed and laid out to reduce parasitic inductances in the connection between the source S and drain D of the high and low- side MOSFETs 12 and 14, respectively.
  • a non-application specific buck converter having a reduced-inductance or low-inductance connection between the source of the high-side MOSFET and the drain of the low-side MOSFET and which is capable of carrying moderate to high current.
  • 00010495 building block that provides a connection between the source of a high-side transistor of the module and the drain of a low-side transistor of the module that is capable of carrying moderate to high current and has a reduced or low inductance, and is therefore suitable for use as a building block for the design/construction of a buck converter for use at moderate/high frequencies.
  • a method of forming a buck converter that is suitable for use a thigh frequencies by using an integrated transistor module or building block having a reduced or low inductance connection between the source of a high-side transistor of the module and the drain of a low-side transistor of the module, and which is capable of carrying moderate to high current.
  • the present invention provides an integrated transistor module that provides a low-inductance high-current capacity connection between the transistors, and is useful as a building block for other circuitry, such as, for example, buck converters.
  • the invention comprises, in one form thereof, an integrated transistor module including a lead frame that defines at least one low-side land and at least one high-
  • a stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands.
  • a low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land.
  • a high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.
  • An advantage of the p ⁇ esent invention is that an integrated transistor module is provided that includes a low-inductance high-current-capacity connection between the drain of one transistor and the source of another, and which is therefore useful as a building block for a buck converter.
  • Another advantage of the present invention is that the integrated transistor module is easily and efficiently heat sinked.
  • a still further advantage of the present invention is that the integrated transistor module is formed from devices using modular/standard packages, and is therefore fabricated according to an efficient process flow.
  • An even further advantage of the present invention is that the integrated transistor module simplifies the layout and design of printed circuit boards.
  • Yet another advantage of the present invention is that the integrated transistor module can be used in scalable multi-phase DC-DC converter devices.
  • an advantage of the present invention is that the integrated transistor module reduces component counts in DC/DC converter devices.
  • FIG. 1 is a schematic diagram of an exemplary synchronous buck converter
  • FIG. 2 illustrates the functional modules of the synchronous buck converter of
  • FIG. 3 is a side view of one embodiment of an integrated FET module of the present invention.
  • FIG. 4 is a side view of a second embodiment of an integrated FET module of the present invention.
  • FIGS. 5A-5C show top views of one embodiment of a lead frame for a third embodiment of an integrated FET module of the present invention, and the method of fabricating same;
  • FIGS. 6A-6G illustrate one embodiment of a method for fabricating one embodiment of an integrated FET module of the present invention.
  • FIG. 1 there is shown a schematic diagram of an exemplary synchronous buck converter. As discussed
  • synchronous buck converter (SBC) 10 includes a high-side metal oxide semiconductor field effect transistor (MOSFET) 12 and a low-side MOSFET 14.
  • MOSFET metal oxide semiconductor field effect transistor
  • the drain D of low-side MOSFET 14 is electrically connected to the source S of high-side MOSFET 12.
  • the gates G of MOSFETs 12 and 14 are connected to corresponding outputs (not referenced) of a pulse-width modulation (PWM) controller 20.
  • PWM pulse-width modulation
  • the integrated FET module of the present invention integrates the circuitry within circle 22, including MOSFETs 12 and 14.
  • Integrated transistor module 30 includes high- and low-side transistors 12 and 14, substrate or lead frame 32, molding 34, and heat sink 36.
  • the high-and low-side transistors 12 and 14 such as, for example, field effect transistors (FETs) or metal oxide semiconductor field effect transistors (MOSFETs), are disposed upon and coupled to substrate or lead frame 32 which provides a low-inductance electrical connection between the drain D of low-side FET 14 and the source S of high-side FET 12, and thus an integrated transistor module 30 that is suitable for use as a building block for other circuits, such as, for example, a buck converter.
  • FETs field effect transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • High- and low-side FETS 12 and 14 are conventional integrated-circuit MOSFET devices, and are selected so as to be suitable for the application for which integrated FET module 30 is intended.
  • high-side FET 12 is configured as a flip-chip device/package
  • low-side FET 14 is configured as a BGA device/package.
  • Substrate or leadframe 32 is constructed of an electrically conductive material, such as, for example, copper or aluminum, and has a thickness of, for example, from approximately .005 to approximately 0.010 inches.
  • substrate 32 and moldings 34 define at least one high-side land pattern 42 and at least one low-side land pattern 44.
  • the portions of substrate 32 upon which land patterns 42 arid 44 are defined are i ⁇ tercohhe " cted * by a stepped portion 46 of " " " substrate 32.
  • Stepped portion 46 orients high-side land pattern 42 and low-side land pattern 44 in respective planes that are substantially parallel relative to each other.
  • Stepped portion 46 in conjunction with molding 34 dispose the high- and low-side FETS 12 and 14 in a substantially co-planar manner relative to each other.
  • Substrate 32 is half-etched to prepare a pattern on high-side land pattern 42 upon and to which high-side MOSFET 12 is mounted, that includes pad 48.
  • High-side FETs 12 are flip-chip mounted to corresponding high-side land patterns 42 and low-side FETs 14 are mounted using conventional processes for mounting BGA packages to corresponding low-side land patterns 44. More particularly, the drains D of each low-side FET 14 are attached to a corresponding low-side land pattern 44, and the sources S of each high-side FET 12 are flip-chip attached to high-side land pattern 42.
  • Moldings 34 are formed upon and cover the side of land patterns 44 opposite to the sides thereof to which high-side FETS 12 are attached.
  • a first or top surface 34A (Figs. 3 and 6B) of moldings 34 are formed to be substantially coplanar with first or upper surface 32A of substrate 32. Moldings 34 electrically isolate the drains and gates of the high-side FETS 12 from contact with or electrically shorting to heat sink
  • Heat sink 36 is attached in a thermally-conductive manner, such as, for example, a thermally conductive paste or solder paste, to first or upper surface 32A of substrate 32. Heat sink 36 extends the entire length and/or width of integrated FET module 30 since moldings 34 prevent shorting of the drains and gates of the high-side FETS 12 to heat sink 36. Heat sink 36 is constructed of a thermally- conductive material, such as, for example, a strip of copper or other suitable thermally-conductive material
  • Figs. 6A-6G illustrate one embodiment of a method for fabricating one embodiment of an integrated FET module of the present invention.
  • Preformed lead frame 32 is configured with mirror-image sides or halves, as shown in Fig. 6A, from each of which respective integrated FET modules 30 are formed.
  • Molded portions 34 are formed on each of the mirror-image halves of substrate 32, as shown in Fig 6B. Molded portions 34 cover stepped portion 46 and the side of low-side land 44 that is opposite to the side thereof upon which low-side FET 14 is mounted, and form top surfaces 34A that are substantially coplanar with first or upper surface 32A of substrate 32.
  • High-side FETS 12 are then flip-chip mounted onto high-side land patterns 42, as shown in Fig. 6C.
  • Solder balls 56 are formed on pads 48, which are later reflowed to electrically connect substrate 32, and thus source S of high-side FET 12 and drain D of low-side FET 14, of integrated FET module 30 to a circuit board or other device, as shown in Fig. 6D.
  • the low-side FETs 14 are then mounted by conventional BGA package attach to low-side lands 44 of substrate 32, as shown in Fig. 6E, and the two mirror-image
  • 00010495 halves are singulated, such as, for example, by punching (as shown in Fig. 6F) or by sawing (as shown in Fig. 6G).
  • each subassembly 60 includes one or more high-side FETs 12 mounted to corresponding high-side lands 42 of substrate 32 and isolated by corresponding moldings 34.
  • Substrate 32 a portion of which extends from moldings 34 and defines land 44, forms an embedded connector strip suitable for connecting the source of high-side FET 12 to another package or device, such as low-side FET 14.
  • substrate 32 can be alternately configured to connect virtually any other desired type of integrated circuit device and/or package to high-side FET 12.
  • substrate 32 shown in Figs. 5A-5C corresponds to an embodiment of integrated FET module 30 that includes two high-side FETS 12 and one low-side FET 14. Accordingly, in that embodiment, substrate 32 includes molding 34 which is disposed around the periphery of high-side land patterns 42 defined by substrate 32.
  • the sources S of respective high-side FETS 12 are flip- chip mounted to high-side land patterns 42 and low-side FET 14 is mounted as described above.
  • sources S of high-side FETS 12 are electrically connected via substrate 32 to the drain D of low-side FET 14 in a similar manner to that described above. This interconnection of the FET sources considerably simplifies the layout of the printed circuit board relative to the layout required for interconnecting discrete components.
  • integrated FET module 30 forms a building block for other circuitry, such as, for example, buck converters or other circuitry requiring two MOSFETs having the drain of one MOSFET connected the source of the other via substrate/leadframe 32 that is capable of carrying relatively high current and has a relatively low inductance.
  • the surfaces of integrated FET module 30 are substantially coplanar and thereby provide a device to which heatsink 36 is easily attached and/or integrated, and which has a larger surface area than would otherwise be possible since the high-side FET 12 is electrically isolated from heatsink 36 by molding 34 and thus the likelihood of FET 12 shorting to heatsink 36 is minimized.

Abstract

An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low­side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

Description

INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Patent Application Serial No. 10/876,248 filed June 24, 2004.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to an integrated transistor module that is suitable for use as a building block for other devices, including synchronous buck converters.
DESCRIPTION OF THE RELATED ART
Typically used in power supplies for cell phones, portable computers, digital cameras, routers, and other portable electronic systems, synchronous buck converters shift DC voltage levels in order to provide power to programmable grid arrays integrated circuits, microprocessors, digital signal processing integrated circuits and other circuits, while stabilizing battery outputs, filtering noise, and reducing ripple. Synchronous buck converters are also used to provide high-current multiphase power in a wide range of date communications, telecom, point-of-load and computing applications. Fig. 1 shows a simplified schematic diagram of a typical synchronous buck converter. Synchronous buck convert (SBC) 10 includes a high-side metal oxide
00010495 semiconductor field effect transistor (MOSFET) 12 and a low-side MOSFET 14. The drain D of low-side MOSFET 14 is electrically connected to the source S of high-side MOSFET 12. Most commercial-produced MOSFETs are vertical devices, and are packaged such that the external points of connection to the gate, drain and source are on the same geographic plane of the device.
The connection between the source S and drain D of the high and low-side MOSFETs 12 and 14, respectively, in SBC 10 must have a very low inductance in order for SBC 10 to be used at moderate to high operating/switching frequencies. Where MOSFETs 12 and 14 are configured as discrete devices, the design of the circuit board layout of SBC 10 must be optimized to reduce parasitic inductances. Alternatively, SBC 10 can be configured as a fully-integrated synchronous buck converter in a single package and which is designed and laid out to reduce parasitic inductances in the connection between the source S and drain D of the high and low- side MOSFETs 12 and 14, respectively. Such fully integrated devices, however, tend to be fairly application and/or design specific devices that are often not compatible with other applications and/or designs. Further, the printed circuit board traces/conductors that connect the MOSFETs are typically not well-suited to carrying moderate to high levels of current.
Therefore, what is needed in the art is a non-application specific buck converter having a reduced-inductance or low-inductance connection between the source of the high-side MOSFET and the drain of the low-side MOSFET and which is capable of carrying moderate to high current.
Furthermore, what is needed in the art is an integrated transistor module or
00010495 building block that provides a connection between the source of a high-side transistor of the module and the drain of a low-side transistor of the module that is capable of carrying moderate to high current and has a reduced or low inductance, and is therefore suitable for use as a building block for the design/construction of a buck converter for use at moderate/high frequencies.
Moreover, what is needed in the art is a "method of forming an integrated transistor module or building block that provides a reduced or low inductance connection between the source of a high-side transistor of the module and the drain of a low-side transistor of the module that is capable of carrying moderate to high current, and thereby enables the design/construction of a buck converter for use at high frequencies.
Still further, what is needed in the art is a method of forming a buck converter that is suitable for use a thigh frequencies by using an integrated transistor module or building block having a reduced or low inductance connection between the source of a high-side transistor of the module and the drain of a low-side transistor of the module, and which is capable of carrying moderate to high current.
SUMMARY OF THE INVENTION
The present invention provides an integrated transistor module that provides a low-inductance high-current capacity connection between the transistors, and is useful as a building block for other circuitry, such as, for example, buck converters.
The invention comprises, in one form thereof, an integrated transistor module including a lead frame that defines at least one low-side land and at least one high-
00010495 side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.
An advantage of the pϊesent invention is that an integrated transistor module is provided that includes a low-inductance high-current-capacity connection between the drain of one transistor and the source of another, and which is therefore useful as a building block for a buck converter. Another advantage of the present invention is that the integrated transistor module is easily and efficiently heat sinked.
A still further advantage of the present invention is that the integrated transistor module is formed from devices using modular/standard packages, and is therefore fabricated according to an efficient process flow. An even further advantage of the present invention is that the integrated transistor module simplifies the layout and design of printed circuit boards.
Yet another advantage of the present invention is that the integrated transistor module can be used in scalable multi-phase DC-DC converter devices.
Moreover, an advantage of the present invention is that the integrated transistor module reduces component counts in DC/DC converter devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The above-mentioned and other features and advantages of this invention,
00010495 and the manner of attaining them, will become apparent and be better understood by reference to the following description of one embodiment of the invention in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of an exemplary synchronous buck converter; FIG. 2 illustrates the functional modules of the synchronous buck converter of
Fig. 1;
FIG. 3 is a side view of one embodiment of an integrated FET module of the present invention;
FIG. 4 is a side view of a second embodiment of an integrated FET module of the present invention; and
FIGS. 5A-5C show top views of one embodiment of a lead frame for a third embodiment of an integrated FET module of the present invention, and the method of fabricating same; and
FIGS. 6A-6G illustrate one embodiment of a method for fabricating one embodiment of an integrated FET module of the present invention.
Corresponding reference characters indicate corresponding parts throughout the several views. The exemplifications set out herein illustrate one preferred embodiment of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.
DETAILED DESCRIPTION OF THE DRAWINGS Referring now to the drawings and particularly to Fig. 1 , there is shown a schematic diagram of an exemplary synchronous buck converter. As discussed
00010495 above, synchronous buck converter (SBC) 10 includes a high-side metal oxide semiconductor field effect transistor (MOSFET) 12 and a low-side MOSFET 14. The drain D of low-side MOSFET 14 is electrically connected to the source S of high-side MOSFET 12. Further, the gates G of MOSFETs 12 and 14 are connected to corresponding outputs (not referenced) of a pulse-width modulation (PWM) controller 20. As best shown in Fig. 2, the integrated FET module of the present invention integrates the circuitry within circle 22, including MOSFETs 12 and 14.
Referring now to Figs. 3 and 4, a side view of one embodiment of an integrated transistor module of the present invention is shown before (Fig. 4) and after (Fig. 3) singulation. Integrated transistor module 30 includes high- and low-side transistors 12 and 14, substrate or lead frame 32, molding 34, and heat sink 36. Generally, the high-and low-side transistors 12 and 14, such as, for example, field effect transistors (FETs) or metal oxide semiconductor field effect transistors (MOSFETs), are disposed upon and coupled to substrate or lead frame 32 which provides a low-inductance electrical connection between the drain D of low-side FET 14 and the source S of high-side FET 12, and thus an integrated transistor module 30 that is suitable for use as a building block for other circuits, such as, for example, a buck converter.
High- and low-side FETS 12 and 14 are conventional integrated-circuit MOSFET devices, and are selected so as to be suitable for the application for which integrated FET module 30 is intended. In the embodiment shown, high-side FET 12 is configured as a flip-chip device/package, and low-side FET 14 is configured as a BGA device/package.
00010495 Substrate or leadframe 32 is constructed of an electrically conductive material, such as, for example, copper or aluminum, and has a thickness of, for example, from approximately .005 to approximately 0.010 inches. Generally, substrate 32 and moldings 34 define at least one high-side land pattern 42 and at least one low-side land pattern 44. The portions of substrate 32 upon which land patterns 42 arid 44 are defined are iήtercohhe"cted*by a stepped portion 46 of " " " substrate 32. Stepped portion 46 orients high-side land pattern 42 and low-side land pattern 44 in respective planes that are substantially parallel relative to each other. Stepped portion 46 in conjunction with molding 34 dispose the high- and low-side FETS 12 and 14 in a substantially co-planar manner relative to each other.
Substrate 32 is half-etched to prepare a pattern on high-side land pattern 42 upon and to which high-side MOSFET 12 is mounted, that includes pad 48.
High-side FETs 12 are flip-chip mounted to corresponding high-side land patterns 42 and low-side FETs 14 are mounted using conventional processes for mounting BGA packages to corresponding low-side land patterns 44. More particularly, the drains D of each low-side FET 14 are attached to a corresponding low-side land pattern 44, and the sources S of each high-side FET 12 are flip-chip attached to high-side land pattern 42.
Moldings 34 are formed upon and cover the side of land patterns 44 opposite to the sides thereof to which high-side FETS 12 are attached. A first or top surface 34A (Figs. 3 and 6B) of moldings 34 are formed to be substantially coplanar with first or upper surface 32A of substrate 32. Moldings 34 electrically isolate the drains and gates of the high-side FETS 12 from contact with or electrically shorting to heat sink
00010495 36 (see Figs 3 and 4).
Heat sink 36 is attached in a thermally-conductive manner, such as, for example, a thermally conductive paste or solder paste, to first or upper surface 32A of substrate 32. Heat sink 36 extends the entire length and/or width of integrated FET module 30 since moldings 34 prevent shorting of the drains and gates of the high-side FETS 12 to heat sink 36. Heat sink 36 is constructed of a thermally- conductive material, such as, for example, a strip of copper or other suitable thermally-conductive material
Figs. 6A-6G illustrate one embodiment of a method for fabricating one embodiment of an integrated FET module of the present invention. Preformed lead frame 32 is configured with mirror-image sides or halves, as shown in Fig. 6A, from each of which respective integrated FET modules 30 are formed. Molded portions 34 are formed on each of the mirror-image halves of substrate 32, as shown in Fig 6B. Molded portions 34 cover stepped portion 46 and the side of low-side land 44 that is opposite to the side thereof upon which low-side FET 14 is mounted, and form top surfaces 34A that are substantially coplanar with first or upper surface 32A of substrate 32. High-side FETS 12 are then flip-chip mounted onto high-side land patterns 42, as shown in Fig. 6C. Solder balls 56 are formed on pads 48, which are later reflowed to electrically connect substrate 32, and thus source S of high-side FET 12 and drain D of low-side FET 14, of integrated FET module 30 to a circuit board or other device, as shown in Fig. 6D.
The low-side FETs 14 are then mounted by conventional BGA package attach to low-side lands 44 of substrate 32, as shown in Fig. 6E, and the two mirror-image
00010495 halves are singulated, such as, for example, by punching (as shown in Fig. 6F) or by sawing (as shown in Fig. 6G).
It should be particularly noted that singulation of integrated FET modules 30 at the stage of fabrication shown in Fig. 6D forms two subassemblies 60. Each subassembly 60 includes one or more high-side FETs 12 mounted to corresponding high-side lands 42 of substrate 32 and isolated by corresponding moldings 34. Substrate 32, a portion of which extends from moldings 34 and defines land 44, forms an embedded connector strip suitable for connecting the source of high-side FET 12 to another package or device, such as low-side FET 14. Although presented as connecting high-side FET 12 to low-side FET 14, substrate 32 can be alternately configured to connect virtually any other desired type of integrated circuit device and/or package to high-side FET 12.
The embodiment of substrate 32 shown in Figs. 5A-5C corresponds to an embodiment of integrated FET module 30 that includes two high-side FETS 12 and one low-side FET 14. Accordingly, in that embodiment, substrate 32 includes molding 34 which is disposed around the periphery of high-side land patterns 42 defined by substrate 32. The sources S of respective high-side FETS 12 are flip- chip mounted to high-side land patterns 42 and low-side FET 14 is mounted as described above. Thus, sources S of high-side FETS 12 are electrically connected via substrate 32 to the drain D of low-side FET 14 in a similar manner to that described above. This interconnection of the FET sources considerably simplifies the layout of the printed circuit board relative to the layout required for interconnecting discrete components.
00010495 In use, integrated FET module 30 forms a building block for other circuitry, such as, for example, buck converters or other circuitry requiring two MOSFETs having the drain of one MOSFET connected the source of the other via substrate/leadframe 32 that is capable of carrying relatively high current and has a relatively low inductance. The surfaces of integrated FET module 30 are substantially coplanar and thereby provide a device to which heatsink 36 is easily attached and/or integrated, and which has a larger surface area than would otherwise be possible since the high-side FET 12 is electrically isolated from heatsink 36 by molding 34 and thus the likelihood of FET 12 shorting to heatsink 36 is minimized.
While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the present invention using the general principles disclosed herein. Further, this application is intended to cover such departures from the present disclosure as come within the known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.
10
00010495

Claims

What is Claimed:
1. An integrated transistor module, comprising: a lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands; a low-side transistor mounted upon said low-sideland, a drain of said transistor being electrically connected to said low-side land; and a high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land.
2. The integrated transistor module of claim 1 , wherein said lead frame comprises a conductive metal.
3. The integrated transistor module of claim 2, wherein said low-side and said high-side transistor comprise metal oxide semiconductor field effect transistors.
4. The integrated transistor module of claim 2, wherein said high-side transistor is flip-chip mounted to said high-side land.
5. The integrated transistor module of claim 2, wherein said low-side transistor is contained within a ball grid array package, said package being mounted to said low-side land.
11
00010495
6. The integrated transistor module of claim 2, further comprising a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.
7. The integrated transistor module of claim 6, further comprising a heat sink thermally coupled to the side of said substrate opposite said high-side land and thereby to said low-side and said high-side transistors.
8. The integrated transistor of claim 7, wherein said heat sink extends over said molded portion.
9. A synchronous buck converter, comprising: an integrated subassembly including a lead frame, at least one low-side transistor and at least one high-side transistor, said lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands, said low-side transistor mounted upon said low-side land, a drain of said transistor being electrically connected to said low-side land, said high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land.
10. The synchronous buck converter of claim 9, wherein said lead frame
12
00010495 comprises a conductive metal.
11. The synchronous buck converter of claim 10, wherein said low-side and said high-side transistor comprise metal oxide semiconductor field effect transistors.
12. "The synchronous buck converter of claim 10, wherein said high-side transistor is flip-chip mounted to said high-side land.
13. The synchronous buck converter of claim 10, wherein said low-side transistor is contained within a ball grid array package, said package being mounted to said low-side land.
14. The synchronous buck converter of claim 10, further comprising a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.
15. The synchronous buck converter of claim 14, further comprising a heat sink thermally coupled to the side of said substrate opposite said high-side land and thereby to said low-side and said high-side transistors.
16. The synchronous buck converter of claim 15, wherein said heat sink extends over said molded portion.
13
00010495
17. An integrated subassembly, comprising: a lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands; a high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land; and a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.
18. The integrated transistor module of claim 17, wherein said lead frame comprises a conductive metal.
19. The integrated transistor module of claim 17, wherein said high-side transistor comprises a metal oxide semiconductor field effect transistor.
20. The integrated subassembly of claim 17, wherein said high-side transistor is flip-chip mounted to said high-side land.
21. A method of fabricating an integrated transistor module, comprising: forming a leadframe that defines at least one low-side land and at least one high-side land vertically offset from said low-side land; enclosing in an electrically insulating material a portion of said leadframe
14
00010495 proximate said high-side land, an upper surface of said insulating material on a side of said leadframe that is opposite said high-side land being substantially coplanar relative to a side of said leadframe opposite said low-side land; and mounting a high-side transistor upon said high-side land, a source of said high-side transistor being electrically connected to said high-side land.
22. The method of claim 21 , comprising the further step of mounting a low- side transistor upon said low-side land, a drain of said low-side transistor electrically connected to said low-side land, said leadframe electrically interconnecting said source of said high-side transistor with said drain of said low-side transistor.
23. The method of claim 22, wherein said high-side transistor is flip-chip mounted upon said high-side land.
24. The method of claim 22, wherein said low-side transistor is contained within a ball grid array package.
15
00010495
PCT/US2005/021877 2004-06-24 2005-06-22 Integrated transistor module and method of fabricating same WO2006012110A2 (en)

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US7842555B2 (en) 2010-11-30
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TWI405315B (en) 2013-08-11
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WO2006012110A3 (en) 2006-09-08
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KR20070020304A (en) 2007-02-20
US20050285238A1 (en) 2005-12-29

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