WO2006008746A2 - Capteur a pixel actif integre et son procede de fabrication - Google Patents
Capteur a pixel actif integre et son procede de fabrication Download PDFInfo
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- WO2006008746A2 WO2006008746A2 PCT/IL2005/000779 IL2005000779W WO2006008746A2 WO 2006008746 A2 WO2006008746 A2 WO 2006008746A2 IL 2005000779 W IL2005000779 W IL 2005000779W WO 2006008746 A2 WO2006008746 A2 WO 2006008746A2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Definitions
- This invention is generally in the field of integrated electronic devices and relates to complementary metal-oxide-semiconductor (CMOS) image sensors.
- CMOS complementary metal-oxide-semiconductor
- CMOS imager technology presents a new generation of imagers with advance features that make them an alternative technology to charge-coupled device (CCD) based imagers.
- CCD charge-coupled device
- CMOS based active pixel sensors APS capable of achieving nearly the same performance as CCDs in terms of quantum efficiency and noise have been developed.
- CMOS technology instead of CCDs is associated with the fact that CCDs typically require high power for operation and are not well suited for integration of additional signal and image processing operations.
- on-chip CMOS sensors consume two orders of magnitude less power and are well suited for a further integration with on-chip, image-processing operations.
- CMOS sensors can be read out randomly (that is, pixels can be accessed in any order) and only the interesting parts of the picture may be read out.
- CMOS sensors are realized by the leading microelectronics processing technology with outstanding advantages in speed, power reliability, and cost.
- CMOS imagers often require the use of "on pixel” electronics to perform smart signal processing though negatively affecting such parameters as filling factor, pixel area, etc.
- the dynamic range defined as a ratio in brightness between the darkest and the brightest parts of the image, generally achieves smaller values in CMOS technology than in CCD technology, but could be increased with the help of "on pixel" smart signal processing possible with the CMOS technology.
- the "on pixel” smart signal processing may for example include incorporation of electronic filters that allows for achieving real-time automatic scaling of each pixel, and/or the use of median filters (MED), e.g., to remove the so-called "salt and pepper” noise.
- MED median filters
- On-pixel median calculations can provide an improvement in system complexity, power mass and cost, and may be performed with real time throughput.
- CMOS very large scale integration VLSI
- SOI silicon-on- insulator
- SOI silicon-on- insulator
- the SOI layer thickness is in the range of few microns and the same circuit design and layout as in bulk silicon can be utilized. This approach is therefore easy to implement without heavy investments in process development and circuit design.
- the most important benefit of this approach is in improved radiation hardness with no additional improvements in speed, latch up immunity, etc.
- the source/drain n + and p + junctions can penetrate to the bottom of the SOI layer. As a result, the effective junction area is significantly smaller. The resulting major reduction in junction capacitance results in a much faster circuit.
- CMOS image sensors One of the most promising of them, the SOI active pixel sensor with the photosites implemented in the substrate, was disclosed in International Publication WO 00/21280. There, active pixel sensors for a high quality imager are fabricated using a SOI process by integrating photodetectors on the SOI substrate and forming pixel read-out transistors on the SOI thin-film.
- the technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistors in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnection among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read via the transistors formed on the silicon islands.
- the placing of photosites into the SOI substrate is advantageous over conventional bulk CMOS sensors in a number of factors.
- high collection and absorption efficiencies, large dynamic range, and low noise can be achieved for the pixels.
- the pixels can exhibit very little cross-talk and can be formed closely to one another. Additionally, the pixels can exhibit radiation hardness. Also, gains in power consumption and speed can be achieved due to common advantages of the SOI electronics over bulk electronics.
- single wafer structure signifies that the wafer structure is formed on the single substrate without any hybridization between two separate wafers to bond photodetector and CMOS electronics carrying substrates.
- an active pixel sensor comprising: a silicon substrate patterned to form a photodetector arrangement therein; a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying an electronics circuit vertically integrated with said photodetector arrangement for processing output thereof.
- SOI silicon-on-insulator
- the senor includes a single wafer structure formed by the substrate and the SOI.
- the sensor further includes an upper electrically insulating layer on top of the SOI layer structure.
- the photodetector arrangement is in the form of an array of spaced-apart doped regions of the silicon substrate, defining the array of photosensitive regions, spaced by electrically insulating regions.
- the electronic circuit includes transistors and preferably also capacitors.
- the electronic circuit includes a plurality of differently doped regions in the silicon layer of the SOI layer structure and lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI layer structure, defining a transistor arrangement (active regions of transistors).
- the SOI layer structure and the upper layer are patterned to form vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit.
- the capacitor arrangement of the electronic circuit is defined by lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI layer structure.
- the silicon substrate may have a thickness allowing illumination therethrough of the photodetector arrangement. The thickness may for example be of about 20 micrometers.
- the substrate thickness may be selected to enable diffusion of current carriers, generated in the substrate in response to the illumination, to the photodetector arrangement.
- the sensor may also include a lowermost electrically insulating layer carrying the substrate thereon.
- This lowermost electrically insulating layer may be transparent for certain wavelength range allowing illumination therethrough (and through the thin substrate) of the photodetector arrangement.
- the sensor of the invention may be configured by patterning a single wafer structure, which is formed by the unpatterned silicon substrate and the SOI layer structure on said unpatterned substrate.
- This single wafer structure may be formed by bonding between first and second wafer structures, where the first wafer structure is formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, and the second wafer structure is formed by a second silicon substrate covered by a second electrically insulating layer.
- the first and second wafers are bonded at the first and second electrically insulating layers, thereby forming the SOI layer structure including the second silicon substrate on the electrically insulating layer resulting from the boding.
- an active pixel sensor comprising: a silicon substrate patterned to define a photodetector arrangement formed by an array of doped regions defining the array of photosensitive elements spaced by electrically insulating regions; a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying an electronics circuit configured such that each element of the electronic circuit is vertically integrated with the respective photosensitive element for processing output thereof; an upper electrically insulating layer patterned with horizontally oriented electrically conductive regions defining gate electrodes of the transistors; and vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit.
- SOI silicon-on-insulator
- a method of fabricating an active pixel sensor with an electronics circuit vertically integrated with a photodetector arrangement comprising: providing a silicon-on-insulator (SOI) layer structure on a p-type silicon substrate; processing said SOI layer structure by applying thereto or therethrough an ion implantation or material diffusion, and by applying material removal processes, to thereby define elements of said electronics circuit and elements of said photodetector arrangement vertically integrated with each other in a single wafer structure.
- SOI silicon-on-insulator
- the method consists of the following: providing a wafer structure formed by the SOI layer structure on the ⁇ -type silicon substrate; applying said processing to the substrate through the SOI layer structure to define a photodetector arrangement layer therein; forming an upper insulator layer by oxidizing the silicon layer of said SOI; applying patterning procedures to the upper insulator layer, and the silicon layer and the buried oxide layer of said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper layer, the SOI layer structure and the substrate to define an array of photodiodes of the photodetector arrangement such that each photodiode is vertically aligned with its corresponding element of the electronic circuit.
- the processing to define the photodetector layer includes applying ion implantation to the substrate through the SOI layer structure.
- the patterning procedures include patterning the silicon layer of the SOI layer structure by applying ion implantation thereto to form transistor elements, and patterning the SOI layer structure and the upper layer by the material removal to form transistor and capacitor element, and interconnects between the electronics and the photodetector arrangement.
- the method may further include at least partial removal of the substrate layer to enable backside illumination therethrough of the photodetector arrangement.
- a lower insulator layer may be formed interfacing the substrate layer. This lower insulator layer is transparent to the illumination.
- the method consists of the following: providing first and second wafer structures, the first wafer structure being formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, the silicon layer of the SOI presenting the photodetector arrangement layer, and the second wafer structure being formed by a second silicon substrate covered by a second electrically insulating layer, bonding the first and second wafer structures at the first and second electrically insulating layers, thereby forming said SOI layer structure including the second silicon substrate on the electrically insulating layer resulting from said boding; applying the material removal to partially remove the second silicon substrate; oxidizing an upper surface of the second silicon substrate to thereby enable formation of an upper electrically insulating layer; patterning said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper electrically insulating layer, the SOI layer structure and the first substrate below the SOI layer structure to define an array of photodi
- the first substrate layer may be then at least partially removed to enable backside illumination of the photodetector arrangement.
- Fig. IA is a schematic illustration of an example of an integrated structure of an active pixel sensor device of the present invention
- Fig. IB illustrates an electric scheme of the device of Fig. IA
- Fig. 2 illustrates a test photodiode structure obtained through ion implantation
- Figs. 3 A to 3H show a method of fabrication of the structure of Fig. 2;
- Fig. 4 illustrates a test photodiode structure obtained through material diffusion;
- Figs. 5 A and 5B show the measurement results for the structures of Figs. 2 and 4;
- Fig. 6 is a schematic illustration of another example of an integrated structure of an active pixel sensor device of the present invention.
- Figs. 7A to 7D exemplify a method of fabricating the structure of Fig. 6.
- the sensor device 10 includes a silicon p-type substrate 12 patterned to form a photodetector arrangement 14 therein; and a silicon-on-insulator (SOI) layer structure 16 (silicon layer 16A on a buried oxide layer 16B) on the substrate 12.
- SOI silicon-on-insulator
- the silicon layer 16A is processed to form an SOI CMOS electronics circuit, generally at 18, vertically integrated with the photodetector arrangement 14 for processing output thereof.
- the substrate 12 layer thickness is considered to be too large to enable the backside illumination. Accordingly, the photodetector arrangement (its pixel regions) is illuminated from the top electronics side. It should be noted that it is possible to thin down the substrate to the range of about 20 micrometers to enable efficient back side illumination.
- the sensor device 10 is prepared as a single wafer structure formed by the substrate 12 and the SOI 16.
- the device 10 also includes an upper electrically insulating layer (e.g., silicon oxide) 20 on top of the SOI 16.
- the insulator layer 20 is prepared as two-layer structure: layer 2OA serving as the gate insulator and a capacitor spacer (e.g., obtained by oxidation of silicon layer 16A); and top layer 2OB.
- the photodetector arrangement 14 is in the form of an array of spaced- apart doped regions of the silicon substrate, defining the array of photosensitive regions, spaced by electrically insulating regions 22.
- Fig. IA one such region (image pixel) 14A is shown in full, and two adjacent pixels 14B and 14C are partially shown.
- This region 14 is formed as n+Si layer doped in the p-type Si substrate 12. Regions 14A-14C are spaced from each other by electrically insulating regions (e.g., silicon oxide) 22.
- electrically insulating regions e.g., silicon oxide
- the electronic circuit 18 (its transistor part) is formed as a plurality of differently doped regions 24A and 24B in the silicon layer 16A so as to define an active area of the transistor.
- the top layer 20 and SOI structure 16 are patterned to form vertical interconnects, generally at 26, between the pixel region 14A and the respective element of the electronic circuit 18.
- the interconnect 26 preferably has a horizontally elongated portion 26A above the silicon layer 16A being spaced therefrom by the oxide layer material 2OA to thereby form together a capacitor which serves to store the photo generated electronic charge.
- the upper layer 20 is then further patterned to enable metal contacts 28A and 28B to the silicon layer 16 A.
- Fig. IB shows in a self-explanatory manner the electrical scheme of the device 10.
- contact 28A is grounded.
- the so-obtained structure consists of two main parts: (1) buried n + -p Si photodiode (formed by layers 12 and 14) below the BOX layer 16B, the photodiode being utilized for sensing the light and generating the photo-current; and (2) top silicon (SOI) electronics 18 that consists of integration capacitor (for accumulating the charges) and on-pixel smart electronics (for signal processing).
- top silicon (SOI) electronics 18 that consists of integration capacitor (for accumulating the charges) and on-pixel smart electronics (for signal processing).
- CMOS transistor only one CMOS transistor is shown for the sake of simplicity. Both parts (photodiode and electronics) are vertically integrated.
- the present invention provides the active pixel sensor in which the photodetector arrangement 14 and the CMOS electronics 18 are integrated vertically thus making the entire pixel area 14A available for smart signal processing. This sensor is advantageously implemented in the single wafer structure thus preventing the need to bond two silicon dies together with tens of thousands electrical connections.
- the starting material for the device fabrication is an SOI wafer formed by the/Mype substrate layer 12 (before doping, i.e., before forming layer 14, as well as before defining the pixel isolating oxide 22), buried oxide (BOX) 16B and silicon 16 A on top thereof. Regions 22 are defined by lithography followed by Reactive Ion Etching (RIE) of the SOI layer structure 16 and substrate 12 (including its layer 14), and filled with silicon oxide, thus forming insulating spacers between adjacent pixels. As indicated above, the oxide layer 2OA is fabricated by oxidation of a part of top silicon 16A (e.g., thermal oxidation of IOOA of the top Si layer 16A).
- RIE Reactive Ion Etching
- Doping (n+ doping) is applied to the layer 14 (thus forming p-n transition layer 12-14 for photodiodes 12-14B, 12-14A, 12- 14C), and n+ and ⁇ -doping is applied to layer 16A (thus forming the transistor active regions 24A and 24B). Regions 22 may be defined before the creation of regions 24A and 24B or after that.
- the formation of layer 14 can use an ion (e.g. phosphor) implantation technique. This may for example be a two-stage implantation, aimed at reducing the damage to the top SOI layer 16A and allowing better damage repair by thermal annealing.
- Further fabrication steps relate to the r definition of the transistors and other elements of the electronic circuit, and are performed by standard SOI CMOS process.
- An additional lithographic step is used either prior to oxidation or later on, to define the interconnect 26 followed by the RIE etching applied to layers 16A and 16B.
- polycrystalline silicon is deposited and patterned to form the vertical interconnect 26 as well as the top electrode of the storage capacitor 26A.
- metallic contacts 28A and 28B are fabricated by oxide etch of the respective regions of the top layer 20, metal deposition (e.g., Al), and excessive metal etch.
- test structures of two types for of photodiodes shown in Figs. 2 and 4, respectively: three test structures of the type 100 of Fig. 2 distinguishing from each other by the P- implantation parameters (showing that ion implantation through the SOI structure can effectively be utilized to fabricate the photodetector arrangement) and one test structure type 200 of Fig. 4 fabricated using P diffusion rather than implantation.
- the fabrication of the structure type 100 will now be described with reference to Figs.
- the starting material for the device fabrication was an SOI wafer: a 14-22 ⁇ cmp-type SOI wafer with 2050A top Si layer 16A, 2000A buried oxide (BOX) layer 16B and a 625 micron thick substrate 12 (commercially available from SOITEC, fabricated by the Unibond process).
- the oxide layer 2OA is fabricated by oxidation of a part of top silicon 16A (e.g., thermal oxidation of IOOA of the top Si layer 16A).
- n+ doping is applied to the layer 12, to form layer 14 by ion (e.g. phosphor) implantation technique.
- a material removal is applied to a region of the SOI structure to define the electric contact to the n+-layer 14 of the photodiode (about 75 micron diameter).
- Fig. 3D polysilicon deposition and subsequent P diffusion is applied.
- the photodiode is defined by further patterning (Fig. 3E) to form a diode mesa structure using RIE (mesa diameter of 200 micron).
- RIE mea diameter of 200 micron
- second oxidation and boron implantation are applied to form layer 2OB and define p+ regions 30 (Fig. 3F).
- oxide etching followed by Al deposition is applied to form contacts 32 to enable measurement of the photodiode characteristics in the experimental samples (Figs. 3G and 3H).
- the resulting photodiode structure, after selective Al-layer removal, is shown in Fig. 2.
- the structure 200 of Fig. 4 is obtained starting from the SOI wafer and carrying out P diffusion, after etching away the tqp silicon layer and the box layer.
- Figs. 5A-5B illustrate the measured photodiodes' characteristics. This includes I-V measurements in the dark (Fig. 5A) and under constant white light top illumination of 5 mW/cm 2 (Fig. 5B). The dark resistance of the diodes was calculated as well as the responsivity. Also, the breakdown voltage of diodes was measured. The area of all diodes is 3-10 "4 cm 2 (200 ⁇ m in diameter mesas). In Figs. 5A and 5B, four graphs Gi-G 4 are shown, corresponding to respectively, reference diffusion, deep implant 10 14 cm “2 , deep implant 3xl0 14 cm “2 , and double implant - deep implant 10 14 cm '2 and shallow 2x10 15 . Table 1 summarized the measurement results.
- the leakage current is lower than those with the high-dose implantation; the dark resistance is higher for this diode (low-dose) than those of the high-dose implantation.
- the responsivity of the low-dose diode is higher than that of the high-dose diodes.
- the best responsivity (0.7 AAV) was achieved for the reference diode that did not experience ion implantation.
- the measured responsivity is very close to reported values of commercial Si-diodes. It is thus clear that the ion implantation process might degrade the performances of the diodes. The larger the dose of the implantation the worse is the diode performances.
- N noise ⁇ 30 electrons.
- the vertically integrated SOI imager structure could be improved by eliminating two restricting factors that limit the performances of the device. These include the following: (a) a need of using the backside illumination approach (backside illumination is necessary when the entire pixel area is to be used for electronics), thus requiring removal of the backside Si substrate at the end of the process (otherwise most of the visible light will be absorbed in the substrate); and
- An active pixel sensor 300 of Fig. 6 is generally similar to that of Fig. IA, except for the thickness of a substrate layer 112 (12 in Fig. IA), and presence of a newly introduced silicon oxide layer 50.
- Layer 112 is thinner than layer 12 so that to allow for a backside illumination to penetrate deep enough into the substrate to generate photocarriers within the diffusion distance from layer 14.
- the thickness of layer 112 is chosen to maximize the photocurrent in photodiode 112- 14.
- the first technique utilizes etching away the backside Si substrate (12 in Fig. IA) using standard Chemical Mechanical Planarization (CMP) and etching techniques, carried out at the end of the fabrication process as described above with reference to Fig. IA. It should be noted that the processed wafer can be bonded to another substrate (from top), before the substrate removal, for a mechanical support.
- CMP Chemical Mechanical Planarization
- the performances of the photodiode depend on the thickness of the residual Si substrate layer 112 that should be appropriately thin (e.g., about 20 micrometers) to avoid absorption of the light during backside illumination.
- the second technique takes advantage of the SOI fabrication technology to form double buried oxide layers (BOX layers).
- the role of the second, bottom BOX layer 50 is for two important aspects: forming a natural stop-etch layer; and the backside of the thinned wafer will be terminated by thermal oxide that has extremely low surface recombination velocity, and hence much lower dark current.
- the same processing procedure as described above is used to define the vertically integrated CMOS imager (i.e., starting from an SOI and carrying out ion implantation/diffusion and material removal).
- standard dry etching techniques are used to selectively etch the silicon layer but not the oxide layer (for example, ICP for deep trenches) to totally remove the backside substrate. This allows for the formation of high quality and flat interfaces, without surface defects and recombination.
- Such a structure shown in Fig. 6 is ideal for backside illumination.
- the second problem associated with the ion implantation can be solved by making the n + Si layer of the buried p-n photodiode as an integral part of the starting (modified) SOI wafer and by fabricating it by using either diffusion or epitaxy. As a result, there is no damage to the Si crystal during the fabrication process and the performances of the photodiode are improved by at least a factor of 5-10.
- Fig. 7A shows a structure profile 60 obtained as follows:
- a starting wafer of this process is the standard p-type SOI wafer structure 60 formed by a p-type Si layer 112 on oxide layer (BOX) 50.
- This SOI structure is located on top of a p- type substrate 62.
- The, phosphorous (P) diffusion of the p-type SOI wafer 112 is carried out to form the upper n + Si layer 14 of the diode.
- this layer can epitaxially be grown during the fabrication of the SOI wafer using the standard ELTRAN process.
- oxidation of a thin top layer 16B is performed.
- the second wafer 70 (Fig. 7B) is prepared using a p- type Si substrate 72 with porous silicon (PS) sacrificial layer 74 and a top oxide 16B for wafer bonding.
- PS porous silicon
- Wafer bonding and separation is carried out according to the standard ELTRAN process between wafers 60 and 70 (Fig. 7C).
- the wafer at the end of the process (Fig. 7D) includes a buried p-n junction 80 (similar to that of 12-14 in Fig. IA or 2) and a second, bottom BOX 50 as required.
- the present invention provides the novel technique for vertical integration of CMOS sensors and CMOS electronics using SOI wafers.
- the SOI CMOS sensor is formed by a buried p-n photodiode (below the BOX) and a top SOI layer available for CMOS electronics.
- the vertically integrated SOI CMOS sensor is ideal for backside illumination with all pixel area being available for electronic design.
- Such a sensor could also be configured for operating with front side illumination, where the light has to pass through the top thin silicon layer and the poly silicon gate level. These layers are equivalent to the double poly silicon layers of conventional CCD imagers.
- the SOI CMOS sensor of the present invention can be fabricated by the SOI ELTRAN process to form a buried p-n junction and a second BOX layer for substrate removal.
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DE102007007584A1 (de) * | 2006-12-29 | 2008-07-03 | Osram Opto Semiconductors Gmbh | Halbleiterdetektoranordnung und Herstellungsverfahren für eine Halbleiterdetektoranordnung |
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US8063424B2 (en) * | 2009-11-16 | 2011-11-22 | International Business Machines Corporation | Embedded photodetector apparatus in a 3D CMOS chip stack |
CN109904181A (zh) * | 2019-02-22 | 2019-06-18 | 上海集成电路研发中心有限公司 | 一种高填充因子的cmos成像传感器及其制作方法 |
CN111029357A (zh) * | 2019-12-24 | 2020-04-17 | 湖北三维半导体集成制造创新中心有限责任公司 | 半导体结构及其制备方法 |
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CN111029357A (zh) * | 2019-12-24 | 2020-04-17 | 湖北三维半导体集成制造创新中心有限责任公司 | 半导体结构及其制备方法 |
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