WO2005124578A3 - System, method and apparatus of error detection during a modular operation - Google Patents

System, method and apparatus of error detection during a modular operation Download PDF

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Publication number
WO2005124578A3
WO2005124578A3 PCT/IL2005/000640 IL2005000640W WO2005124578A3 WO 2005124578 A3 WO2005124578 A3 WO 2005124578A3 IL 2005000640 W IL2005000640 W IL 2005000640W WO 2005124578 A3 WO2005124578 A3 WO 2005124578A3
Authority
WO
WIPO (PCT)
Prior art keywords
modular
stamp value
result
error detection
detection during
Prior art date
Application number
PCT/IL2005/000640
Other languages
French (fr)
Other versions
WO2005124578A2 (en
Inventor
Shay Gueron
Original Assignee
Discretix Technologies Ltd
Shay Gueron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Discretix Technologies Ltd, Shay Gueron filed Critical Discretix Technologies Ltd
Publication of WO2005124578A2 publication Critical patent/WO2005124578A2/en
Publication of WO2005124578A3 publication Critical patent/WO2005124578A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7271—Fault verification, e.g. comparing two values which should be the same, unless a computational fault occurred
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation

Abstract

Some embodiments of the present invention provide an apparatus, a system, and/or a method of detecting an error in a modular operation, e.g., a modular exponential including a series of modular multiplications. Some demonstrative embodiments may include determining a result stamp value corresponding to a calculated result of a modular multiplication of the series of modular multiplications; determining an expected stamp value corresponding to an expected result of the modular multiplication; and comparing the result stamp value with the expected stamp value. Other embodiments are described and claimed.
PCT/IL2005/000640 2004-06-16 2005-06-16 System, method and apparatus of error detection during a modular operation WO2005124578A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57966104P 2004-06-16 2004-06-16
US60/579,661 2004-06-16

Publications (2)

Publication Number Publication Date
WO2005124578A2 WO2005124578A2 (en) 2005-12-29
WO2005124578A3 true WO2005124578A3 (en) 2006-08-24

Family

ID=35510392

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2005/000640 WO2005124578A2 (en) 2004-06-16 2005-06-16 System, method and apparatus of error detection during a modular operation

Country Status (1)

Country Link
WO (1) WO2005124578A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2605232B1 (en) * 2007-03-19 2014-07-16 Fujitsu Limited Embedded device having countermeasure function against fault attack

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3816728A (en) * 1972-12-14 1974-06-11 Ibm Modulo 9 residue generating and checking circuit
US3873820A (en) * 1974-01-31 1975-03-25 Ibm Apparatus for checking partial products in iterative multiply operations
US4870607A (en) * 1986-07-03 1989-09-26 Nec Corporation Error detection carried out by the use of unused modulo-m code
US4926374A (en) * 1988-11-23 1990-05-15 International Business Machines Corporation Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3816728A (en) * 1972-12-14 1974-06-11 Ibm Modulo 9 residue generating and checking circuit
US3873820A (en) * 1974-01-31 1975-03-25 Ibm Apparatus for checking partial products in iterative multiply operations
US4870607A (en) * 1986-07-03 1989-09-26 Nec Corporation Error detection carried out by the use of unused modulo-m code
US4926374A (en) * 1988-11-23 1990-05-15 International Business Machines Corporation Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations

Also Published As

Publication number Publication date
WO2005124578A2 (en) 2005-12-29

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