WO2005122706A3 - Method of aligning semiconductor device and semiconductor structure thereof - Google Patents

Method of aligning semiconductor device and semiconductor structure thereof Download PDF

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Publication number
WO2005122706A3
WO2005122706A3 PCT/KR2005/000853 KR2005000853W WO2005122706A3 WO 2005122706 A3 WO2005122706 A3 WO 2005122706A3 KR 2005000853 W KR2005000853 W KR 2005000853W WO 2005122706 A3 WO2005122706 A3 WO 2005122706A3
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WO
WIPO (PCT)
Prior art keywords
die
semiconductor
semiconductor device
aligning
semiconductor structure
Prior art date
Application number
PCT/KR2005/000853
Other languages
French (fr)
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WO2005122706A2 (en
Inventor
Joon-Mo Kang
Original Assignee
Joon-Mo Kang
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Filing date
Publication date
Priority claimed from KR1020050000019A external-priority patent/KR100713579B1/en
Application filed by Joon-Mo Kang filed Critical Joon-Mo Kang
Publication of WO2005122706A2 publication Critical patent/WO2005122706A2/en
Publication of WO2005122706A3 publication Critical patent/WO2005122706A3/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/011—Groups of the periodic table
    • H01L2924/01105—Rare earth metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20109—Temperature range 350 C=<T<400 C, 623.15K =<T< 673.15K

Abstract

The invention relates to a method of aligning semiconductor devices in die stacking and a semiconductor structure fabricated by the method. In stacking a die on a wafer, for example, a first semiconductor device on the wafer and a second semiconductor device on the die are aligned by a magnetic force between at least a first magnetic body belonging to the wafer and at least a second magnetic body belonging to the die. After the alignment, the die is made not to move by the magnetic force between the magnetic bodies to maintain the alignment which is necessary for the fabrication of a semiconductor structure.
PCT/KR2005/000853 2004-05-31 2005-03-24 Method of aligning semiconductor device and semiconductor structure thereof WO2005122706A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20040038878 2004-05-31
KR10-2004-0038878 2004-05-31
KR10-2005-0000019 2005-01-03
KR1020050000019A KR100713579B1 (en) 2004-05-31 2005-01-03 Method of aligning semiconductor device and semiconductor structure thereof

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WO2005122706A2 WO2005122706A2 (en) 2005-12-29
WO2005122706A3 true WO2005122706A3 (en) 2006-08-17

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US8796073B2 (en) * 2008-09-24 2014-08-05 Qualcomm Incorporated Low cost die-to-wafer alignment/bond for 3d IC stacking
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JP4472023B1 (en) * 2009-12-11 2010-06-02 有限会社ナプラ SUBSTRATE FOR ELECTRONIC DEVICE, LAMINATE FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING THEM
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US8330272B2 (en) * 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
CN104282607A (en) * 2013-07-09 2015-01-14 中国科学院微电子研究所 Wafer alignment method and device
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US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
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