WO2005119780A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2005119780A1 WO2005119780A1 PCT/JP2004/007817 JP2004007817W WO2005119780A1 WO 2005119780 A1 WO2005119780 A1 WO 2005119780A1 JP 2004007817 W JP2004007817 W JP 2004007817W WO 2005119780 A1 WO2005119780 A1 WO 2005119780A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- hole
- upper electrode
- semiconductor device
- film
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000000034 method Methods 0.000 title claims description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 9
- 238000006073 displacement reaction Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 description 87
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000000386 athletic effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Definitions
- the present invention relates to a semiconductor device suitable for a nonvolatile memory including a ferroelectric capacitor and a method for manufacturing the same.
- a ferroelectric capacitor provided in a ferroelectric memory or the like has a configuration in which a ferroelectric film is sandwiched between a lower electrode and an upper electrode.
- Patent Document 1 JP 2001-351920 A
- An object of the present invention is to provide a semiconductor device capable of suppressing peeling of an upper electrode from a ferroelectric film and a method for manufacturing the same.
- a semiconductor device includes a semiconductor substrate, a ferroelectric capacitor formed above the semiconductor substrate, and a hole that covers the ferroelectric capacitor and reaches an upper electrode of the ferroelectric capacitor. And a wiring formed on the interlayer insulating film and connected to the upper electrode through the hole.
- the semiconductor device according to the present invention is characterized in that the planar shapes of the holes are different from each other in length of two axes orthogonal to each other.
- an interlayer insulating film covering the ferroelectric capacitor is formed.
- a hole reaching the upper electrode of the ferroelectric capacitor is formed in the interlayer insulating film.
- a wiring connected to the upper electrode through the hole is formed on the interlayer insulating film.
- FIG. 1 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by a method according to an embodiment of the present invention.
- FIG. 2A is a cross-sectional view showing a method for manufacturing a ferroelectric memory according to the embodiment of the present invention in the order of steps.
- FIG. 2B is a cross-sectional view showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2A.
- FIG. 2C is a cross-sectional view showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2B.
- FIG. 2D is a sectional view showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2C.
- FIG. 2E is a sectional view, following FIG. 2D, of the method for manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps.
- FIG. 2F is a sectional view showing a method for manufacturing a ferroelectric memory according to the embodiment of the present invention in order of steps, following FIG. 2E.
- FIG. 2G is a sectional view showing the method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2F.
- FIG. 2H is a sectional view showing a manufacturing method of the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2G.
- FIG. 21 is a cross-sectional view showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2H.
- FIG. 2J is a cross-sectional view showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 21;
- FIG. 2K is a sectional view showing a method of manufacturing a ferroelectric memory according to the embodiment of the present invention in order of steps, following FIG. 2J.
- FIG. 2L is a view showing a step of manufacturing the ferroelectric memory according to the embodiment of the present invention, following FIG. 2K. It is sectional drawing which shows a method in order of a process.
- FIG. 2M is a sectional view showing the method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps, following FIG. 2L.
- FIG. 2N is a sectional view, following FIG. 2M, showing the method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps.
- FIG. 3A is a schematic diagram showing a planar shape of a wiring 17 in the embodiment of the present invention.
- FIG. 3B is a schematic view showing a planar shape of a wiring 117 in a conventional ferroelectric memory.
- FIG. 4A is a schematic diagram showing a shape of a wiring 17 in the embodiment of the present invention.
- FIG. 4B is a schematic diagram showing a shape of a wiring 117 in a conventional ferroelectric memory.
- FIG. 5A is a diagram showing an example of a planar shape of a contact hole.
- FIG. 5B is a diagram showing another example of the planar shape of the contact hole.
- FIG. 6 is an SEM photograph showing the state of peeling of the upper electrode.
- FIG. 7 is a cross-sectional view showing a contact hole 20.
- FIG. 8 is a cross-sectional view showing a plug 31.
- FIG. 9 is a schematic diagram showing another example of the planar shape of the wiring 17.
- FIG. 10 is a schematic view showing another example of the shape of the wiring 17.
- FIG. 1 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by a method according to an embodiment of the present invention.
- This memory cell array is provided with a plurality of bit lines 103 extending in one direction, and a plurality of word lines 104 and plate lines 105 extending in a direction perpendicular to the direction in which the bit lines 103 extend. Have been. Further, a plurality of memory cells of the ferroelectric memory according to the present embodiment are arranged in an array so as to match the lattice constituted by the bit lines 103, the word lines 104, and the plate lines 105. . Each memory cell is provided with a ferroelectric capacitor 101 and a MOS transistor 102. [0012] The gate of the MOS transistor 102 is connected to the word line 104.
- One source and drain of the MOS transistor 102 are connected to the bit line 103, and the other source and drain are connected to one electrode of the ferroelectric capacitor 101.
- the other electrode of the ferroelectric capacitor 101 is connected to the plate line 105.
- Each word line 104 and plate line 105 are shared by a plurality of MOS transistors 102 arranged in the same direction as the direction in which they extend.
- each bit line 103 is shared by a plurality of MOS transistors 102 arranged in the same direction as the extending direction.
- the direction in which the word line 104 and the plate line 105 extend, and the direction in which the bit line 103 extends may be referred to as a row direction and a column direction, respectively.
- the arrangement of the bit lines 103, the word lines 104, and the plate lines 105 is not limited to the above.
- data is stored according to the polarization state of the ferroelectric film provided on the ferroelectric capacitor 101.
- FIG. 2A to 2N are cross-sectional views illustrating a method of manufacturing a ferroelectric memory (semiconductor device) according to the embodiment of the present invention in the order of steps.
- FIG. 3 is a plan view showing the same step as FIG. 2D.
- the ratio of the area of a certain portion in plan view to the area of the wafer (semiconductor substrate) is referred to as the area ratio of the portion.
- FIG. 7 is a diagram showing a cross section orthogonal to the cross section shown in FIG. 2L.
- an element isolation insulating film 2 for dividing an element active region is formed on a surface of a semiconductor substrate 1 such as a Si substrate, for example, by LOCOS (Local Oxidation). of Silicon) method.
- the gate insulating film 3, the gate electrode 4, the silicide layer 5, the sidewall 6, the low-concentration diffusion layer 21 and the high-concentration diffusion layer 22 A transistor (MOSFET) having a source / drain diffusion layer is formed.
- MOSFET Metal Organic Source/ drain diffusion layer
- a silicon oxynitride film 7 is formed on the entire surface so as to cover the MOS FET, and a silicon oxide film 8 is further formed on the entire surface.
- the silicon oxynitride film 7 is formed in order to prevent hydrogen deterioration of the gate insulating film 3 and the like when forming the silicon oxide film 8.
- a silicon oxide film 8b is further formed on the silicon oxide film 8a by using TEOS.
- the thickness of the silicon oxide film 8b is, for example, about 100 nm.
- a lower electrode film 9 is formed on the silicon oxide film 8b.
- the lower electrode film 9 is composed of, for example, a Ti film and a Pt film formed thereon.
- the thicknesses of the Ti film and the Pt film are, for example, 20 nm and 180 nm.
- a ferroelectric film 10 is formed on the lower electrode film 9 in an amorphous state.
- a PZT (Pb (Zr, T O) film is formed.
- the thickness of the dielectric film 10 is, for example, about 200 nm.
- an upper electrode film 11 is formed on the ferroelectric film 10.
- an IrOx film iridium oxide film
- an IrO film such as an IrO film and an IrO film is formed.
- an upper electrode 11a is formed as shown in FIG. 2D.
- heat treatment is performed in an atmosphere containing oxygen to recover damage due to patterning.
- the capacitor insulating film 10a is formed by patterning the ferroelectric film 10.
- an oxygen anneal is used to prevent peeling of the AlO film to be formed later.
- an A1 ⁇ film 12 is formed on the entire surface by a sputtering method as a protective film.
- the protective film prevents hydrogen from entering the ferroelectric capacitor from outside.
- the lower electrode 9a is formed. Then, it is used to prevent peeling of the Al O film to be formed later.
- an Al 2 O 3 film 13 is formed on the entire surface by a sputtering method as a protective film.
- an interlayer insulating film 14 is formed on the entire surface by a high-density plasma method. To do.
- the thickness of the interlayer insulating film 14 is, for example, about 1.5 ⁇ .
- the interlayer insulating film 14 is planarized by a CMP (chemical mechanical polishing) method. Next, plasma processing using N 2 O gas is performed. As a result, the interlayer insulating film 14
- a barrier metal film (not shown) is formed by continuously forming a Ti film and a TiN film in the holes by a sputtering method.
- a W film is loaded into the holes by a CVD (chemical vapor deposition) method, and the W film is flattened by a CMP method, thereby forming a W plug 15.
- a SiON film 16 is formed as an antioxidant film of the W plug 15 by, for example, a plasma enhanced CVD method.
- a contact hole 19 reaching the upper electrode 11a and a contact hole 20 reaching the lower electrode 9a are formed by the SiON film 16, the interlayer insulating film 14, and the Al 2 O 3 film 13. And A1 ⁇ film 12 are formed. Then use oxygen to heal the damage.
- the planar shape of the contact hole 19 is elliptical.
- the direction in which the major axis of the ellipse extends is made to coincide with the direction in which the major axis of the upper electrode 11a extends.
- the lengths of the major axis and the minor axis be as long as possible within a range where a predetermined amount of space can be secured between the upper electrode 11a and the outer edge. In other words, it is preferable to increase the length of both the major axis and the minor axis as much as possible within the range of the misalignment margin set for the upper electrode 11a. Is more preferable.
- the surface of W plug 15 is exposed by removing SiON film 16 over the entire surface by etch-back.
- an A1 film is formed with a part of the surface of the upper electrode 11a, a part of the surface of the lower electrode 9a, and the surface of the W plug 15 exposed.
- A1 wiring 17 is formed by patterning the film. To achieve. At this time, for example, the W plug 15 and the upper electrode 11a are connected to each other by a part of the A1 wiring 17.
- a cover film made of, for example, a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.
- the planar shape of the contact hole 19 reaching the upper electrode 11a is an elliptical shape whose major axis extends in the same direction as that of the upper electrode 11a. Accordingly, as long as the distance between the outer electrode and the outer edge of the upper electrode 11a can be secured by a predetermined amount, the length of the short axis can be made as long as possible, and the length of the long axis can be made long. That is, the area of the contact hole 19 can be determined in consideration of not only the length of the short axis of the upper electrode 11a but also the length of the long axis. Therefore, it is possible to make the area of the contact hole 19 larger than the conventional one.
- the contact area between the A1 wiring 17 and the upper electrode 11a can be increased, and the stress (external force per unit area) acting on the contact surface between the A1 wiring 17 and the upper electrode 11a and the upper electrode 11a can be increased.
- the force acting on the contact surface between the ferroelectric film 10a and the ferroelectric film 10a can be reduced. As a result, it is possible to suppress the peeling of the upper electrode 11a from the ferroelectric film 10a.
- the maximum value of the contact area between the A1 wiring 117 and the upper electrode 111 is determined based only on the length of the short axis of the upper electrode 111. Therefore, the stress acting on the contact surface between the A1 wiring 117 and the upper electrode 111 and the stress acting on the contact surface between the upper electrode 111 and the ferroelectric film 110 increase, and the upper electrode 111 is immediately peeled off. Cheap.
- the planar shape of the contact hole reaching the upper electrode is not limited to an elliptical shape, but may be different if the lengths of two orthogonal axes are different from each other, as shown in FIGS. 5A and 5B.
- the shape may be a rectangle, a track-like track for athletics (a shape in which four corners of a rectangle are chamfered), and the like.
- the present invention is applicable to both a ferroelectric capacitor having a stacked structure and a ferroelectric capacitor having a planar structure. Further, the materials of the upper electrode, the ferroelectric film, and the upper electrode are not limited to those of the above-described embodiment.
- the force with which the A1 wiring 17 is buried in the contact hole 19 For example, as shown in FIG. 8, the plug 31 made of W or an Al_Cu alloy is carried in the contact hole 19. Then, the A1 wiring 17 may be formed so as to connect the W plug 15 and the plug 31. However, when W is buried in the contact hole 20 that reaches the lower electrode 9a including Pt, a plug 31 and the lower electrode 9a are formed by forming a metal film such as a TiN film before burying W. Is preferably suppressed.
- the direction in which the wiring 17 extends is not particularly limited.
- the wiring 17 may extend in a direction parallel to the long axis of the contact hole.
- the present invention since a large contact area between the wiring and the upper electrode can be ensured, the stress acting on the contact surface between the upper electrode and the ferroelectric film is reduced. Thus, peeling of the upper electrode from the ferroelectric film can be suppressed.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004800428080A CN100521211C (zh) | 2004-06-04 | 2004-06-04 | 半导体装置及其制造方法 |
PCT/JP2004/007817 WO2005119780A1 (ja) | 2004-06-04 | 2004-06-04 | 半導体装置及びその製造方法 |
JP2006514038A JP5190198B2 (ja) | 2004-06-04 | 2004-06-04 | 半導体装置及びその製造方法 |
US11/601,807 US7635885B2 (en) | 2004-06-04 | 2006-11-20 | Semiconductor device and manufacturing method of the same |
US12/563,382 US7927946B2 (en) | 2004-06-04 | 2009-09-21 | Semiconductor device and manufacturing method of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/007817 WO2005119780A1 (ja) | 2004-06-04 | 2004-06-04 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/601,807 Continuation US7635885B2 (en) | 2004-06-04 | 2006-11-20 | Semiconductor device and manufacturing method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005119780A1 true WO2005119780A1 (ja) | 2005-12-15 |
Family
ID=35463134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/007817 WO2005119780A1 (ja) | 2004-06-04 | 2004-06-04 | 半導体装置及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7635885B2 (ja) |
JP (1) | JP5190198B2 (ja) |
CN (1) | CN100521211C (ja) |
WO (1) | WO2005119780A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1892421B (zh) * | 2005-07-07 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 形成存储结接触孔的方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008120286A1 (ja) * | 2007-02-27 | 2008-10-09 | Fujitsu Microelectronics Limited | 半導体記憶装置、半導体記憶装置の製造方法、およびパッケージ樹脂形成方法 |
US8450168B2 (en) * | 2010-06-25 | 2013-05-28 | International Business Machines Corporation | Ferro-electric capacitor modules, methods of manufacture and design structures |
US8587045B2 (en) * | 2010-08-13 | 2013-11-19 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of forming the same |
CN104617108B (zh) * | 2015-01-27 | 2017-06-27 | 深圳市华星光电技术有限公司 | 低温多晶硅tft基板结构 |
US11296147B2 (en) * | 2019-05-16 | 2022-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing memory device having spacer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10144878A (ja) * | 1996-11-06 | 1998-05-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001358309A (ja) * | 1999-05-14 | 2001-12-26 | Toshiba Corp | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242244A (ja) * | 1985-08-20 | 1987-02-24 | Toshiba Corp | 双方向ブロツクチエ−ン制御方式 |
JPH10242426A (ja) * | 1996-12-26 | 1998-09-11 | Sony Corp | 半導体メモリセルのキャパシタ構造及びその作製方法 |
JP3655984B2 (ja) | 1997-01-24 | 2005-06-02 | 株式会社伊藤製作所 | 砂等の沈殿物の水切りバケットにおける水切部材 |
JP3055494B2 (ja) | 1997-06-10 | 2000-06-26 | 日本電気株式会社 | 強誘電体メモリ及びその製造方法 |
JP2000066371A (ja) * | 1998-08-17 | 2000-03-03 | Nec Corp | フォトマスク及びフォトレジストパターンの製造方法 |
US6611014B1 (en) * | 1999-05-14 | 2003-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof |
JP4979154B2 (ja) * | 2000-06-07 | 2012-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2002033459A (ja) * | 2000-07-14 | 2002-01-31 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6927410B2 (en) * | 2003-09-04 | 2005-08-09 | Silicon Storage Technology, Inc. | Memory device with discrete layers of phase change memory material |
JP4042730B2 (ja) * | 2004-09-02 | 2008-02-06 | セイコーエプソン株式会社 | 強誘電体メモリおよびその製造方法 |
KR100568515B1 (ko) * | 2004-12-06 | 2006-04-07 | 삼성전자주식회사 | 저항 소자를 구비한 반도체소자 및 그 제조방법 |
-
2004
- 2004-06-04 WO PCT/JP2004/007817 patent/WO2005119780A1/ja active Application Filing
- 2004-06-04 JP JP2006514038A patent/JP5190198B2/ja not_active Expired - Fee Related
- 2004-06-04 CN CNB2004800428080A patent/CN100521211C/zh not_active Expired - Fee Related
-
2006
- 2006-11-20 US US11/601,807 patent/US7635885B2/en active Active
-
2009
- 2009-09-21 US US12/563,382 patent/US7927946B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10144878A (ja) * | 1996-11-06 | 1998-05-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001358309A (ja) * | 1999-05-14 | 2001-12-26 | Toshiba Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1892421B (zh) * | 2005-07-07 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 形成存储结接触孔的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1943033A (zh) | 2007-04-04 |
JP5190198B2 (ja) | 2013-04-24 |
JPWO2005119780A1 (ja) | 2008-04-03 |
US20100009466A1 (en) | 2010-01-14 |
US7927946B2 (en) | 2011-04-19 |
US20070097726A1 (en) | 2007-05-03 |
CN100521211C (zh) | 2009-07-29 |
US7635885B2 (en) | 2009-12-22 |
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