WO2005101495A1 - Flexible printed circuit board for mounting semiconductor chip - Google Patents

Flexible printed circuit board for mounting semiconductor chip Download PDF

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Publication number
WO2005101495A1
WO2005101495A1 PCT/JP2005/007077 JP2005007077W WO2005101495A1 WO 2005101495 A1 WO2005101495 A1 WO 2005101495A1 JP 2005007077 W JP2005007077 W JP 2005007077W WO 2005101495 A1 WO2005101495 A1 WO 2005101495A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
circuit board
printed circuit
flexible printed
mounting
Prior art date
Application number
PCT/JP2005/007077
Other languages
French (fr)
Japanese (ja)
Inventor
Akihiro Nakamura
Original Assignee
Nippon Mektron, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mektron, Ltd. filed Critical Nippon Mektron, Ltd.
Publication of WO2005101495A1 publication Critical patent/WO2005101495A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01004Beryllium [Be]
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    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/013Alloys
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    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections

Definitions

  • the present invention relates to a flexible printed circuit board, and more particularly to a flexible printed circuit board for mounting a semiconductor chip, which employs a method of mounting a semiconductor chip after applying a sealing material when mounting a semiconductor chip.
  • FIG. 4 shows a state where a sealing material is being injected.
  • a wiring pattern 12 made of copper foil is formed on one surface of a base material 11, and an insulating layer 20 is attached on a flexible printed circuit board 10 provided with a reinforcing material 13 on the other surface, and the semiconductor chip 30 is soldered.
  • sealant 50 is injected using $ 100 per dollar.
  • a region between the insulating layer 20 and a contour line P of the contour of the semiconductor chip 30 (a contour line when the contour of the semiconductor chip 30 is projected at right angles toward the flexible circuit board 10) P
  • the sealing material 50 is injected into X with the needle 100 directed.
  • the injected sealing material 50 penetrates into the lower portion of the semiconductor chip 30 by a capillary phenomenon.
  • This material has a flux effect, and by applying it on a substrate before mounting a semiconductor chip and reflowing after mounting the semiconductor chip, solder connection and sealing can be performed simultaneously.
  • FIG. 5 shows a state after the sealing material 50 has penetrated, and fills gaps between the semiconductor chip 30 and the flexible circuit board 10 and the insulating layer 20.
  • Figure 5 shows that the sealing material 50 is This shows a state in which the wiring 12 is positively injected. In this case, when the temperature cycle test is performed, the wiring 12 is broken in the region X due to a thermal shock.
  • FIG. 6 shows a state in which the solder 40 has flown excessively.
  • the height of the standoff that is, the gap between the flexible circuit board 10 and the semiconductor chip 30 is extremely small, whereby the wiring 12 is easily broken.
  • the wiring 12 is easily disconnected in the region X where the sealing material 50 is injected by the needle 100. This is due to the difference in physical properties between the sealing material 50 and the wiring 12 in contact with the wiring 12, particularly due to the difference in the coefficient of thermal expansion.
  • the area X may be made smaller, but the force vj cannot be reduced to the limit where the needle 100 can enter.
  • the present invention has been made in consideration of the above points, and has as its object to provide a flexible circuit board that can apply as little thermal stress to wiring as possible.
  • the present invention provides:
  • a flexible printed circuit board for mounting a semiconductor chip using a no-flow underfill material as a sealing material an end of the insulating layer covering the surface of the flexible printed circuit board near the semiconductor chip may be connected to the flexible printed circuit board.
  • a flexible printed circuit board for mounting a semiconductor chip wherein the flexible printed circuit board is arranged at a position within a projection line of an outline of the semiconductor chip on the flexible printed circuit board;
  • the edge of the insulating layer is positioned within the outline of the semiconductor chip. As a result, the contact area between the wiring and the sealing material is reduced, and the breakage of the wiring due to the difference in thermal stress between the two can be prevented.
  • FIG. 1 is an explanatory diagram showing a configuration of one embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a state in which an insulating layer 20 regulates a solder flow.
  • FIG. 4 is a longitudinal sectional view showing a state in which a sealing material is injected in a conventional method of manufacturing a flexible circuit board.
  • FIG. 5 is a longitudinal sectional view showing a state after the sealing material has penetrated after the sealing material 50 shown in FIG. 4 has been injected.
  • FIG. 6 is a longitudinal sectional view showing a state in which the conventional solder 40 has flowed too much.
  • FIG. 1 is a longitudinal sectional view showing one embodiment of the present invention. As shown in Fig. 1, the insulating layer 2
  • the insulating layer 20 extends halfway through a portion where the wiring 12 is covered by the semiconductor chip 30. Therefore, the length of the wiring 12 that contacts the sealing material 50 is
  • the length is L even when the portion including 40 is included, and the length of the contact of the wiring 12 with the sealing material 50 is greatly reduced. Furthermore, looking at the portion between the end of the insulating layer 20 and the solder 40, the length of the portion in contact with the sealing material 50 is very short.
  • FIGS. 2 (a), (b), and (c) are process diagrams for manufacturing the embodiment shown in FIG. As shown in FIG. 2A, the base material 11 on the flexible circuit board is exposed, and the sealing material 50 is supplied by a dispenser 60 near the end of the wiring 12.
  • the semiconductor chip 30 that has been subjected to the solder 40 treatment is mounted on the flexible circuit board 10, and the encapsulant 50 is attached to the flexible circuit board 10. And a gap between the semiconductor chip 30 and the semiconductor chip 30.
  • the semiconductor chip 30 is connected to the flexible circuit board 10 by reflow soldering.
  • the sealing material 50 is partially extruded from the gap between the flexible circuit board 10 and the semiconductor chip 30 and is in the state shown in FIG. 1, that is, the surface of the sealing material 50 is The side force is also in a state of forming a slope applied to the upper surface of the insulating layer 20.
  • FIG. 3 shows a state where the insulating layer 20 regulates the flow of solder. That is, since the end of the insulating layer 20 is sunk under the semiconductor chip 30, it reaches very close to the electrode of the soldered semiconductor chip. For this reason, when the solder is reflowed, even if the solder flows out, it does not flow out after coming into contact with the end of the insulating layer 20!
  • the insulating layer 20 of the present invention is formed by bonding a resin film, such as polyimide, in which an opening is formed in advance by die cutting to a flexible printed board, or by bonding the film on a flexible printed board.
  • a gas laser using a gas such as CO, Ar, or iodine, or a YAG,
  • the openings are precisely processed using a solid-state laser such as ruby, and a photosensitive resist, a resin material using a photosensitive agent such as a photo solder cover, or a photosensitive resist is attached to the wiring board. It includes those formed by a general method for manufacturing a circuit board, such as those in which an opening is formed by subjecting a resin material to exposure, development, etching, or the like.

Abstract

A flexible circuit board wherein least heat stress is applied on wiring. The flexible printed circuit board is provided for mounting a semiconductor chip by using a no-flow underfill material as a sealing material. An insulating layer (20) covers a front plane of the flexible printed circuit board (10). An edge part of the insulating layer (20) close to the semiconductor chip (30) is arranged at a position inside of an outer-shape profile projection line P of the semiconductor chip.

Description

半導体チップ実装用可撓性プリント回路基板  Flexible printed circuit board for mounting semiconductor chips
技術分野  Technical field
[0001] 本発明は、可撓性プリント回路基板に係り、とくに半導体チップを実装するにつき封 止材塗布後に半導体チップを搭載する方式を採用する半導体チップ実装用可撓性 プリント回路基板に関する。  The present invention relates to a flexible printed circuit board, and more particularly to a flexible printed circuit board for mounting a semiconductor chip, which employs a method of mounting a semiconductor chip after applying a sealing material when mounting a semiconductor chip.
背景技術  Background art
[0002] 回路の高密度化が進み、これに好適な半導体チップを実装した可撓性プリント回 路基板を用いることが普及している (特開 2003-318308号公報)。そして、従来、可撓 性回路基板に半導体チップを実装するには、半導体チップの搭載後に液状の封止 材を注入している。  [0002] As the density of circuits has increased, the use of flexible printed circuit boards on which semiconductor chips suitable for this have been mounted has become widespread (Japanese Patent Application Laid-Open No. 2003-318308). Conventionally, in order to mount a semiconductor chip on a flexible circuit board, a liquid sealing material is injected after the mounting of the semiconductor chip.
[0003] 図 4は、封止材を注入している様子を示したものである。ベース材 11の一面に銅箔 による配線パターン 12が形成され、他面に補強材 13が設けられた可撓性プリント回 路基板 10の上に絶縁層 20が貼付され、かつ半導体チップ 30がはんだ 40により接 続された上で、封止材 50が-一ドル 100を用いて注入される。  FIG. 4 shows a state where a sealing material is being injected. A wiring pattern 12 made of copper foil is formed on one surface of a base material 11, and an insulating layer 20 is attached on a flexible printed circuit board 10 provided with a reinforcing material 13 on the other surface, and the semiconductor chip 30 is soldered. Once connected by 40, sealant 50 is injected using $ 100 per dollar.
[0004] このため、絶縁層 20と半導体チップ 30の外形輪郭投影線 (半導体チップ 30の外形 輪郭を可撓性回路基板 10に向けて直角に投影したときの輪郭線) Pとの間の領域 X に、ニードル 100を向けて封止材 50を注入する。注入された封止材 50は、毛細管現 象により半導体チップ 30の下部に浸透していく。  [0004] For this reason, a region between the insulating layer 20 and a contour line P of the contour of the semiconductor chip 30 (a contour line when the contour of the semiconductor chip 30 is projected at right angles toward the flexible circuit board 10) P The sealing material 50 is injected into X with the needle 100 directed. The injected sealing material 50 penetrates into the lower portion of the semiconductor chip 30 by a capillary phenomenon.
[0005] このような液状封止材に替わって、近年、ノーフローアンダーフィル材と呼ばれる材 料が、取り扱いの容易さから普及し始めている (特開 2003-86627号公報および特開 2002- 203874号公報)。  [0005] In recent years, a material called a no-flow underfill material has begun to spread in place of such a liquid sealing material due to its ease of handling (JP-A-2003-86627 and JP-A-2002-203874). No.).
[0006] この材料は、フラックス効果を持っており、半導体チップ搭載前に基板上に塗布し、 半導体チップを搭載した後にリフローすることによって、はんだ接続および封止を同 時に行うことができる。  [0006] This material has a flux effect, and by applying it on a substrate before mounting a semiconductor chip and reflowing after mounting the semiconductor chip, solder connection and sealing can be performed simultaneously.
[0007] 図 5は、封止材 50が浸透した後の状態を示すもので、半導体チップ 30と可撓性回 路基板 10および絶縁層 20との隙間を埋めている。この図 5は、従来、封止材 50が適 正に注入された状態を示しており、この場合、温度サイクル試験を行うと、熱衝撃によ り領域 Xで配線 12の破断が起きる。 FIG. 5 shows a state after the sealing material 50 has penetrated, and fills gaps between the semiconductor chip 30 and the flexible circuit board 10 and the insulating layer 20. Figure 5 shows that the sealing material 50 is This shows a state in which the wiring 12 is positively injected. In this case, when the temperature cycle test is performed, the wiring 12 is broken in the region X due to a thermal shock.
[0008] これに対して、はんだ 40が流れ過ぎた状態を示すと図 6の状態となる。この場合は 、スタンドオフ、つまり可撓性回路基板 10と半導体チップ 30との間の隙間の高さが極 端に小さぐこれにより配線 12は破断し易くなる。 [0008] On the other hand, FIG. 6 shows a state in which the solder 40 has flown excessively. In this case, the height of the standoff, that is, the gap between the flexible circuit board 10 and the semiconductor chip 30 is extremely small, whereby the wiring 12 is easily broken.
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0009] 上記した 2つの技術のうち、液状の封止材を注入する方式によると、ニードル 100に より封止材 50を注入する領域 Xで、配線 12の断線が生じ易い。これは、配線 12に接 して 、る封止材 50と配線 12との物性の相違、とくに熱膨張係数の違いによって配線[0009] Among the two techniques described above, according to the method of injecting the liquid sealing material, the wiring 12 is easily disconnected in the region X where the sealing material 50 is injected by the needle 100. This is due to the difference in physical properties between the sealing material 50 and the wiring 12 in contact with the wiring 12, particularly due to the difference in the coefficient of thermal expansion.
12に無理な応力が加わるためである。これを緩和するには、領域 Xをより小さくすれ ばよいが、ニードル 100が入る限度までし力 vj、さくできない。 This is because an excessive stress is applied to 12. To alleviate this, the area X may be made smaller, but the force vj cannot be reduced to the limit where the needle 100 can enter.
[0010] もう一つのノーフローアンダーフィル材を用いる場合は、液状の封止材よりも硬化後 の物性の不一致が大き ヽものしか存在しな 、ため、材料を選択しても殆ど改善され ず、やはり問題がある。 [0010] When another no-flow underfill material is used, there is only a large discrepancy in physical properties after curing compared to the liquid sealing material, so that even if the material is selected, there is almost no improvement. There is still a problem.
[0011] 本発明は、上述の点を考慮してなされたもので、配線に熱応力ができるだけ加わら な ヽような可撓性回路基板を提供することを目的とする。  [0011] The present invention has been made in consideration of the above points, and has as its object to provide a flexible circuit board that can apply as little thermal stress to wiring as possible.
課題を解決するための手段  Means for solving the problem
[0012] 上記目的達成のため、本発明では、 [0012] To achieve the above object, the present invention provides:
ノーフローアンダーフィル材を封止材として半導体チップを実装するための可撓性 プリント回路基板において、前記可撓性プリント回路基板の表面を覆う絶縁層の前記 半導体チップ寄りの端部を、前記可撓性プリント回路基板における前記半導体チッ プの外形輪郭投影線以内の位置に配したことを特徴とする半導体チップ実装用可撓 性プリント回路基板、  In a flexible printed circuit board for mounting a semiconductor chip using a no-flow underfill material as a sealing material, an end of the insulating layer covering the surface of the flexible printed circuit board near the semiconductor chip may be connected to the flexible printed circuit board. A flexible printed circuit board for mounting a semiconductor chip, wherein the flexible printed circuit board is arranged at a position within a projection line of an outline of the semiconductor chip on the flexible printed circuit board;
を提供するものである。  Is to provide.
発明の効果  The invention's effect
[0013] 本発明は上述のように、絶縁層の端部を半導体チップの外形輪郭投影線以内の位 置に配したため、配線と封止材との接触する範囲が縮小し、両者の熱応力の違いに よる配線破断を防止することができる。 [0013] As described above, according to the present invention, the edge of the insulating layer is positioned within the outline of the semiconductor chip. As a result, the contact area between the wiring and the sealing material is reduced, and the breakage of the wiring due to the difference in thermal stress between the two can be prevented.
図面の簡単な説明  Brief Description of Drawings
[0014] [図 1]本発明の一実施例の構成を示す説明図。  FIG. 1 is an explanatory diagram showing a configuration of one embodiment of the present invention.
[図 2]図 2(a),(b),(c)は、図 1に示す実施例を製造するための工程図。  2 (a), 2 (b), and 2 (c) are process diagrams for manufacturing the embodiment shown in FIG. 1.
[図 3]絶縁層 20がはんだ流れを規制する状態を示す断面図。  FIG. 3 is a cross-sectional view showing a state in which an insulating layer 20 regulates a solder flow.
[図 4]従来の可撓性回路基板製造法における封止材を注入している様子を示す縦断 面図。  FIG. 4 is a longitudinal sectional view showing a state in which a sealing material is injected in a conventional method of manufacturing a flexible circuit board.
[図 5]図 4に示した封止材 50注入後の、封止材が浸透した後の状態を示す縦断面図  FIG. 5 is a longitudinal sectional view showing a state after the sealing material has penetrated after the sealing material 50 shown in FIG. 4 has been injected.
[図 6]従来のはんだ 40が流れ過ぎた状態を示す縦断面図。 FIG. 6 is a longitudinal sectional view showing a state in which the conventional solder 40 has flowed too much.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0015] 以下に、添付図面を参照して本発明の実施例を説明する。 An embodiment of the present invention will be described below with reference to the accompanying drawings.
実施例 1  Example 1
[0016] 図 1は、本発明の一実施例を示す縦断面図である。この図 1に示すように、絶縁層 2 FIG. 1 is a longitudinal sectional view showing one embodiment of the present invention. As shown in Fig. 1, the insulating layer 2
0が半導体チップ 30の外形輪郭投影線 Pの位置よりもはんだ 40に寄った位置まで潜 り込んでおり、図 5に示した領域 Xは存在しない。 0 penetrates to a position closer to the solder 40 than the position of the outline contour projection line P of the semiconductor chip 30, and the region X shown in FIG. 5 does not exist.
[0017] 図 1に示す場合、絶縁層 20は、配線 12が半導体チップ 30により覆われている部分 の途中まで延びている。このため、配線 12のうち封止材 50と接触する長さは、はんだIn the case shown in FIG. 1, the insulating layer 20 extends halfway through a portion where the wiring 12 is covered by the semiconductor chip 30. Therefore, the length of the wiring 12 that contacts the sealing material 50 is
40の部分を含めても Lであり、配線 12が封止材 50と接触する長さは大幅に短縮され ている。さらに、絶縁層 20の端部とはんだ 40との間の部分を見れば、封止材 50に接 触して 、る部分の長さは非常に短 、。 The length is L even when the portion including 40 is included, and the length of the contact of the wiring 12 with the sealing material 50 is greatly reduced. Furthermore, looking at the portion between the end of the insulating layer 20 and the solder 40, the length of the portion in contact with the sealing material 50 is very short.
[0018] 図 2(a),(b),(c)は、図 1に示す実施例を製造するための工程図である。図 2(a)に示す ように、可撓性回路基板におけるベース材 11が露出し、配線 12の端部近くにデイス ペンス 60により封止材 50を供給する。 FIGS. 2 (a), (b), and (c) are process diagrams for manufacturing the embodiment shown in FIG. As shown in FIG. 2A, the base material 11 on the flexible circuit board is exposed, and the sealing material 50 is supplied by a dispenser 60 near the end of the wiring 12.
[0019] 次いで、図 2(b)に示すように、可撓性回路基板 10上にはんだ 40の処理をしてある 半導体チップ 30を搭載して、封止材 50を可撓性回路基板 10と半導体チップ 30との 隙間に充填させる。 [0020] その後、図 2(c)に示すように、リフローはんだ処理をして可撓性回路基板 10に半導 体チップ 30を接続する。この状態では、封止材 50は可撓性回路基板 10と半導体チ ップ 30との隙間から一部が押し出されて図 1に示した状態、つまり封止材 50の表面 が半導体チップ 30の側面力も絶縁層 20の上面に掛けての斜面を形成する状態とな る。 Next, as shown in FIG. 2 (b), the semiconductor chip 30 that has been subjected to the solder 40 treatment is mounted on the flexible circuit board 10, and the encapsulant 50 is attached to the flexible circuit board 10. And a gap between the semiconductor chip 30 and the semiconductor chip 30. Thereafter, as shown in FIG. 2 (c), the semiconductor chip 30 is connected to the flexible circuit board 10 by reflow soldering. In this state, the sealing material 50 is partially extruded from the gap between the flexible circuit board 10 and the semiconductor chip 30 and is in the state shown in FIG. 1, that is, the surface of the sealing material 50 is The side force is also in a state of forming a slope applied to the upper surface of the insulating layer 20.
[0021] 図 3は、絶縁層 20がはんだ流れを規制する状態を示している。すなわち、絶縁層 2 0の端部は、半導体チップ 30の下に潜り込んでいるから、はんだ処理された半導体 チップの電極の極く近くに達している。このため、はんだをリフロー処理したときに、は んだが流れ出しても絶縁層 20の端部に接触した後は、流れ出さな!/、。  FIG. 3 shows a state where the insulating layer 20 regulates the flow of solder. That is, since the end of the insulating layer 20 is sunk under the semiconductor chip 30, it reaches very close to the electrode of the soldered semiconductor chip. For this reason, when the solder is reflowed, even if the solder flows out, it does not flow out after coming into contact with the end of the insulating layer 20!
[0022] したがって、はんだの流れ過ぎによるスタンドオフの低下を防止することができる。 Therefore, it is possible to prevent the standoff from being reduced due to the excessive flow of the solder.
[0023] 本発明の絶縁層 20は、例えば型抜きにより予め開口部を形成したポリイミド等の榭 脂製フィルムを可撓性プリント基板に貼り合わせたものや、可撓性プリント基板上に 貼り合せ又は印刷により、さらには現像、エッチングによって予め形成された榭脂製 カバー材料に対して CO、 Ar、ヨウ素等の気体による気体レーザー、または YAG、 The insulating layer 20 of the present invention is formed by bonding a resin film, such as polyimide, in which an opening is formed in advance by die cutting to a flexible printed board, or by bonding the film on a flexible printed board. Alternatively, a gas laser using a gas such as CO, Ar, or iodine, or a YAG,
2  2
ルビー等の固体レーザーを用いて開口部を精密加工したもの、さらには配線された 基板上に感光性レジスト、フォトソルダーカバー等の感光剤を用いた榭脂材料、また は感光性レジストを貼り合わせた榭脂材料を露光 現像 エッチング等の処理をす ることによって開口部を形成したもの等、の一般的な回路基板の製造方法で形成さ れたものを含む。  The openings are precisely processed using a solid-state laser such as ruby, and a photosensitive resist, a resin material using a photosensitive agent such as a photo solder cover, or a photosensitive resist is attached to the wiring board. It includes those formed by a general method for manufacturing a circuit board, such as those in which an opening is formed by subjecting a resin material to exposure, development, etching, or the like.
産業上の利用可能性  Industrial applicability
[0024] 可撓性回路基板における配線と封止材との接触範囲における熱応力の違いに起 因する配線破断を防止するため、可撓性回路基板を用いた電子回路の信頼性を向 上することができる。 [0024] In order to prevent wiring breakage due to a difference in thermal stress in the contact area between the wiring and the sealing material on the flexible circuit board, the reliability of the electronic circuit using the flexible circuit board is improved. can do.

Claims

請求の範囲 The scope of the claims
[1] ノーフローアンダーフィル材を封止材として半導体チップを実装するための可撓性 プリント回路基板において、  [1] In a flexible printed circuit board for mounting a semiconductor chip using a no-flow underfill material as a sealing material,
前記可撓性プリント回路基板の表面を覆う絶縁層の前記半導体チップ寄りの端部 を、前記可撓性プリント回路基板における前記半導体チップの外形輪郭投影線以内 の位置に配した  An end of the insulating layer covering the surface of the flexible printed circuit board, which is closer to the semiconductor chip, is arranged on the flexible printed circuit board within a position within an outline contour projection line of the semiconductor chip.
ことを特徴とする半導体チップ実装用可撓性プリント回路基板。  A flexible printed circuit board for mounting a semiconductor chip.
[2] 請求項 1記載の半導体チップ実装用印刷回路基板において、  [2] The printed circuit board for mounting a semiconductor chip according to claim 1,
前記絶縁層の前記半導体チップ寄りの端部を、前記半導体チップのバンプ搭載部 にできるだけ近い位置に配したことを特徴とする半導体チップ実装用可撓性プリント 回路基板。  A flexible printed circuit board for mounting a semiconductor chip, wherein an end of the insulating layer near the semiconductor chip is arranged as close as possible to a bump mounting portion of the semiconductor chip.
[3] 請求項 1記載の半導体チップ実装用印刷回路基板において、  [3] The printed circuit board for mounting a semiconductor chip according to claim 1,
前記封止材は、前記半導体チップの外形輪郭投影線以内の位置で前記基板の配 線と接触することを特徴とする半導体チップ実装用可撓性プリント回路基板。  The flexible printed circuit board for mounting a semiconductor chip, wherein the sealing material is in contact with a wiring of the substrate at a position within a projection line of an outline of the semiconductor chip.
PCT/JP2005/007077 2004-04-14 2005-04-12 Flexible printed circuit board for mounting semiconductor chip WO2005101495A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026147A1 (en) * 1999-10-04 2001-04-12 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP2001358170A (en) * 2000-06-15 2001-12-26 Hitachi Ltd Semiconductor device and its manufacturing method
JP2003068792A (en) * 2001-08-28 2003-03-07 Nippon Avionics Co Ltd Flip-chip mounting method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026147A1 (en) * 1999-10-04 2001-04-12 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP2001358170A (en) * 2000-06-15 2001-12-26 Hitachi Ltd Semiconductor device and its manufacturing method
JP2003068792A (en) * 2001-08-28 2003-03-07 Nippon Avionics Co Ltd Flip-chip mounting method

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