WO2005101495A1 - Flexible printed circuit board for mounting semiconductor chip - Google Patents
Flexible printed circuit board for mounting semiconductor chip Download PDFInfo
- Publication number
- WO2005101495A1 WO2005101495A1 PCT/JP2005/007077 JP2005007077W WO2005101495A1 WO 2005101495 A1 WO2005101495 A1 WO 2005101495A1 JP 2005007077 W JP2005007077 W JP 2005007077W WO 2005101495 A1 WO2005101495 A1 WO 2005101495A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor chip
- circuit board
- printed circuit
- flexible printed
- mounting
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
Definitions
- the present invention relates to a flexible printed circuit board, and more particularly to a flexible printed circuit board for mounting a semiconductor chip, which employs a method of mounting a semiconductor chip after applying a sealing material when mounting a semiconductor chip.
- FIG. 4 shows a state where a sealing material is being injected.
- a wiring pattern 12 made of copper foil is formed on one surface of a base material 11, and an insulating layer 20 is attached on a flexible printed circuit board 10 provided with a reinforcing material 13 on the other surface, and the semiconductor chip 30 is soldered.
- sealant 50 is injected using $ 100 per dollar.
- a region between the insulating layer 20 and a contour line P of the contour of the semiconductor chip 30 (a contour line when the contour of the semiconductor chip 30 is projected at right angles toward the flexible circuit board 10) P
- the sealing material 50 is injected into X with the needle 100 directed.
- the injected sealing material 50 penetrates into the lower portion of the semiconductor chip 30 by a capillary phenomenon.
- This material has a flux effect, and by applying it on a substrate before mounting a semiconductor chip and reflowing after mounting the semiconductor chip, solder connection and sealing can be performed simultaneously.
- FIG. 5 shows a state after the sealing material 50 has penetrated, and fills gaps between the semiconductor chip 30 and the flexible circuit board 10 and the insulating layer 20.
- Figure 5 shows that the sealing material 50 is This shows a state in which the wiring 12 is positively injected. In this case, when the temperature cycle test is performed, the wiring 12 is broken in the region X due to a thermal shock.
- FIG. 6 shows a state in which the solder 40 has flown excessively.
- the height of the standoff that is, the gap between the flexible circuit board 10 and the semiconductor chip 30 is extremely small, whereby the wiring 12 is easily broken.
- the wiring 12 is easily disconnected in the region X where the sealing material 50 is injected by the needle 100. This is due to the difference in physical properties between the sealing material 50 and the wiring 12 in contact with the wiring 12, particularly due to the difference in the coefficient of thermal expansion.
- the area X may be made smaller, but the force vj cannot be reduced to the limit where the needle 100 can enter.
- the present invention has been made in consideration of the above points, and has as its object to provide a flexible circuit board that can apply as little thermal stress to wiring as possible.
- the present invention provides:
- a flexible printed circuit board for mounting a semiconductor chip using a no-flow underfill material as a sealing material an end of the insulating layer covering the surface of the flexible printed circuit board near the semiconductor chip may be connected to the flexible printed circuit board.
- a flexible printed circuit board for mounting a semiconductor chip wherein the flexible printed circuit board is arranged at a position within a projection line of an outline of the semiconductor chip on the flexible printed circuit board;
- the edge of the insulating layer is positioned within the outline of the semiconductor chip. As a result, the contact area between the wiring and the sealing material is reduced, and the breakage of the wiring due to the difference in thermal stress between the two can be prevented.
- FIG. 1 is an explanatory diagram showing a configuration of one embodiment of the present invention.
- FIG. 3 is a cross-sectional view showing a state in which an insulating layer 20 regulates a solder flow.
- FIG. 4 is a longitudinal sectional view showing a state in which a sealing material is injected in a conventional method of manufacturing a flexible circuit board.
- FIG. 5 is a longitudinal sectional view showing a state after the sealing material has penetrated after the sealing material 50 shown in FIG. 4 has been injected.
- FIG. 6 is a longitudinal sectional view showing a state in which the conventional solder 40 has flowed too much.
- FIG. 1 is a longitudinal sectional view showing one embodiment of the present invention. As shown in Fig. 1, the insulating layer 2
- the insulating layer 20 extends halfway through a portion where the wiring 12 is covered by the semiconductor chip 30. Therefore, the length of the wiring 12 that contacts the sealing material 50 is
- the length is L even when the portion including 40 is included, and the length of the contact of the wiring 12 with the sealing material 50 is greatly reduced. Furthermore, looking at the portion between the end of the insulating layer 20 and the solder 40, the length of the portion in contact with the sealing material 50 is very short.
- FIGS. 2 (a), (b), and (c) are process diagrams for manufacturing the embodiment shown in FIG. As shown in FIG. 2A, the base material 11 on the flexible circuit board is exposed, and the sealing material 50 is supplied by a dispenser 60 near the end of the wiring 12.
- the semiconductor chip 30 that has been subjected to the solder 40 treatment is mounted on the flexible circuit board 10, and the encapsulant 50 is attached to the flexible circuit board 10. And a gap between the semiconductor chip 30 and the semiconductor chip 30.
- the semiconductor chip 30 is connected to the flexible circuit board 10 by reflow soldering.
- the sealing material 50 is partially extruded from the gap between the flexible circuit board 10 and the semiconductor chip 30 and is in the state shown in FIG. 1, that is, the surface of the sealing material 50 is The side force is also in a state of forming a slope applied to the upper surface of the insulating layer 20.
- FIG. 3 shows a state where the insulating layer 20 regulates the flow of solder. That is, since the end of the insulating layer 20 is sunk under the semiconductor chip 30, it reaches very close to the electrode of the soldered semiconductor chip. For this reason, when the solder is reflowed, even if the solder flows out, it does not flow out after coming into contact with the end of the insulating layer 20!
- the insulating layer 20 of the present invention is formed by bonding a resin film, such as polyimide, in which an opening is formed in advance by die cutting to a flexible printed board, or by bonding the film on a flexible printed board.
- a gas laser using a gas such as CO, Ar, or iodine, or a YAG,
- the openings are precisely processed using a solid-state laser such as ruby, and a photosensitive resist, a resin material using a photosensitive agent such as a photo solder cover, or a photosensitive resist is attached to the wiring board. It includes those formed by a general method for manufacturing a circuit board, such as those in which an opening is formed by subjecting a resin material to exposure, development, etching, or the like.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004118778A JP2007242641A (en) | 2004-04-14 | 2004-04-14 | Flexible printed circuit board for mounting semiconductor chip |
JP2004-118778 | 2004-04-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005101495A1 true WO2005101495A1 (en) | 2005-10-27 |
Family
ID=35150257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/007077 WO2005101495A1 (en) | 2004-04-14 | 2005-04-12 | Flexible printed circuit board for mounting semiconductor chip |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2007242641A (en) |
TW (1) | TW200539768A (en) |
WO (1) | WO2005101495A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5353153B2 (en) | 2007-11-09 | 2013-11-27 | パナソニック株式会社 | Mounting structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001026147A1 (en) * | 1999-10-04 | 2001-04-12 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP2001358170A (en) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | Semiconductor device and its manufacturing method |
JP2003068792A (en) * | 2001-08-28 | 2003-03-07 | Nippon Avionics Co Ltd | Flip-chip mounting method |
-
2004
- 2004-04-14 JP JP2004118778A patent/JP2007242641A/en active Pending
-
2005
- 2005-04-12 WO PCT/JP2005/007077 patent/WO2005101495A1/en active Application Filing
- 2005-04-13 TW TW094111679A patent/TW200539768A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001026147A1 (en) * | 1999-10-04 | 2001-04-12 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP2001358170A (en) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | Semiconductor device and its manufacturing method |
JP2003068792A (en) * | 2001-08-28 | 2003-03-07 | Nippon Avionics Co Ltd | Flip-chip mounting method |
Also Published As
Publication number | Publication date |
---|---|
JP2007242641A (en) | 2007-09-20 |
TW200539768A (en) | 2005-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9159665B2 (en) | Flip chip interconnection having narrow interconnection sites on the substrate | |
US9545013B2 (en) | Flip chip interconnect solder mask | |
JP3367886B2 (en) | Electronic circuit device | |
TWI478254B (en) | Bump-on-lead flip chip interconnection | |
US20100065966A1 (en) | Solder Joint Flip Chip Interconnection | |
KR100244965B1 (en) | Method for manufacturing printed circuit board(PCB) and ball grid array(BGA) package | |
USRE44608E1 (en) | Solder joint flip chip interconnection | |
KR101521485B1 (en) | Pga type wiring board and mehtod of manufacturing the same | |
JP4864810B2 (en) | Manufacturing method of chip embedded substrate | |
JP2008171879A (en) | Printed board and package mounting structure | |
KR20020044577A (en) | Advanced flip-chip join package | |
JP2006100385A (en) | Semiconductor device | |
JP2005340448A (en) | Semiconductor device, its manufacturing method, circuit board, and electronic apparatus | |
JP2008288490A (en) | Process for producing built-in chip substrate | |
JP3485509B2 (en) | Flip chip type semiconductor device and manufacturing method thereof | |
JPH10135276A (en) | Area array semiconductor device, printed board and screen mask | |
WO2005101495A1 (en) | Flexible printed circuit board for mounting semiconductor chip | |
JP2007258448A (en) | Semiconductor device | |
JP2007220740A (en) | Semiconductor device and manufacturing method thereof | |
JP2006237367A (en) | Printed wiring board | |
JP2008034774A (en) | Circuit device mounted with semiconductor device, and wiring board | |
JP4828997B2 (en) | SEMICONDUCTOR PACKAGE AND ITS MOUNTING METHOD, AND INSULATED WIRING BOARD USED FOR THE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD | |
JP2007266640A (en) | Semiconductor device, method of manufacturing the same, circuit board, and electronic apparatus | |
JP4615360B2 (en) | Semiconductor device | |
KR101133126B1 (en) | Semiconductor package and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: JP |