WO2005098925A1

WO2005098925A1 - Techniques promoting adhesion of porous low k film to underlying barrier layer

Info

Publication number: WO2005098925A1
Application number: PCT/US2005/009969
Authority: WO
Inventors: Francimar Schmitt; Alexandros T. Demos; Derek R. Witty; Hichem M'saad; Sang H. Ahn; Lester A. D'cruz; Khaled A. Elsheref; Zhenjiang Cui
Original assignee: Applied Materials, Inc.
Priority date: 2004-03-31
Filing date: 2005-03-24
Publication date: 2005-10-20
Also published as: TW200614374A; KR20070028361A; TWI275146B; CN1938833A; JP4842251B2; US20050233591A1; US7547643B2; KR101141459B1; JP2007531319A; CN1938833B

Abstract

Adhesion of a porous low K film to an underlying barrier layer is improved by forming an intermediate layer lower in carbon content, and richer in silicon oxide, than the overlying porous low K film. This adhesion layer can be formed utilizing one of a number of techniques, alone or in combination. In one approach, the adhesion layer can be formed by introduction of a rich oxidizing gas such as O2/CO2/etc. to oxidize Si precursors immediately prior to deposition of the low K material. In another approach, thermally labile chemicals such as alpha-terpinene, cymene, and any other non-oxygen containing organics are removed prior to low K film deposition. In yet another approach, the hardware or processing parameters, such as the manner of introduction of the non-silicon containing component, may be modified to enable formation of an oxide interface prior to low K film deposition. In still another approach, parameters of ebeam treatment such as dosage, energy, or the use of thermal annealing, may be controlled to remove carbon species at the interface between the barrier and the low K film. In a further approach, a pre-treatment plasma may be introduced prior to low k deposition to enhance heating of the barrier interface, such that a thin oxide interface is formed when low K deposition gases are introduced and the low K film is deposited.

Description

TECHNIQUES PROMOTING ADHESION OF POROUS LOW K FILM TO UNDERLYING BARRIER LAYER

CROSS-REFERENCES TO RELATED APPLICATIONS [0001] This nonprovisional patent application claims priority to U.S. Provisional P atent Application No. 60/558,475, filed March 31, 2004, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND OF THE INVENTION [0002] One ofthe primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gas-es. Such deposition processes are referred to as chemical vapor deposition or CND. Conventional thermal CND processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CND processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CND (PECND) techniques such as described in United States Patent o. 5,362,526, entitled "Plasma- Enhanced CND Process Using TEOS for Depositing Silicon Oxide", which is incorporated by reference herein. Plasma-enhanced CND techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of higphly reactive species. The high reactivity ofthe released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECND processes.

[0003] Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits ha^ve generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.25 μ -feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.

[0004] In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant < 2.5) to reduce the capacitive coupling between adjacent metal lines. Liner/barrier layers have been used between the conductive materials and the insulators to prevent diffusion of byproducts such as moisture onto the conductive material as described in International Publication Number WO 99/41423, published on August 17, 1999. For example, moisture that can be generated during formation of a low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of the conductive metal surface. A barrier/liner layer formed from organosilicon or organosilane nitride materials can block the diffusion ofthe byproducts. However, the barrier/liner layers typically have dielectric constants that are greater than about 2.5, and the high dielectric constants result in a combined insulator that may not significantly reduce the dielectric constant.

[0005] Fig.1 A- IE illustrates a three-layer deposition PECND process for depositing a PECND lining layer 2 ofthe oxidized organosilane or organosiloxane polymer as described in International Publication Number WO 99/41423. The lining layer 2 acts as an isolation layer between a subsequent layer 7 and the underlying substrate surface 6 and metal lines 8, 9, 10 formed on the substrate surface. The layer 7 is capped by a PECND capping layer 12 ofthe oxidized organosilane or organosiloxane polymer. The PECND process deposits a multi-component dielectric layer, wherein a carbon containing silicon dioxide (SiO₂) is first deposited on the patterned metal layer having metal lines 8, 9, 10 formed on substrate 6. [0006] Referring to Fig. 1 A, the PECND lining layer 2 is deposited by the plasma enhanced reaction of an organosilane or organosiloxane compound such as methylsilane, CH₃SiH₃, and an oxidizing gas such as Ν₂O in the presence of an inert gas, such as argon, at a temperature of approximately 50°C to 350°C. The oxidized organosilane or organosiloxane layer is then cured. The deposited PECND lining layer 2 (at about 2000 A per minute) has improved barrier characteristics for the subsequent deposition ofthe layer 7 shown in Fig. IB. The lining layer obtained from methylsilane has sufficient C-H bonds to be hydrophobic, and is an excellent moisture barrier. A low K dielectric layer 7 is then deposited on the liner layer 2 by the reaction of a silane compound and hydrogen peroxide (H₂O₂) at a temperature below 200°C at a pressure of about 0.2 to about 5 Torr during deposition ofthe layer 7. The layer 7 may be partially cured as shown in Fig. 1C to remove solvents such as water prior to deposition of a cap layer 12 as shown in Fig. ID. Curing is performed by pumping down a reaction under an inert gas atmosphere under 10 Torr.

[0007] Conventional liner layers, such as silicon nitride (SiN), have higher dielectric constants than silicon oxides, and the combination of low K dielectric layers with high k dielectric liner layers provides little or no improvement in the overall stack dielectric constant and capacitive coupling. Referring to Fig. ID, after deposition ofthe layer 7, an optional capping layer 12 may be deposited on the low k dielectric layer 7 by the plasma enhanced reaction of an organosilane or organosiloxane compound and an oxidizing gas such as N₂O. Referring to Fig. IE, after deposition ofthe capping layer, if any, the deposited layers are cured in a furnace or another chamber to drive off remaining solvent or water. The capping layer 12 is also an oxidized organosilane or organosiloxane film that has good barrier properties and has a dielectric constant of about 4.0. Both the liner layer 2 and the cap layer 12 have a dielectric constant greater than 3.0 and the high dielectric constant layers substantially detract from the benefit ofthe low k dielectric layer 7.

[0008] As devices get smaller, liner layers and cap layers having relatively high dielectric constants contribute more to the overall dielectric constant of a multi-component dielectric layer. Additionally, the smaller device geometries result in an increase in parasitic capacitance between devices. Parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit can result in crosstalk between the metal lines or interconnects and/or resistance-capacitance (RC) delay, thereby reducing the response time ofthe device and degrading the overall performance ofthe device. The effects of parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit is especially of concern as the current state ofthe art circuits can employ 4 to 5 levels of interconnection, while next generation devices may require 6, 7, or possibly 8 levels of interconnection.

[0009] Lowering the parasitic capacitance between metal interconnects separated by dielectric material can be accomplished by either increasing the thickness ofthe dielectric material or by lowering the dielectric constant ofthe dielectric material. Increasing the thickness ofthe dielectric materials, however, does not address parasitic capacitance within the same metallized layer or plane. As a result, to reduce the parasitic capacitance between metal interconnects on the same or adjacent layers, one must change the material used between the metal lines or interconnects to a material having a lower dielectric constant than that ofthe materials currently used, i.e., k « 3.0.

[0010] Therefore, there remains a need for dielectric layers having dielectric constants below about 2.5 with good adhesion properties.

SUMMARY OF THE INVENTION [0011] Adhesion of a porous low K film to an underlying barrier layer is improved by forming an intermediate layer lower in carbon content, and richer in silicon oxide, than the overlying porous low K film. This adhesion layer can be formed utilizing one of a number of techniques, alone or in combination. In certain approaches, the adhesion layer can be created prior to formation ofthe overlying low K layer. In one such embodiment, the oxide adhesion layer may be formed by introducing a rich oxidizing gas, including but not limited to O₂ or CO₂, to oxidize Si precursors remaining on the surface ofthe barrier/liner layer. In accordance with another embodiment, hardware or processing parameters such as the manner of introduction ofthe non-silicon containing component, may be modified to form a discrete oxide adhesion interface, prior to deposition ofthe overlying low K nanoporous film. In accordance with still another embodiment, the liner/barrier layer may be exposed to a plasma prior to low K deposition, thereby enhancing heating ofthe barrier interface, such that a thin oxide is subsequently formed when gases are introduced to result in low K deposition. In other approaches, the adhesion layer can be created subsequent to formation ofthe overlying low K layer. In one such embodiment, parameters of annealing the low K material, including but not limited to annealing ambient, thermal annealing temperature, and ebeam annealing parameters such as dosage or energy, may be controlled to remove carbon and other species at the interface between the barrier and the low K film.

[0012] An embodiment of a method in accordance with the present invention for promoting adhesion between a nanoporous low K film and an underlying liner/barrier layer, comprises, providing a substrate bearing a liner/barrier layer. A silicon oxide adhesion layer is formed over the liner/barrier layer. A low K film is deposited over the adhesion layer, and the deposited low K film is cured to form nanopores therein. [0013] An embodiment of a method in accordance with the present invention for promoting adhesion between a nanoporous low K film and an underlying liner/barrier layer, comprises, pro iding a substrate bearing a liner/barrier layer, and depositing a low K film over the liner barrier layer. Electron beam radiation is applied to the low K film to create pores therein and to reduce a carbon content along an interface between the liner/barrier layer and. the low K film, such that an oxide adhesion layer is fonned between the liner/barrier layer and the low K film.

[0014] An embodiment of an interconnect structure in accordance with the present invention for an integrated circuit, comprises, a liner/barrier layer, a silicon oxide adhesion layer overlying the liner/barrier layer; and a nanoporous low K layer overlying the adhesion layer.

[0015] A further understanding of embodiments in accordance with the present invention can be made by way of reference to the ensuing detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Fig. 1A-1E are schematic diagrams of dielectric layers deposited on a substrate by the processes known in the art;

[0017] Fig. 2 is a cross-sectional diagram of an exemplary CND reactor configured for use according to the present invention;

[0018] Fig. 3 is a schematic diagram of a remote microwave chamber for dissociation of process gases prior to entering the reactor of Fig. 2;

[0019] Fig. 4 is a flowchart of a process control computer program pro uct used in conjunction with the exemplary CND reactor of Fig. 2;

[0020] Fig. 5 is a flow chart illustrating steps undertaken in depositing liner and cap layers in a deposition process according to one embodiment ofthe present invention;

[0021] Fig. 6A-6F is a schematic diagram ofthe layers deposited on a substrate by the process of Fig.5;

[0022] Fig. 7 is a cross sectional view showing a dual damascene structure comprising the silicon oxide layers ofthe present invention; [0023] Figs. 8A-8H are cross-sectional views showing one embodiment of a dual damascene deposition sequence ofthe present invention.

[0024] Fig. 9 plots Fourier Transform InfraRed (FTIR) spectra for a number of different film stacks. DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0025] Embodiments in accordance with the present invention relate to a variety of techniques, employed alone or in combination, that improve adhesion between a nanoporous low K film and an underlying barrier layer.

[0026] Incorporated by reference herein for all purposes are U.S. patent nos. 6,541,367 and 6,596,627. These patents describe depositing a nano-porous silicon oxide layer having a low dielectric constant. The nano-porous silicon oxide layer is produced by plasma enhanced (PECND) or microwave enhanced chemical vapor deposition of a silicon/oxygen containing material that optionally contains thermally labile organic groups, and by controlled annealing ofthe deposited silicon/oxygen containing material to form microscopic gas pockets that are uniformly dispersed in a silicon oxide layer. The relative volume ofthe microscopic gas pockets to the silicon oxide layer is controlled to preferably maintain a closed cell foam structure that provides low dielectric constants after annealing. Trie nano-porous silicon oxide layers will have dielectric constants less than about 3.0, preferably less than about 2.5. [0027] The silicon/oxygen material is chemical vapor deposited by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an unsaturated non-silicon bearing component having thermally labile groups with axi oxidizing gas. The oxidizing gases are oxygen (O ) or oxygen containing compounds such as nitrous oxide (Ν₂O), ozone (O₃), and carbon dioxide (C0₂), preferably N₂O or O₂.

[0028] Oxygen and oxygen containing compounds are preferably dissociated to increase reactivity when necessary to achieve a desired carbon content in the deposited film. RF power can be coupled to the deposition chamber to increase dissociation of the oxidizing compounds. The oxidizing compounds may also be dissociated in a microwave chamber prior to entering the deposition chamber to reduce excessive dissociation ofthe silicon containing compounds. Deposition ofthe silicon oxide layer can be continuous or discontinuous. Although deposition preferably occurs in a single deposition chamber, the layer can be deposited sequentially in two or more deposition chambers. Furthermore, F power can be cycled or pulsed to reduce heating ofthe substrate and promote greater porosity in the deposited film.

[0029] The oxidizable silicon component ofthe oxidizable silicon containing compound or mixture comprises organosilane or organosiloxane compounds which generally include the structure:

H I I — C-Si —

wherein each Si is bonded to at least one hydrogen atom and may be bonded to one or two carbon atoms, and C is included in an organo group, preferably alkyl or alkenyl groups such as -CH , -CH₂-CH₃, -CH₂-, or -CH₂-CH₂-, or fluorinated carbon derivatives thereof. When an organosilane or organosiloxane compound includes two or more Si atoms, each Si is separated from another Si by -O-, -C-, or -C-C-, wherein each bridging C is included in an organo group, preferably alkyl or alkenyl groups such as -CH₂-, -CH₂-CH₂-, - CH(CH₃)-, -C(CH₃)₂-, or fluorinated carbon derivatives thereof. The preferred organosilane and organosiloxane compounds are gases or liquids near room temperature and can be volatilized above about 10 Torr. Suitable silicon containing compounds include: methylsilane, CH -SiH₃ dimethylsilane, (CH₃)₂-SiH₂ disilanomethane, SiH₃-CH₂-SiH₃ bis(methylsilano)methane, CH₃-SiH₂-CH₂-SiH₂-CH₃

2,4,6-trisilaoxane -(-SiH₂-CH₂-SiH₂-CH₂-SiH₂-O-)- (cyclic) cyclo-1 ,3,5,7-tetrasilano-2,6-dioxy-4,8- imethylene -(-SiH₂-CH₂-SiH₂-O-)₂- (cyclic) 1,3,5-trisilacyclohexane, -(-SiH₂-CH₂-)₃- (cyclic)

1 ,3-dimethyldisiloxane, CH₃-SiH₂-O-SiH₂-CH₃

1,1,3,3-tetramethyldisiloxane (CH₃)₂-SiH-O-SiH-(CH₃)₂

1,1,5,5-tetramethyltrisiloxane, and (CH₃)₂-SiH-O-SiH₂-O-SiH-(CH₃)₂ 1,1,3,5,5-pentamethyltrisiloxane (CH₃)₂-SiH-O-SiH(CH₃)-O-SiH- (CH₃)₂ and fluorinated carbon derivatives thereof, sucli as 1,2-disilanotetrafluoroethane. The hydrocarbon groups in the organosilanes and organosiloxane may be partially or fully fluorinated to convert C-H bonds to C-F bonds. Many ofthe preferred organosilane and organosiloxane compounds are commercially available. A combination of two or more of the organosilanes or organosiloxanes can be employed to provide a blend of desired properties such as dielectric constant, oxide content, hydrophobicity, film stress, and plasma etching characteristics.

[0030] When the oxidizable silicon component forms a compound with an unsaturated non-silicon bearing component having thermally labile groups, the organosilane or organosiloxane compound are functional groups possessing both a silicon oxygen bond and a silicon-hydrogen bond. Preferred functional groups having the bonding requirements include: methylsiloxy, and (CH₃-SiH₂-O-) dimethylsiloxy ((CH₃)₂-SiH-O-)

[0031] The unsaturated non-silicon bearing component having thermally labile groups has the property of reacting with a plasma-sustained oxidizing environment to form thermally labile molecules that deposit, and which, when subsequently exposed to elevated temperatures, thermally decompose to form volatile species with low boiling points. Decomposition and evolution ofthe thermally labile group's volatile species from the deposited film will leave voids in the structure-, reducing the structure's density. Selectively removing embedded chemically reacted solid material within the deposited film by a thermal process results in low density films which have low dielectric constants. Formation of voids using some compounds such as 2,4,6-trisilaoxane (2,4,6- trisilatetrahydropyran) and cyclo-l,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene is achieved during annealing without addition of labile groups by virtue of a non-planar ring structure: l,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene, and -(-SiH₂-CH₂-SiH₂-O-) - (cyclic) 2,4,6-trisilatetrahydropyran, -SiH₂-CH₂-SiH₂-CH₂-SiH₂-O-(cyclic)

[0032] The thermally labile organic groups contain sufficient oxygen to form gaseous products when the silicon oxide layer is annealed. [0033] When the oxidizable silicon component forms a. compound with an unsaturated non-silicon bearing component having thermally labile groups, preferred thermally labile groups are non-silicon containing multiply unsaturated cycloalkanes (having two or more carbon-carbon double bonds), including heterocyclodialk enes, with oxygen or nitrogen incorporated within the molecular structure, and which generally tend to perform favorably in plasma environments. Preferred labile groups include:

Dioxin, C₄H₄O₂, -(-CH=CH-O-CH=CH-O-)-, cyclic Furan, C₄H₄O, -(-CH=CH-CH=CH-O- , cyclic Fulvene, C₆H₆, -(-CH=CH-CH=CH-C(CH₂)-)-,cyclic

[0034] Oxidizable silicon containing compounds comprising the oxidizable silicon component and the thermally labile groups include:

methylsilyl-l,4-dioxinyl ether CH₃-SiH₂-O-(C₄H₃O₂) 2-methylsiloxanyl furan -(-CH=CH-CH=C(0-SiH₂-CH₃)-O-)-, cyclic 3-methylsiloxanyl furan -(-CH=CH-C(O-SiH₂-CH₃)=CH-O-)-, cyclic 2,5-bis(methylsiloxy)- 1 ,4-dioxin -(-CH=C(O-SiH₂-CH₃)-O-CH=C(O-SiH₂-CH₃)-O-)-, cyclic

3,4-bis(methylsiloxanyl) furan -(-CH=C(O-SiH₂-CH₃)-C(O-SiH₂-CH₃)=CH-O-)-, cyclic

2,3-bis(methylsiloxanyl) furan -(-CH=CH-C(O-Si-H₂-CH₃)=C(O-SiH₂-CH₃)-O-)-, cyclic

2,4-bis(methylsiloxanyl) furan -(-CH=C(O-SiH₂-CH₃)-CH=C(O-SiH₂-CH₃)-O-)-, cyclic

2,5-bis(methylsiloxanyl) furan -(-C(O-SiH₂-CH₃)=CH-CH=C(O-SiH₂-CH₃)-O-)-, cyclic

1 -methylsiloxanylfulvene -(-CH=CH-CH=CH-C(CH(O-SiH₂-CH₃))-)-, cyclic 2-methylsiloxanylfulvene -(-CH=CH-CH=CH-C(CH₂)(O-SiH₂-CH₃)-)-, cyclic 6-methylsiloxanylfulvene -(-C(O-SiH₂-CH₃)=CH-CH=CH-C=CH-)-, cyclic bis(methylsiloxanyl)fulvene (C₆H₄)(O-SiH₂-CH ₃)₂₅ cyclic dimethylsilyl-l,4-dioxinyl ether (CH₃)₂-SiH-O-(C₄H₃O₂), cyclic 2-dimethylsiloxanyl furan -(-CH=€H-CH=CCO-SiH-(CH₃)₂)-O-)-, cyclic 3-dimethylsiloxanyl furan -(-CH=CH-C(O-SiH-(CH₃)₂)-CH-O-)-, cyclic 2,5-bis(dimethylsiloxy)- 1 ,4-dioxin -(-CH=C(O-SiH-(CH₃)₂)-O-CH=C(O-SiH-(CH₃)₂)- O-)-, cyclic 3,4-bis(dimethylsiloxanyl) furan -(-CH=C(O-SiH-(CH₃)₂)-C(0- SiH-(CH₃)₂)=CH-O-)- cyclic 2,3-bis(dimethylsiloxanyl) furan -(-CH=CH-C(O-SiH-(CH₃)₂)=C(O-SiH-(CH₃)₂)-O-)- cyclic 2,4-bis(dimethylsiloxanyl) furan -(-CH=C(O-SiH-(CH₃)₂)-CH=C(O-SiH-(CH₃)₂)-O-)- cyclic 2,5-bis(dimethylsiloxanyl) furan -(-C(O-SiH-(CH₃)₂)=CH-CB=C(O-SiH-(CH₃)₂)-O-)- cyclic

1 -dimethylsiloxanylfαlvene -(-CH-CH-CH=CH-C(CH(O- SiH-(CH₃)₂))-)-, cyclic

2-dimethylsiloxanylfulvene -(-CH=CH-CH=CH-C(CH₂)(0-SiH-(CH₃)₂)-)-,cyclic

6-dimethylsiloxanylfulvene -(-C(O-SiH-(CH₃)₂)=CH-CH=CH-C=CH-)-, cyclic bis(dimethylsiloxanyl)fulvene (C₆H₄)(O-SiH-(CH )₂)₂, cyclic and fluorinated carbon derivatives thereof. Preferably the compoumds are liquid at room temperature and can be volatilized near a pressure of 10 Torr or above. Such compounds react with an oxidizing gas to form a gel-like silicon/oxygen containing material that retains many ofthe labile organic groups at temperatures below about 50°C.

[0035] The amount of labile organic groups retained in the deposited silicon/oxygen containing material can be increased by mixing the reactive compoumds with non-silicon containing components that comprise one or more labile organic groups. The labile organic groups include the dioxan, furan, and fulvene derivative chemicals described for the silicon containing reactive compounds and other oxygen contaioing organic groups. The labile organic groups are preferably the silicon containing and non-silicon containing components incorporated in the same molecule, but with the methylsilyl or methylsiloxanyl groups replaced with vinyl groups, or with the metJiylsiloxanyl groups replaced with ester groups, or with the methylsiloxanyl groups replaced with other non- silicon containing organic groups, in addition to those chemicals without the methylsiloxanyl groups, such as 1,4-dioxin and furan. Preferred non-silicon containing multiply unsaturated cycloalkanes (having two or more carbon-carbon double bonds) include:

vinyl- 1,4-dioxinyl ether CH₂-CH₂-O-(C₄H₃O₂), cyclic vinyl furyl ether CH₂=CH₂-O-(C₄H₃O)-, cyclic vmyl-l,4-dioxin CH₂=CH₂-(C₄H₃O₂), cyclic vinyl furan CH₂=CH₂-O-(C₄H₃O), cyclic methyl furoate CH₃C(O)-O-(C₄H₃O), cyclic furyl formate (C₄H₃O)-COOH, cyclic furyl acetate (C₄H₃O)-CH₂COOH, cyclic furaldehyde CH(O)-(C₄H₃O), cyclic difuryl ketone (C₄H₃O)₂C(O), cyclic difuryl ether (C₄H₃O)-O-(C₄H₃O), cyclic difurfuryl ether (C₄H₃O)C(O)-O-C(O)(C₄H₃O), cyclic furan, C₄H₄O, (cyclic)

1,4-dioxin, C₄H₄O₂, (cyclic) and fluorinated carbon derivatives thereof.

[0036] The non-silicon containing components can alternatively be mixed with the reactive silicon containing materials that do not contain labile organic groups, such as: methylsilane, CH₃-SiH₃ dimethylsilane, (CH₃)₂-SiH₂ disilanomethane, SiH₃-CH₂-SiH₃ bis(methylsilano)methane, CH₃-SiH₂-CH₂-SiH₂-CF3₃

2,4,6-trisilaoxane -(-SiH₂-CH₂-SiH₂-CH₂-SiH₂-O-)- (cyclic) 1,3,5-trisilacyclohexane, -(-SiH₂CH₂-)₃ - (cyclic) cyclo-l,3,5,7-tetrasilano-2,6- -(-SiH₂-CH₂-SiH₂-O-)₂- (cyclic) dioxy-4,8-dimethylene

1 ,3-dimethyldisiloxane, CH₃-SiH₂-O-SiH₂-CH₃

1,1,3,3-tetramethyldisiloxane (CH₃)₂-SiH-O-SiH-(CH₃)₂ 1,1,5,5-tetramethyltrisiloxane, and (CH₃)₂-SiH-O-SiH₂-O-SiH-(CH₃)₂

1,1,3,5,5-pentamethyltrisiloxane (CH₃)₂-SiH-O-SiH(CH₃>O~SiH-(CH₃)₂ and the fluorinated carbon derivatives thereof.

[0037] A combination of thermally-labile-imparting and non-therπxally-labile-imparting compounds can be co-deposited to tailor film properties. A preferred- embodiment ofthe co-deposition compounds include a thermally-labile-imparting compound selected from either methylsilyl-l,4-dioxinyl ether or 2-methylsiloxanyl furan and a non-thermally- labile-imparting compound selected from either 2,4,6-trisilaoxane (2,4,6- trisilatetrahydropyran) or cyclo-1 ,3,5,7-tetrasilano-2,6-dioxy-4,8-dim-ethylene. [0038] The co-deposited heteroalicyclic non-thermally-labile imparting molecules which can be used advantageously are non-planar cyclic molecules with insignificant ring strain and which deposit in random orientations. For 2,4,6-trisilaoxane and cyclo-1,3,5,7- tetrasilano-2,6-dioxy-4,8-dimethylene, the dual bonding ofthe silyl functional groups to the methylene groups can provide improved thermal stability and better mechanical properties ofthe resultant film. The non-planar molecule can provide a relatively reduced stack density within the deposited film, thereby producing low dielectric films.

[0039] After the silicon/oxygen containing material is deposited as a film, the -film is preferably annealed at a gradually increasing temperature to convert the labile organic groups to dispersed gas pockets in a nano-porous silicon oxide layer having a low dielectric constant attributed to a preferably closed cell foam structure.

[0040] In a preferred embodiment, the nano-porous silicon oxide layer ofthe present invention is deposited on a PECVD silicon oxide, silicon nitride, silicon oxynitride, or hydrogenated silicon carbide (e.g., BLOk™ layer material available from Applied Materials Inc., of Santa Clara, California.) barrier layer that was deposited on a patterned metal layer by plasma assisted reaction of one or more reactive silicon containing compounds. The nano-porous silicon oxide layer is then deposited in the same multichamber clustered CND system while applying RF power or remote microwave power, and is subsequently heated using an increasing temperature profile, optionally to between about 350°C to about 400°C. The nano-porous silicon oxide layer is optionally capped in the same chamber or in an adjacent cluster tool processing chamber used to deposit the barrier layer, for example with a hydrogenated silicon carbide (BLOk™). The liner and cap layers serve as barriers which protect the nano-porous silicon oxide layer.

[0041] Treatment ofthe porous silicon oxide layer with a hydrophobic-imparting chemical during or following curing at an elevated temperature, improves the moisture resistance ofthe deposited film. The chemical used is preferably selected from a. group consisting of hexamethyldisilazane, trimethylsilyldiethylamine, phenyldimethylsilyldimethylamine, trimethoxysilyldi-methylamine, tris(trifluoromethyl)silyldimethylamine, bis(trimethyl-silyl)hydrazine, 1 - ρhenyldimethylsilyl-2-methyl-hydrazine, l-trimethoxysilyl-2-methyl-hydrazine-. 1- tris(trifluoromethylsilyl)-2-methyl-hydrazine, trimethylchlorosilane, trimethylbr mosilane, trimethylsilane, or combinations thereof. [0042] The liner and cap layers can be deposited by plasma assisted chemical vapor deposition (CND) of silicon oxide, silicon nitride, silicon oxynitride, or hydrogenated silicon carbide (BLOk™).

[0043] Further description ofthe invention will be directed toward a specific apparatus for depositing nano-porous silicon oxide layers ofthe present invention.

Exemplary C VD Plasma Reactor

[0044] One suitable CND plasma reactor in which a method ofthe present invention can be carried out is the "DLK" chamber available from Applied Materials of Santa Clara, California, and is shown in Fig. 2, which is a vertical, cross-section view of a parallel plate chemical vapor deposition reactor 110 having a high vacuum region 115. Reactor 110 contains a gas distribution manifold 111 for dispersing process gases through perforated holes in the manifold to a substrate or substrate (not shown) that rests on a substrate support plate or susceptor 112 which is raised or lowered by a lift motor 114. A liquid injection system (not shown), such as typically used for liquid injection of TEOS, may also be provided for injecting a liquid reactant. Preferred liquid injection systems include the AM AT Gas Precision Liquid Injection System (GPLIS) and the AMAT Extended Precision Liquid Injection System (EPLIS), both available from Applied Materials, Inc.

[0045] The reactor 110 includes heating ofthe process gases and substrate, such as by resistive heating coils (not shown) or external lamps (not shown). Referring to Fig. 2, susceptor 112 is mounted on a support stem 113 so that susceptor 112 (and the substrate supported on the upper surface of susceptor 112) can be controllably moved between a lower loading/off-loading position and an upper processing position which is closely adjacent to manifold 111.

[0046] When susceptor 112 and the substrate are in processing position 114, they are surrounded by a an insulator 117 and process gases exhaust into a manifold 124. In the specific DLK design shown and described in connection with Figure 2, the substrate may be seated within a pocket (not shown) in the upper surface ofthe susceptor, sized to allow a clearance of approximately 2 mm between the edge ofthe wafer and the pocket wall.

[0047] During processing, gases inlet to manifold 111 are uniformly distributed radially across the surface ofthe substrate. A vacuum pump 132 having a throttle valve controls the exhaust rate of gases from the chamber. [0048] Before reaching manifold 111, deposition and carrier gases are input through gas lines 118 into a mixing system 119 where they are combined and then sent to manifold 111. An optional microwave system 150 (shown in Fig. 3) having an applicator tube 120 may be located on the input gas line for the oxidizing gas to provide additional energy that dissociates only the oxidizing gas prior to entry to the reactor 110. The microwave applicator provides a power from between about 0 and about 6000 W. Generally, the process gases supply lines 18 for each ofthe process gases include (i) safety shut-off valves (not shown) that can be used to automatically or manually shut off the flow of process gas into the chamber, and (ii) mass flow controllers (also not shown) that measure the flow of gas through the gas supply lines. When toxic gases are used in the process, several safety shut-off valves are positioned on each gas supply line in conventional configurations.

[0049] The deposition process performed in reactor 110 can be either a non-plasma process on a cooled substrate pedestal or a plasma enhanced process. In a plasma process, a controlled plasma is typically formed adjacent to the substrate by RF energy applied to distribution manifold 111 from RF power supply 125 (with susceptor 112 grounded). Alternatively, RF power can be provided to the susceptor 112 or RF power can be provided to different components at different frequencies. RF power supply 125 can supply either single or mixed frequency RF power to enhance the decomposition of reactive species introduced into the high vacuum region 115. A mixed frequency RF power supply typically supplies power at a high RF frequency (RF1) of about 13.56 MHz to the distribution manifold 111 and at a low RF frequency (RF2) of about 360 KHz to the susceptor 112. The silicon oxide layers ofthe present invention are most preferably produced using low levels or pulsed levels of high frequency RF power. Pulsed RF power preferably provides 13.56 MHz RF power at about 20 to about 200 W during about 10% to about 30% ofthe duty cycle. Non-pulsed RF power preferably provides 13.56 MHz RF power at about 10 to about 150 W as described in more detail below. Low power deposition preferably occurs at a temperature range from about -20 to about 40°C. At the preferred temperature range, the deposited film is partially polymerized during deposition and polymerization is completed during subsequent curing ofthe film.

[0050] When additional dissociation ofthe oxidizing gas is desired, an optional microwave chamber can be used to input from about 0 to about 3000W of microwave power to the oxidizing gas prior to entering the deposition chamber. Separate addition of microwave power would avoid excessive dissociation ofthe silicon compounds prior to reaction with the oxidizing gas. A gas distribution plate having separate passages for the silicon compound and the oxidizing gas is preferred when microwave power is added to the oxidizing gas.

[0051] Typically, any or all ofthe chamber lining, gas inlet manifold faceplate, support stem 113, and various other reactor hardware is made out of material such as aluminum or anodized aluminum. An example of such a CVD reactor is described in U.S. Patent 5,000,113, entitled "Thermal CVD/PECVD Reactor and Use for Thermal Chemical Vapor Deposition of Silicon Dioxide and In-situ Multi-step Planarized Process," issued to Wang et al. and assigned to Applied Materials, Inc., the assignee ofthe present invention.

[0052] The lift motor 114 raises and lowers susceptor 112 between a processing position and a lower, substrate-loading position. The motor, the gas mixing system 119, and the RF power supply 125 are controlled by a system controller 134 over control lines 136. The reactor includes analog assemblies, such as mass flow controllers (MFCs) and standard or pulsed RF generators, that are controlled by the system controller 134 which executes system control software stored in a memory 210, which in the preferred embodiment is a hard disk drive. Motors and optical sensors are used to move and determine the position of movable mechanical assemblies such as the throttle valve ofthe vacuum pump 132 and motor for positioning the susceptor 112.

[0053] The system controller 134 controls all ofthe activities ofthe CVD reactor and a preferred embodiment ofthe controller 134 includes a hard disk drive, a floppy disk drive, and a card rack. The card rack contains a single board computer (SBC), analog and digital input/output boards, interface boards and stepper motor controller boards. The system controller conforms to the Versa Modular Europeans (VME) standard which defines board, card cage, and connector dimensions and types. The VME standard also defines the bus structure having a 16-bit data bus and 24-bit address bus.

[0054] Fig. 3 is a simplified diagram of a remote microwave system 150 for dissociating process gases such as water prior to entering the DLK reactor 110, in accordance with an embodiment ofthe present invention. Remote microwave system 150 includes an applicator tube 120, a plasma ignition system including an ultraviolet (UV) lamp 154 and a UN power supply 155, a microwave waveguide system that includes various lengths of straight and curved waveguide sections 156, waveguide coupling 158, which maybe connected together at joints 157, an output waveguide section 160, and a magnetron 168. The waveguide section 156 may further have an arm support 162 formed therein for attachment to an pivoting arm 164 mounted on a ann base 166. The pivoting arm comprises arm pieces 165 coupled to ann joints 163 that provide vertical separation ofthe arm pieces and allow rotational movement ofthe arm 164 around the ann joints 163. The arm joints 163, are vertically disposed cylinders coupled to one arm piece 165 at the bottom ofthe arm joint 163 and coupled to a second arm piece 165 at the top ofthe arm joint 165. The attachment ofthe arm pieces 165 at the ends ofthe arm joint 163 allow for vertical separation ofthe arm pieces and flexibility of position the arm 164, and thus the microwave system 150, during operation and maintenance ofthe processing reactor 110.

[0055] Magnetron 168 is a typical magnetron source capable of operating between about 0-3000 Watts for continuous wave (CW) or pulsed output of microwaves of about 2.45 Gigahertz (GHz) frequency. Of course, other magnetrons may be utilized as well. Circulator (not shown) allows only forward microwave transmission from magnetron 168 toward applicator tube 120. Tuning system 170, which may use stub tuners or other tuning elements, provides the microwave system 150 with the ability to match the load at waveguide section 160 to the characteristic impedance ofthe waveguides. Tuning system 170 may provide fixed tuning, manual tuning, or automated tuning, according to specific embodiments. In the specific embodiment, the waveguide sections have rectangular cross- sections, but other types of waveguide also may be used.

[0056] Applicator tube 120 is a circular (or other cross-section) tube made of a composite or ceramic material, preferably alumina, or other material resistant to etching by radicals. In a specific embodiment, applicator tube 120 has a length of about 18-24 inches and a cross-sectional diameter of about 3-4 inches. Applicator tube 120 is disposed through a waveguide section 160, which is open at one end for transmitting microwaves and is terminated at the other end with a metal wall. Microwaves are transmitted through the open end of waveguide section 160 to gases inside applicator tube 120, which is transparent to microwaves. Of course, other materials such as sapphire also may be used for the interior of applicator tube 120. In other embodiments, applicator tube 120 may have a metal exterior and an interior made of a composite or ceramic material wherein microwaves in waveguide section 160 enter a window through the exterior of applicator tube 120 to the exposed interior of tube 120 to energize the gases. [0057] The above-described method can be implemented in a system that is controlled by a processor based system controller such as the controller 134 shown in Fig. 2. Fig. 4 shows a block diagram of a processing system, or reactor 110, such as that depicted in Fig. 2, having such a system controller 134 that can be employed in such a capacity. The system controller 134 includes a programmable central processing unit (CPU) 220 that is operable with a memory 210, a mass storage device 215, an input control unit 245, and a display unit 255. The system controller further includes well-known support circuits 214 such as power supplies, clocks 225, cache 235, input/output (I/O) circuits 240 and the like, coupled to the various components ofthe DLK process reactor 110 to facilitate control of the deposition process. The controller 134 also includes hardware for monitoring substrate processing through sensors (not shown) in the chamber 110. Such sensors measure system parameters such as substrate temperature, chamber atmosphere pressure and the like. All ofthe above elements are coupled to a control system bus 230.

[0058] To facilitate control ofthe chamber as described above, the CPU 220 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and subprocessors. The memory 210 is coupled to the CPU 220, and is accessible to the system bus 230. The memory 210, or computer- readable medium 215, may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. The support circuits 214 are coupled to the CPU 220 for supporting the processor in a conventional manner. The deposition process is generally stored in the memory 210, typically as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 220.

[0059] The memory 210 contains instructions that the CPU 220 executes to facilitate the performance ofthe processing system 10. The instructions in the memory 210 are in the form of program code such as a program 200 that implements the method ofthe present invention. The program code may conform to any one of a number of different programming languages. For example, the program code can be written in C, C++, BASIC, Pascal, or a number of other languages.

[0060] The mass storage device 215 stores data and instructions are retrieves data and program code instructions from a processor readable storage medium, such as a magnetic disk or magnetic tape. For example, the mass storage device 215 can be a hard disk drive, floppy disk drive, tape drive, or optical disk drive. The mass storage device 215 stores and retrieves the instructions in response to directions that it receives from the CPU 220. Data and program code instructions that are stored and retrieved by the mass storage device 215 are employed by the processor unit 220 for operating the processing system. The data and program code instructions are first retrieved by the mass storage device 215 from a medium and then transferred to the memory 210 for use by the CPU 220.

[0061] The input control unit 245 couples a data input device, such as a keyboard, mouse, or light pen, to the processor unit 220 via the system bus 230 to provide for the receipt of a chamber operator's inputs. The display unit 255 provides information to a chamber operator in the form of graphical displays and alphanumeric characters under control ofthe CPU 220.

[O062] The control system bus 230 provides for the transfer of data and control signals between all ofthe devices that are coupled to the control system bus 230. Although the control system bus is displayed as a single bus that directly connects the devices in the CPU 220, the control system bus 230 can also be a collection of busses. For example, the display unit 255, input control unit 245 (with input device), and mass storage device 215 can be coupled to an input-output peripheral bus, while the CPU 220 and memory 210 are coupled to a local processor bus. The local processor bus and input-output peripheral bus are coupled together to fonn the control system bus 230.

[0063] The system controller 134 is coupled to the elements ofthe processing system 10, employed in dielectric deposition processes in accordance with the present invention via the system bus 230 and the I/O circuits 240. The I/O circuits 240 receive instructions from the program 200 stored in memory 210 via the CPU 220 and system bus 230. The program 200 provides program subroutines that enable the I/O circuits 240 to provide for substrate positioning control 250, process gas control 260, pressure control 270, heater control 280, and plasma microwave control 290, ofthe reactor 110.

[0064] The CPU 220 forms a general purpose computer that becomes a specific purpose computer when executing programs such as the program 200 ofthe embodiment ofthe method ofthe present invention depicted in the flow diagram of Fig. 4. Although the invention is described herein as being implemented in software and executed upon a general-purpose computer, those skilled in the art will realize that the invention could be implemented using hardware such as an application specific integrated circuit (ASIC) or other hardware circuitry. As such, it should be understood that the invention can be implemented, in whole or in part, in software, hardware or both.

[0065] The above CND system description is mainly for illustrative purposes, and other plasma CND equipment such as electrode cyclotron resonance (ECR) plasma CND devices, induction-coupled RF high density plasma CND devices, or the like may be employed. Additionally, variations ofthe above described system such as variations in susceptor design, heater design, location of RF power connections and others are possible. For example, the subsfrate could be supported and heated by a resistively heated susceptor. The prefreatment and method for forming a prefreated layer of the present invention is not limited to any specific apparatus or plasma excitation method. The use of other apparatuses is discussed in detail below.

Deposition, of a Νano-Porous Silicon Oxide Layer

[0066] The nano-porous silicon oxide layer ofthe present invention can be deposited in a four-layer process as shown in Fig. 5 using the PECND or microwave chamber of Fig. 2. Referring to Fig. 5, a substrate is positioned 300 in the reactor 110 and a liner/barrier layer is deposited 305 by a PECND process from a plasma comprising a reactive silicon containing compound. The deposition step 305 can include a capacitively coupled plasma or both an inductively and a capacitively coupled plasma in the process chamber 15 according to methods known in the art. The plasma can be generated using inert gases, such as He, Ar, and Ν₂. An inert gas such as helium is commonly used in the PECVD deposition to assist in plasma generation.

[0067] Next, in step 307, an adhesion layer is formed over the liner/barrier layer. The adhesion layer comprises a carbon-containing silicon oxide layer both lower in carbon content, and richer in silicon oxide content, than the overlying porous low K film. The flow of oxygen during this process can affect the percentage of carbon content in the adhesion layer. Higher oxygen flow may result in less carbon in the adhesion layer, while lower oxygen flow may result in more carbon in the adhesion layer. In addition, high RF power can be used in this step to break down the carbon containing species in a manner resulting in less carbon incorporation into the film due to carbon oxidation. As described in detail below, this adhesion layer may be formed utilizing a number of different techniques, employed separately or in combination. As shown in Figure 5, some of these techniques may form the adhesion layer after deposition ofthe nano-porous layer.

[0068] A nano-porous layer ofthe present invention is then deposited 310 on the adhesion layer by depositing a silicon oxygen containing material that further contains labile organic groups.

[0069] Next, in step 311, controlled annealing of the deposited silicon/oxygen containing material fonns microscopic gas pockets that are uniformly dispersed in the layer. In some embodiments, this annealing step may take the form ofthe application of thermal energy. In other embodiments, the annealing may take the form ofthe application of radiation, for example, in the fonn of an electron beam.

[0070] In an aspect ofthe invention, the deposited layers may be cured by an electronic beam (e-bearn) technique. The e-beam treatment may be performed in situ within the same processing system, for example, transferred from one chamber to another without break in a vacuum. The following United States Patents, incorporated herein by reference for all purposes, describe various apparatuses and processes which may be employed for electron beam curing of nanoporous low K layers formed in accordance with the present invention: U.S. patent no. 5,003,178, U.S. patent no. 5,468,595, U.S. patent no. 6,132,814, U.S. patent no. 6,204,201, U.S. patent no. 6,207,555, U.S. patent no. 6,271,146, U.S. patent no. 6,319,655, U.S. patent no. 6,407,399, U.S. patent no. 6,150,070, U.S. patent no. 6,218,090, U.S. patent no. 6,195,246, U.S. patent no. 6,218,090, U.S. patent no. 6,426,127, U.S. patent no. 6,340,556, U.S. patent no. 6,319,555, U.S. patent no. 6,358,670, and U.S. patent no. 6,255,035.

[0071] An e-beam treatment comprise the application or exposure to a dosage between about 10 micro coulombs per square centimeter (μC/cm²) and about 1000 μC/cm², for example, about 800 μC/cm², at energy ranges between about 0.5 kiloelecfron volts (KeV) and about 30 KeV, for example between about 2 KeV and about 10 KeV, such as 4 KeV. Dosages may vary. For example, a dosage between about 10 μC/cm² and about 1000 μC/cm² has been observed to result in curing of layers formed on 200mm and 300mm substrates.

[0072] The electron beams are generally generated at a pressure of about 1 mTorr to about 100 mTorr, in a gas ambient including an inert gas, including nitrogen, helium, argon, xenon, an oxidizing gas including oxygen, a reducing gas including hydrogen, a blend of hydrogen and nitrogen, ammonia, or any combination of these gases. The electron beam current ranges from about 1 mA to about 40 mA, and more preferably from about 2 mA to about 20 mA. The electron beam may cover an area from about 4 square inches to about 700 square inches. The e-beam process apparatus operates ranges from about 25° Celsius to about 450° Celsius, e.g., about 400° Celsius.

[0073] Although any e-beam device may be used, one exemplary device is the EBK chamber, available from Applied Materials, Inc., of Santa Clara California. E-beam processing is more fully described in U.S. Patent application No. 10/302,375 (AMAT 7625), entitled, "Method For Curing Low Dielectric Constant Film By Electron Beam", filed on November 22, 2002, and incorporated by reference for all purposes.

[0074] Next, a cap layer is then deposited 315 on the layer, preferably using a similar process as employed for depositing the lining layer. The substrate is then removed 320 from the reactor 110.

[0075] Referring to Figs. 6A-6F, the four-layer process provides a PECVD lining/barrier layer 400. The lining/barrier layer 400 acts as an isolation layer between the subsequent nano-porous layer 402 and the underlying substrate surface 404 and metal lines 406, 408, 410 formed on the substrate surface.

[0076] An adhesion layer 407 is then formed over liner/barrier layer 400. This adhesion layer is lower in carbon content, and richer in silicon oxide content, than the overlying nano-porous low K layer that is to be formed subsequently. A detailed discussion of formation ofthe low K adhesion layer is presented below.

[0077] The nano-porous layer 402 is capped by a PECVD capping layer 412 ofthe silicon containing compound. This process is implemented and controlled using a computer program stored in the memory 220 of a computer controller 134 for a CVD reactor 110.

[0078] Referring to Fig. 6A, the PECVD lining/barrier layer 400 is deposited in the reactor 110 by introducing a reactive silicon containing compound and an oxidizing gas. The process gases react in a plasma enhanced environment to form a conformal silicon oxide layer 400 on the substrate surface 404 and metal lines 406, 408, 410.

[0079] Referring to Fig. 6B, adhesion layer 407 may then be formed over liner/barrier layer 400. The formation of this adhesion layer is described in detail below. [0080] Referring now to Fig. 6C, the nano-porous layer 402 is deposited from a processing gas consisting of silicon and labile containing compounds and an oxidizing gas. The process gas flows range from about 20 to about 1000 seem for the silicon and labile containing compounds, and about 5 to about 4000 seem ofthe oxidizing gas. The preferred gas flows range from about 50 to about 500 seem for the silicon and labile containing compounds and a flow rate of about 5 to about 2000 seem ofthe oxidizing gas. These flow rates are given for a chamber having a volume of approximately 5.5 to 6.5 liters. Preferably, reactor 110 is maintained at a pressure of about 0.2 to about 5 Ton during deposition ofthe nano-porous layer 402.

[0081] The nano-porous layer 402 is cured as shown in Fig. 6D to remove volatile constituents prior to deposition of a cap layer 412 as shown in Fig. 6E. Curing can be performed in the reactor 110 under an inert gas atmosphere while heating the substrate to progressively higher temperatures.

[0082] The nano-porous layer 402 may be annealed at a gradually increasing temperature to retain gaseous products as dispersed microscopic bubbles, and/or to convert the optional labile organic groups to dispersed microscopic gas bubbles that are retained in the cured silicon oxide film as voids in a preferably closed cell structure. One specific anneal process comprises a heating time period of about 5 minutes, including gradually raising the temperature by about 50°C/min. to a final temperature of between about 350°C to about 400°C. Dispersion ofthe gas bubbles can be controlled by varying the temperature/time profile and by controlling the concentration of labile organic groups in the deposited film.

[0083] Alternatively, or in conjunction with a thermal anneal, the nano-porous layer 402 may be annealed by exposure to electron beam radiation of a particular energy and dose. As described in detail below, under certain conditions ebeam annealing can result in the formation of an oxide adhesion layer along the interface between the liner/barrier layer and the overlying porous low K layer.

[0084] Referring to Fig. 6E, the reactor 110 deposits a capping layer 412, preferably of the same material and by the same methods as used for the deposition ofthe PECVD liner layer 400. Referring to Fig. 6F, after deposition ofthe capping layer 412, the deposited layers are further annealed in a furnace or another chamber at a temperature from about 200°C to about 450°C to drive off remaining volatile products such as water. Of course, processing conditions will vary according to the desired characteristics ofthe deposited films.

Formation of Adhesion Layer

[0085] As indicated above, the process of forming a low k dielectric layer involves depositing a material that is subsequently annealed to remove thermally labile groups and create nanopores therein. Typically, this nanoporous low k dielectric layer comprises silicon oxide having a carbon content of less than 10%, and is deposited over a liner/barrier layer comprising silicon carbide typically having a much higher carbon content of 30% or even greater. The substantial difference in the composition and structure ofthe nanoporous low K dielectric layer versus the underlying barrier/liner material, may interfere with adhesion between them. To improve adhesion between these layers, a separate step of heating the film or substrate prior to the low K deposition step may also be implemented.

[0086] Accordingly, embodiments ofthe present invention propose the formation of a separate silicon oxide layer between them to promote adhesion. Such a silicon oxide adhesion layer in accordance with the present invention is lower in carbon content and richer in silicon oxide content than the overlying low K film, and can be fomied utilizing any one of a number of different techniques, employed alone or in various combinations.

[0087] In accordance with certain embodiments, the adhesion layer may be formed prior to deposition ofthe overlying low K layer that is later annealed to form the nanoporous material. In one specific embodiment, the adhesion layer may be formed through introduction of a rich oxidizing gas immediately prior to the low K deposition step. Examples of rich oxidizing gases which may be flowed to form the adhesion layer include but are not limited to, molecular oxygen (O₂), carbon dioxide (CO₂), ozone (O₃), hydrogen peroxide (H₂O ), nitrous oxide (N₂O), and mixtures thereof. Such prefreatment ofthe liner/barrier layer with a flow of rich oxidizing gases results in oxidation of Si precursors, thereby creating the silicon oxide adhesion layer prior to formation ofthe overlying nanoporous low K material.

[0088] In order to investigate formation of an adhesion layer in accordance with an embodiment ofthe present invention, a film stack was provided having the composition listed in Table 1 below: Table 1

[0089] In order to form a nanoporous low K layer exhibiting favorable adhesion to this film stack, process parameters were varied as summarized in Table 2 below, wherein the silicon-containing component forming the low K material is diethoxymethylsilane and the non-silicon containing component forming the low K material is alpha-terpinene:

Table 2

[0090] Each ofthe process steps listed in Table 2 were performed in an Applied Materials Producer DxZ chamber without the application of low frequency RF power, at a heater temperature of 225°C, a pressure of 8 Torr, a He carrier gas flow rate for diethoxymethylsilane of 1000 seem, and an oxygen gas flow rate of 200 seem.

[0091] In the specific process flow shown in Table 2, alpha-terpinene flow was halted during initialization to reduce the concentration of carbon in the resulting silicon oxide adhesion layer. The spacing between the showerhead and the faceplate was reduced for deposition ofthe low K material to enhance deposition rate. The reduced spacing between the showerhead and faceplate for deposition ofthe low K material resulted in a hotter substrate, since the substrate was placed closer to the faceplate. In addition, the closer spacing resulted in an increased plasma density favoring silicon oxide formation as opposed to a carbon rich film. This increased plasma density is akin to the use of higher power RF energy.

[0092] As deposited, the low K material exhibited a thickness of 2812 A. The as- deposited low K material was then exposed to electron beam radiation for curing, which reduced its thickness to about 1970 A. The electron beam curing was performed at a temperature of 400 °C, utilizing a power of 3 keV, a cureent of 1.5 mA, and a dose of 150 μC/cm².

[0093] For a reference substrate bearing the film stack of Table 1 with the deposited low K layer, after exposure to ebeam curing, application of a force (Gc) of about 4.3 J/m² resulted in separation ofthe low K layer from the underlying Blok™. For a substrate exposed to the same conditions but bearing an oxide adhesion layer in accordance with the present invention, application of Gc forces in excess of about 5.5 J/m², resulted in separation of Blok™ from the underlying nitride, or the nitride from the underlying copper. This result indicated that the Gc force required to separate the nanoporous low K layer from the underlying Blok™, was greater than the 4.3 J/m² Gc ofthe reference wafer.

[0094] Figure 9 shows various Fourier Transform Infrared (FTIR) spectra of film stacks including an oxide adhesion layer in accordance with an embodiment ofthe present invention. Figure 9 reveals the presence ofthe adhesion layer after deposition ofthe overlying low K layer, and also following the ebeam curing treatment step. As indicated by the spectra of Figure 9, the adhesion layer comprises silicon and oxygen, but relatively little carbon and hydrogen.

[0095] The above example represents just one particular embodiment of a process flow for forming an oxide adhesion layer in accordance with the present invention. Other process parameters, and values for those parameters, could be employed. Such process parameters could be varied to optimize this process in the manner of other process flows for chemical vapor deposition (CVD). Any ofthe parameters could be varied to optimize the thickness, uniformity, or other properties ofthe resulting adhesion layer.

[0096] In accordance with still another embodiment ofthe present invention, an oxide adhesion layer may be formed through pre-treatment ofthe liner/barrier layer with a plasma prior to deposition ofthe low K material. Such a plasma pre-treatment would enhance heating at the surface ofthe liner/barrier, promoting reaction of Si precursors on the liner/barrier layer to form the silicon oxide layer. In certain embodiments, the plasma could be formed in an oxidizing ambient.

[0097] In accordance with yet another embodiment in accordance with the present invention, heating by plasma exposure could be followed by the introduction of oxidizing gases, in a separate step or in conjunction with a subsequent step, for example during in initial stages of depositing the low K material. As deposition ofthe low K material is typically plasma-assisted, such a plasma prefreatment step in accordance with the present invention can conveniently be performed in the same chamber, with resulting high throughput. Moreover, the barrier/liner layer may also be formed by plasma-assisted deposition, so that a plasma prefreatment step may be performed in the same chamber utilizing plasma remaining from prior deposition steps.

[0098] For any of the prefreatment or pre-deposition steps described above, RF would be continuously applied (i.e., back-to-back RF) during the transition from pretreatment/pre-deposition to low k deposition. This is because any break or interruption in the plasma between pretreatment/pre-deposition and deposition would increase the risk of particle generation affecting proper functioning ofthe resulting device. In addition, a pause between pretreatment/pre-deposition and deposition could cause a carbon rich initial layer to be present at the start ofthe deposition step. Therefore, the use of a transition or pre-layer silicon oxide rich film in combination with the continuous application of RF power during the transition step is desirable.

[0099] While Figures 6B-C show formation ofthe adhesion layer prior to deposition of the overlying dielectric material that is subsequently annealed to form the nanoporous low K layer, this is not required by the present invention. In accordance with alternative embodiments ofthe present invention, the adhesion layer could be formed subsequent to deposition ofthe overlying low K material.

[0100] In accordance with one such embodiment ofthe present invention, an adhesion layer could be formed subsequent to deposition ofthe low K layer, by adjusting the parameters ofthe subsequent annealing step to allow for removal of carbon species at the interface between the liner/barrier and the overlying low K material. The carbon-depleted, oxide-rich adhesion layer may be formed by removal of thermally labile chemicals such as alpha-terpinene, cymene, or other non-oxygen containing organics, owing to ebeam radiation exposure. In one approach, where electron beam radiation is applied to anneal the deposited film, parameters such as the dosage and energy ofthe applied radiation may be adjusted to remove more carbon at lower depths into the deposited low K film, along the interface with the underlying liner/barrier.

[0101] In another approach, the conditions of a thermal annealing step could be controlled to achieve the same result, i.e. reduction of carbon content and increased oxide content, along the interface. Of course, control over such thermal annealing conditions could also be employed in combination with an ebeam anneal.

[0102] As described in detail above, a silicon oxide adhesion layer in accordance with embodiments ofthe present invention maybe formed utilizing a variety of techniques, alone or in combination. However formed, such an oxide adhesion layer would be expected to have a thickness of between about 10-100 A, with a carbon content of between about 0-10 %.

[0103] A series of experiments were performed to evaluate performance of adhesion layers in accordance with the present invention formed utilizing various approaches. In all cases, the low K layer was deposited over a Si wafer bearing a Blok™ layer, and the deposited film was annealed for five minutes with ebeam radiation having an energy of 4 KeV and a dose of 150 μC/cm², such that the nanoporous film exhibited a thickness of 5000 A. In a first, reference wafer having no oxide adhesion layer, the force (Gc) required to separate the nanoporous low K layer from the underlying Blok™ was 4.0 Gpa.

[0104] A second wafer bore an oxide adhesion layer formed by exposing the Blok™ layer to a flow of molecular oxygen at 200 seem under an applied power of 300W, thereby creating a plasma and oxidizing Si precursors present thereon. A third wafer bore an oxide adhesion layer formed by exposing the Blok™ layer to a flow of molecular oxygen at a higher flow rate (400 seem) under an applied power of 300W. A fourth wafer bore an oxide adhesion layer formed by exposing the Blok™ layer to a flow of molecular oxygen at 400 seem under an applied power of 500W, thereby creating a plasma.

[0105] For the second through fourth wafers, the Blok was observed to separate from the underlying Si wafer before the nanoporous low K material separated from the Blok™. This indicated that the force (Gc) required to separate the nanoporous low K layer from the underlying Blok™ was substantially greater than the 4.0 Gpa ofthe reference wafer.

Deposition of a Dual Damascene Structure

[0106] A preferced dual damascene structure 500 fabricated in accordance with an embodiment ofthe present invention is shown in Fig. 7, and the method of making the structure is sequentially depicted schematically in Figs.8A-8H, which are cross sectional views of a substrate having the steps ofthe invention formed thereon.

[0107] A dual damascene structure 500 which includes a nano-porous intermetal dielectric layer 510 is shown in Fig 7. The intermetal dielectric layers 510 and 514 deposited according to the invention have exfremely low dielectric constants of less than 3, and are often referred to as extreme low k, or ELk, dielectric layers. A first dielectric layer 510, preferably consisting ofthe nano-porous silicon oxide layer ofthe present invention is deposited on a substrate 502. The substrate comprising patterned conducting lines 506 formed in a contact level substrate material 504, with a first (or substrate) etch stop 508 of silicon oxide, silicon nitride, silicon oxynitride, or amorphous hydrogenated silicon carbide (BLOk:™), preferably silicon nitride, deposited thereon.

[0108] A silicon oxide, silicon nitride, silicon oxynitride, or hydrogenated silicon carbide (BLOk™) second etch stop 512 is deposited on the first dielectric layer 510. A second adhesion layer 511 may then be formed over layer 512, as discussed above.

[0109] A second dielectric layer 514, preferably consisting ofthe nano-porous silicon oxide layer ofthe present invention is deposited on the second adhesion layer 511, with a third etch stop 516 deposited on the second dielectric layer 514. The deposited layers are etched to form a via 520, which is subsequently filled with a conducting metal 524, preferably copper, over a barrier layer 522 conformally deposited within the via 520. The structure is then planarized and a capping layer 518 comprising silicon nitride, silicon oxide, silicon oxynitride, or hydrogenated silicon carbide, preferably comprising silicon nitride, is deposited thereon. The capping layer 518 also serves as the substrate etch stop and eoreesponds to the first etch stop 508 for subsequent dual damascene multilevel interconnects.

[0110] As shown in Fig. 8A, a first (or substrate) etch stop 508 of silicon oxide, silicon nitride, silicon oxynitride, or amorphous hydrogenated silicon carbide, preferably silicon nitride is deposited to a thickness of about lOOOA on the substrate 502. The substrate 502 comprises patterned conducting interconnects or lines 506 formed in a contact level substrate material 504. The first etch stop layer 508 may bear an adhesion layer 509 as discussed in detail above.

[0111] A- first nano-porous dielectric layer 510 is deposited according to the invention on the first etch stop 508. The first dielectric layer 510 has a thickness of about 5,000A to about 10,000 A, depending on the size ofthe structure to be fabricated, but has a preferable thickness of about 5,000A. The first dielectric layer 510 and is then annealed at a temperature of about 350°C to about 400°C to remove volatile contaminants from the layer 510.

[0112] A- second etch stop 512, such as silicon oxynitride, is deposited on the dielectric layer 510 to a thickness of about 50θA.

[0113] The second etch stop layer 512 bears an adhesion layer 511, as discussed in detail above. This oxide adhesion layer typically exhibits a thickness of between about 10-100 A.

[0114] A. second nano-porous dielectric layer 514 is then deposited over the adhesion layer 511 with a thickness of about 5,OOθA to about 10,00θA, preferably about 5,OOθA, and is then annealed at a temperature of about 350°C to about 400°C.

[0115] A third etch stop 516 of silicon oxide, silicon nitride, silicon oxynitride, or amorphous hydrogenated silicon carbide (BLOk™), preferably silicon nitride is deposited on the second dielectric layer 514 to a thickness of about 5O0A to about lOOOA, preferably at about lOOOA. A silicon oxide layer 517 having a thickness of about 2000A is the deposited on the third etch stop 516 to serve both as a hard etch mask as well as for future use in a chemical mechanical polishing (CMP) step. An anti-reflective coating (ARC) 519 and a trench photomask comprising a photoresist layer 521 are then respectfully deposited over the silicon oxide layer 517. The photoresist layer 521 is then patterned by conventional photolithography means known in the art.

[0116] The silicon oxide layer 517 is then etched by conventional means known in the art, preferably by an etch process using fluorocarbon chemistry, to expose the third etch 516 as sho vn in Fig. 8B. The initial etch ofthe silicon oxide layer 517 establishes the opening width, or trench width, ofthe dual damascene structure 500. The opening width formed in the silicon oxide layer 517 defines the horizontal interconnect ofthe dual damascene structure 500 formed above the second etch stop 514. The remaining photoresist 521 is then ashed, or dry removed, for preparation ofthe via etch. For formation ofthe contact or via width ofthe dual damascene structure, a second anti- reflective coating 519 and a photoresist layer 521 are then respectfully deposited over the thin silicon oxide layer 517, and then patterned by photolithography to expose the third etch layer 516 by the via width as shown in Fig. 8C.

[0117] Referring to Fig. 8D, the third etch stop 516 and second dielectric layer 514, are trench etched to expose the second etch stop 512. The via 520 is then formed by via etching the second dielectric layer 514 to the second etch stop 512 using anisotropic etching techniques to define the metallization structure (i.e., the interconnect and contact/via) at the width established by the silicon oxide layer 517; and etching the first dielectric layer 510 to the first etch stop 508 at the via width established during the etching ofthe third etch stop 516, second dielectric layer 514, and the second etch stop 512 as shown in Fig. 8E. Any photoresist or ARC material used to pattern the second etch stop 512 or the second dielectric layer 514 is removed using an oxygen strip or other suitable process. Fig. 8F shows the etching ofthe first etch stop 508 protecting the substrate 502, exposing the underlying patterned metal lines 506 in the contact level substrate material 504. The patterned metal lines 506 preferably comprise a conducting metal such as copper. The dual damascene structure 500 is then precleaned by conventional means known in the art prior to subsequent layer deposition.

[0118] The metallization structure is then formed with a conductive material such as aluminum, copper, tungsten or combinations thereof. Presently, the trend is to use copper to form the smaller features due to the low resistivity of copper (1.7 mW-cm compared to 3.1 mW-cm for aluminum). Preferably, as shown in Fig. 8G, a suitable barrier layer 522 such as tantalum nitride is first deposited conformally in the metallization pattern 520 to prevent copper migration into the sureounding silicon and/or dielectric material. Thereafter, a layer of copper 524 is deposited using either chemical vapor deposition, physical vapor deposition, electroplating, preferably by electroplating, to form the conductive structure. Once the structure has been filled with copper or other metal, the surface is planarized using chemical mechanical polishing and capped with a capping layer 518, preferably comprising silicon nitride and having a thickness of about 1000 A, as shown in Fig. 8H. Prior to planarizing the surface, the metal may be annealed in a hydrogen atmosphere to recrystallize the copper fill and to remove voids that may have formed in the structure 500. While not shown, a copper seed layer may be deposited prior to the copper layer 524 when the copper layer 524 is deposited by an electroplating process. The dual damascene formation process may then be repeated to deposit further interconnection levels, of which modem microprocessor integrated circuits have 5 or 6 interconnection levels.

[0119] Again, while the dual damascene formation process shown and described above involves fonnation of an adhesion layer prior to deposition ofthe low K layer, this is not required by all embodiments ofthe present invention. Alternative embodiments may form the adhesion layer subsequent to deposition ofthe low K layer.

Examples

[0120] The following examples demonstrate deposition of a nano-porous silicon oxide based film having dispersed microscopic gas voids. This example is undertaken using a chemical vapor deposition chamber, and in particular, a CENTURA "DLK" system fabricated and sold by Applied Materials, Inc., Santa Clara, California.

Silicon Compound Having Silicon Containing and Thermally Labile Imparting Components (Hypothetical)

[0121] A nano-porous silicon oxide based film is deposited at a chamber pressure of 1.0 Ton and temperature of 30°C from reactive gases which are vaporized and flown into the reactor as follows: methylsilyl-2 -furyl ether, at 150 seem nitrous oxide (N₂O), at 1000 seem

[0122] Prior to entering the chamber, the nitrous oxide is dissociated in a microwave applicator that provides 2000W of microwave energy. The substrate is positioned 600 mil from the gas distribution showerhead and the reactive gases are introduced for 2 minutes. The substrate is then heated over a time period of 5 minutes, raising the temperature ofthe substrate by 50°C/min to a temperature of 400°C to cure and anneal the nano-porous silicon oxide based film. Mixture of Silicon Containing Compound And Added Thermally Labile Imparting Compound (Hypothetical)

[0123] A nano-porous silicon oxide based film is deposited at a chamber pressure of 1.0 Ton and temperature of 30°C from reactive gases which are vaporized and flown into the reactor as follows: cyclo-l,3,5,7-tetrasilylene-2,6-dioxy-4,8 dimethylene, at 100 seem vinyl-2-furyl ether, at 50 seem Nitrous Oxide (N₂O), at 1000 seem

[0124] Prior to entering the chamber, the nitrous oxide is dissociated in a microwave applicator that provides 2000W of microwave energy. The substrate is positioned 600 mil from the gas distribution showerhead and the reactive gases are infroduced for 2 minutes. The substrate is then heated over a time period of 5 minutes, raising the temperature ofthe substrate by 50°C/min to a temperature of 40O°C to cure and anneal the nano-porous silicon oxide based film.

Silicon Compound Having Silicon Containing and Thermally Labile Imparting Components And Added Silicon Containing Compound (Hypothetical)

[0125] A nano-porous silicon oxide based film is deposited at a chamber pressure of 1.0 Ton and temperature of 0°C from reactive gases which are vaporized and flown into the reactor as follows: methylsilyl-2-furyl ether, at 100 seem cyclo-l,3,5,7-tetrasilylene-2,6-dioxy-4,8 dimethylene, at 50 seem Nitrous Oxide (N₂O), at 1000 seem.

[0126] Prior to entering the chamber, the nitrous oxide is dissociated in a microwave applicator that provides 2000W of microwave energy. The substrate is positioned 600 mil from the gas distribution showerhead and the reactive gases are infroduced for 2 minutes. The substrate is then heated over a time period of 5 minutes, raising the temperature ofthe substrate by 50°C/min to a temperature of 40O°C to cure and anneal the nano-porous silicon oxide based film.

[0127] While the above is a complete description of specific embodiments ofthe present invention, various modifications, variations, and alternatives may be employed. These equivalents and alternatives are included within the scope ofthe present invention. Therefore, the scope of this invention is not limited to the embodiments described, but is defined by the following claims and their full scope of equivalents.

Claims

WHAT IS CLAIMED IS: 1. A method for promoting adhesion between a nanoporous low K film and an underlying liner/barrier layer, the method comprising: providing a substrate bearing a liner/barrier layer; forming a silicon oxide adhesion layer over the liner/barrier layer; depositing a low K film over the adhesion layer; and curing the deposited low K film to form nanopores therein.

2. The method of claim 1 wherein providing the substrate comprises providing the substrate bearing a silicon carbide liner/barrier layer.

3. The method of claim 1 wherein forming the oxide adhesion layer comprises exposing the liner/barrier layer to an oxidizing gas prior to deposition ofthe low K film.

4. The method of claim 3 wherein forming the oxide adhesion layer further comprises exposing the oxidizing gas to a silicon-containing gas.

5. The method of claim 1 wherein forming the oxide adhesion layer comprises exposing the liner/barrier layer to a plasma prior to deposition ofthe oxidizing gas.

6. The method of claim 5 wherein the plasma is continuously maintained following deposition of the barrier/liner layer.

7. The method of claim 1 wherein the deposited low K film is cured by the application of electron beam radiation.

8. The method of claim 7 wherein application ofthe electron beam radiation reduces a carbon content along an interface between the liner/barrier and the low K film, thereby contributing to formation ofthe oxide adhesion layer.

9. A method for promoting adhesion between a nanoporous low K film and an underlying liner/barrier layer, the method comprising: providing a substrate bearing a liner/barrier layer; depositing a low K film over the liner/barrier layer; and applying electron beam radiation to the low K film create pores therein and to reduce a carbon content along an interface between the liner/barrier layer and the low K film, such that an oxide adhesion layer is fonned between the liner/barrier layer and the low K film.

10. The method of claim 9 wherein providing the substrate comprises providing the substrate bearing a silicon carbide liner/barrier layer.

11. The method of claim 9 further comprising exposing the liner/barrier layer to an oxidizing gas prior to deposition ofthe low K film.

12. The method of claim 9 further comprising exposing the oxidizing gas to a silicon-containing gas prior to deposition ofthe low K film.

13. The method of claim 12 further comprising exposing the liner/barrier layer to a plasma prior to deposition ofthe low K film.

14. The method of claim 13 wherein the plasma is continuously maintained following deposition of the barrier/liner layer.

15. An interconnect structure for an integrated circuit, the interconnect structure comprising: a liner/barrier layer; a silicon oxide adhesion layer overlying the liner/barrier layer; and a nanoporous low K layer overlying the adhesion layer.

16. The interconnect of claim 15, wherein: the liner/barrier layer comprises a silicon carbide layer having a carbon content of at least about 30%; the nanoporous low K layer comprises a carbon-doped silicon oxide layer having a carbon content of 10% or less; and the silicon oxide adhesion layer comprises silicon oxide having a carbon content of less than 10%.

17. The interconnect of claim 15 wherein the low K layer exhibits a K value of 2.5 or less.

18. The interconnect of claim 15 further comprising a copper metallization layer underlying the liner/barrier layer.