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Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

Info

Publication number
WO2005095679A3
WO2005095679A3 PCT/US2005/004480 US2005004480W WO2005095679A3 WO 2005095679 A3 WO2005095679 A3 WO 2005095679A3 US 2005004480 W US2005004480 W US 2005004480W WO 2005095679 A3 WO2005095679 A3 WO 2005095679A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
silicon
carbide
features
layer
epitaxial
Prior art date
Application number
PCT/US2005/004480
Other languages
French (fr)
Other versions
WO2005095679A2 (en )
Inventor
Christer Hallin
Heinz Lendenmann
Joseph John Sumakeris
Original Assignee
Cree Inc
Christer Hallin
Heinz Lendenmann
Joseph John Sumakeris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • H01L21/0243Surface structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

Abstract

An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.
PCT/US2005/004480 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites WO2005095679A3 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US55412304 true 2004-03-18 2004-03-18
US60/554,123 2004-03-18
US10/929,911 2004-08-30
US10929911 US7109521B2 (en) 2004-03-18 2004-08-30 Silicon carbide semiconductor structures including multiple epitaxial layers having sidewalls

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP20050760477 EP1726037B1 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
CA 2554815 CA2554815A1 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
JP2007503907A JP5014117B2 (en) 2004-03-18 2005-02-14 Sequential lithography method and reduces stacking fault nucleation sites structure to reduce the stacking fault nucleation sites
DE200560020911 DE602005020911D1 (en) 2004-03-18 2005-02-14 Sequential lithographic process for the reduction of stack error-nucleation sites and structures with reduced stack error-nucleation

Publications (2)

Publication Number Publication Date
WO2005095679A2 true WO2005095679A2 (en) 2005-10-13
WO2005095679A3 true true WO2005095679A3 (en) 2005-12-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/004480 WO2005095679A3 (en) 2004-03-18 2005-02-14 Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

Country Status (7)

Country Link
US (2) US7109521B2 (en)
JP (1) JP5014117B2 (en)
KR (1) KR20060128013A (en)
CA (1) CA2554815A1 (en)
DE (1) DE602005020911D1 (en)
EP (1) EP1726037B1 (en)
WO (1) WO2005095679A3 (en)

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US20060243985A1 (en) 2006-11-02 application
CA2554815A1 (en) 2005-10-13 application
US7226805B2 (en) 2007-06-05 grant
JP2007529901A (en) 2007-10-25 application
KR20060128013A (en) 2006-12-13 application
US20050205872A1 (en) 2005-09-22 application
WO2005095679A2 (en) 2005-10-13 application
EP1726037A2 (en) 2006-11-29 application
DE602005020911D1 (en) 2010-06-10 grant
US7109521B2 (en) 2006-09-19 grant
JP5014117B2 (en) 2012-08-29 grant
EP1726037B1 (en) 2010-04-28 grant

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