WO2005079293A2 - Integrated iii-nitride power devices - Google Patents

Integrated iii-nitride power devices Download PDF

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Publication number
WO2005079293A2
WO2005079293A2 PCT/US2005/004388 US2005004388W WO2005079293A2 WO 2005079293 A2 WO2005079293 A2 WO 2005079293A2 US 2005004388 W US2005004388 W US 2005004388W WO 2005079293 A2 WO2005079293 A2 WO 2005079293A2
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Prior art keywords
semiconductor
integrated device
devices
integrated
bridge
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PCT/US2005/004388
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French (fr)
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WO2005079293A3 (en
Inventor
Daniel M. Kinzer
Robert Beach
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Priority to JP2006553268A priority Critical patent/JP2007522677A/en
Priority to DE112005000352T priority patent/DE112005000352T5/en
Publication of WO2005079293A2 publication Critical patent/WO2005079293A2/en
Publication of WO2005079293A3 publication Critical patent/WO2005079293A3/en
Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/257Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16Photovoltaic cells having only PN heterojunction potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present invention relates to power semiconductor devices and more particularly to integrated power semiconductor devices.
  • a known, discrete high electron mobility transistor may include drain pad 10, source pad 12, and gate pad 14. Drain pad 10 is electrically connected to a plurality of drain runners 16, and source pad 12 is electrically connected to a plurality of source runners 18. Usually, drain pad 10 and source pad 12, and runners 16, 18 are arranged parallel to one another. In addition, in one conventional arrangement, drain runners 16 and source runners 18 are alternated in order to distribute current evenly through drain pad 10 and source pad 12. In a device according to Figure 1A, the area between each two opposing runners 16, 18 is an active area.
  • FIG. IB a portion A of an active area of the device of Figure 1A is enlarged to illustrate a plurality of drain fingers 20 that are electrically connected and extend away from each drain pad 10, and a plurality of source fingers 22 that are electrically connected to and extend away from each source pad 12.
  • drain fingers 20 and source fingers 22 alternate along drain pad 16 and source pad 18, whereby an interdigitated configuration is attained.
  • Gate electrode 24 meanders through the space between drain pad 16, drain fingers 20, source pad 18, and source fingers 22, and, although not shown, is connected to a gate runner which electrically connects gate electrode 24 to gate pad 14.
  • a typical HEMT includes substrate 25, which may be formed from GaN, Si, SiC, or Sapphire, first semiconductor body 26 formed from one ⁇ i-nitride semiconductor such as GaN and disposed over substrate 25, and a second semiconductor body 28 formed of another HI- nitride semiconductor of a different band gap such as AlGaN disposed over first semiconductor body 26.
  • First semiconductor body 26 and second semiconductor body 28 form heterojunction 30, which due to piezoelectric polarization forms a two dimensional electronic gas (2DEG) at or near heterojunction 30.
  • the 2DEG so formed is highly conductive and serves as a channel for conducting current between a source finger 20 and a drain finger 22. It should be noted that in a typical device source fingers 22 and drain fingers 20 are connected to second semiconductor body 28 by a highly conductive ohmic contact layer 32.
  • gate electrode 24 is insulated form second semiconductor body 28 by gate insulation layer 34.
  • gate electrode 24 can make a schottky contact with second semiconductor body 28, as seen, for example, in Figure ID.
  • the devices illustrated by Figure 1 C and Figure ID are depletion mode devices, meaning that the device is nominally on and the activation of gate electrode 24 in each device by application of an appropriate voltage interrupts the 2DEG to turn the device off. Enhancement mode HEMTs are shown in U.S. Provisional Application Serial No. 60/544,626, filed February 12, 2004, the disclosure of which is incorporated herein by reference and U.S. patent application entitled El-Nitride Bidirectional Switch, filed in the name of Daniel M.
  • Bidirectional devices can include one gate electrode, or two gate electrodes.
  • Figure IE illustrates a bidirectional discrete device which includes two gate electrodes.
  • the prior art devices described with reference to Figures 1A-1E are discrete devices, meaning that each of these devices occupies a single, discrete semiconductor die. Due to the high breakdown voltage and current carrying capabilities El-nitride power devices occupy only a small area on a die. Thus, IE-nitride-based semiconductor power devices are very small compared to silicon-based devices.
  • El-nitride semiconductor power devices need to be packaged so that they may be used in an electronic application, such as a power supply application, or motor control application.
  • the packaging elements are thought to contribute the most to the overall size of the package due to the small size of the El-nitride power devices. Because many power applications require more than one power semiconductor device, it is expected that packaging, not the die, will contribute the most to the amount of space that is occupied by IE-nitride-based power semiconductor packages.
  • an integrated device includes two or more El-nitride power semiconductor devices which are formed in a single common semiconductor die.
  • an integrated device according to the present invention can be packaged in a common package, which results in space saving among other advantages.
  • a device according to the first embodiment of the present invention is an integrated device that includes two El-nitride-based power devices connected in a half-bridge configuration.
  • a device is an integrated device that includes six IE-nitride-based power devices connected to form three half-bridges for use in, for example, a three phase power application.
  • a device according to the third embodiment of the present invention is an integrated device that includes four El-nitride-based power devices connected in a H-bridge configuration.
  • a device is an integrated device which includes two IE-nitride based bidirectional devices connected to form a half-bridge and two IE-nitride based devices having a common drain for use in, for example, boost converter applications.
  • a device is an integrated device which include four El-nitride based schottky diodes in a full bridge configuration.
  • Figure 1 A is a top plan view of a discrete IE-nitride power device according to the prior art.
  • Figure IB is an enlarged view of portion A of an active area of the device shown in Figure 1 A.
  • Figure 1C is a cross-sectional view of an example of a device according to the prior art taken along line B-B in Figure IB viewed in the direction of the arrows.
  • Figure ID is a cross-sectional view of another example of a device according to the prior art taken along line B-B in Figure IB viewed in the direction of the arrows.
  • Figure IE shows a top plan view of a bidirectional IE-nitride device which includes two gate electrodes.
  • Figure 2 is a top plan view of an integrated half-bridge device according to the first embodiment of the present invention.
  • Figure 3 is a top plan view of an integrated three-phase device according to the second embodiment of the present invention.
  • Figure 4 is a top plan view of an integrated H-bridge device according to the third embodiment of the present invention.
  • Figure 5 is a top plan view of an integrated device according to the fourth embodiment of the present invention, which includes two El-nitride based bidirectional devices connected to form a half-bridge and two IE-nitride based devices having a common drain.
  • Figure 6A shows a top plan view of a IE-nitride schottky device according to prior art.
  • Figure 6B shows a cross-sectional view of a schottky device according to the prior art taken along line 6B-6B in Figure 6A and viewed in the direction of the arrows.
  • Figure 7 shows a top plan view of an integrated IE-nitride based schottky bridge according to the fifth embodiment of the present invention.
  • Figures 8A-8C illustrate integrated devices according to the present invention each with a feature for attaining electrical isolation between the two devices.
  • an integrated device includes two HEMTs formed on one die and interconnected to form a half-bridge.
  • the term integrated as used herein means that the devices are formed in a common die.
  • an integrated device according to the first embodiment includes a high side HEMT 36, which includes drain pad 10, and gate pad 14, and a low side HEMT 38, which includes source pad 12 and gate pad 14.
  • high side HEMT 36 and low side HEMT 38 are formed in a single die.
  • a device according to the first embodiment can be packaged together, thereby saving space in a power application.
  • the drain pad of low side HEMT 38 and the source pad of high side HEMT 36 are combined into a single pad, switched node pad 40, which serves as the output pad for the half- bridge.
  • an integrated device may include three half-bridges formed in a single die.
  • drain pads 10 of high side HEMTs 36 are interconnected to form a single pad, bus pad 42
  • source pads 12 of low side HEMTs 38 are interconnected to form a single pad, ground pad 44, for the three phase bridge according to the second embodiment of the present invention.
  • an integrated device according to the third embodiment includes four HEMTs formed in a single die and integrated into an H bridge configuration. In this embodiment drain pads 10 of high side HEMTs 36 are connected to one another to form bus pad 42, source pads 12 of low side HEMTs are connected together to form ground pad 44.
  • the source pad of one high side HEMT 36 is common with the drain pad of one low side HEMT 38 to form a first output pad 40A, and the source pad of the other high side HEMT 36 is common with the drain pad of the other low side HEMT 38 to form second output pad 40B.
  • an integrated device may include two bidirectional HEMTs integrated in a half-bridge configuration. That is, one bidirectional HEMT is a high side device 46 and the other is low side device 48. It should be noted that each bidirectional HEMT in the fourth embodiment includes two gate pads 14A, 14B. Also, it should be noted that due to bidirectionality, HEMTs 36, 38 in the fourth embodiment only include power pads 50, rather than source pads and drain pads. As seen in Figure 5, one power pad 52 is common to both bidirectional HEMTs, and serves as the switched output pad 40.
  • a device according to the fourth embodiment includes first HEMT 54 and second HEMT 56 integrated to have a common drain pad 58.
  • a device can be formed which is the integration of two integrated devices.
  • a device according to the fourth embodiment can be used to form a bridgeless boost converter.
  • IE-nitride semiconductor systems can also be used for forming diodes, such as schottky diodes.
  • a schottky diode 60 in IE-nitride system does not include a gate, but rather includes anode electrode 62, which makes a schottky contact with second semiconductor body 28, and cathode electrode 64 which makes an ohmic contact with second semiconductor body 28. It should be noted that similar to a HEMT, anode electrodes 62, and cathode electrodes 64 are connected to respective runners 66 which are in turn electrically connected to anode pad 68 and cathode pad 70.
  • an integrated device is a schottky bridge that includes four IE-nitride schottky diodes that are arranged in a full-bridge configuration. Specifically, anode pads of the first two schottky devices are integrated to form a common anode pad 61, cathode pads of the second two schottky devices are integrated to form a common cathode pad 63, and the cathode pad of each of the first two schottky devices is integrated with the anode pad of one of the other two second schottky devices to form a third common pad 65, and a fourth common pad 67, whereby a schottky bridge is realized.
  • second semiconductor body 28 may be removed to interrupt the 2DEG whenever desired in order to achieve electrical isolation.
  • a recess 104 can be formed in second semiconductor body 28 to a depth that will cause an interruption in the 2DEG and thus electrically isolates the two devices as illustrated in Figure 8 A.
  • Recess 104 can be extended through second semiconductor body 28 to first semiconductor body 26 as illustrated in Figure 8B.
  • second semiconductor layer 28 may include an implanted region 106 that includes crystal damage to first and second semiconductor bodies 26, 28 which causes an interruption in the 2DEG at selected locations between devices 100, 102 to attain electrical isolation between the same. Once an isolated portion of the 2DEG is interrupted, the high resistivity of the first semiconductor body 26 can be relied on for isolation. Thus, two or more devices may be formed on a single die.
  • an HEMT or a schottky device as described herein as prior art is preferred as a building block for an integrated device according to the present invention. However, it should be understood that the present invention is not limited to the configurations disclosed herein.

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Abstract

A III-nitride based integrated semiconductor device which includes at least two III-nitride based semiconductor devices formed in a common die.

Description

INTEGRATED -NITRIDE POWER DEVICES
RELATED APPLICATION
[0001] The present application is based on and claims benefit of U.S. Provisional Application No. 60/544,626 filed February 12, 2004, entitled UI- NITRIDE BIDIRECTIONAL SWITCH, to which a claim of priority is hereby made and the disclosure of which is hereby incorporated by this reference.
FIELD OF THE INVENTION
[0002] The present invention relates to power semiconductor devices and more particularly to integrated power semiconductor devices.
BACKGROUND OF THE INVENTION
[0003] Referring to Figure 1 A, a known, discrete high electron mobility transistor (HEMT) may include drain pad 10, source pad 12, and gate pad 14. Drain pad 10 is electrically connected to a plurality of drain runners 16, and source pad 12 is electrically connected to a plurality of source runners 18. Usually, drain pad 10 and source pad 12, and runners 16, 18 are arranged parallel to one another. In addition, in one conventional arrangement, drain runners 16 and source runners 18 are alternated in order to distribute current evenly through drain pad 10 and source pad 12. In a device according to Figure 1A, the area between each two opposing runners 16, 18 is an active area.
[0004] Referring next to Figure IB, a portion A of an active area of the device of Figure 1A is enlarged to illustrate a plurality of drain fingers 20 that are electrically connected and extend away from each drain pad 10, and a plurality of source fingers 22 that are electrically connected to and extend away from each source pad 12. It should be noted that drain fingers 20 and source fingers 22 alternate along drain pad 16 and source pad 18, whereby an interdigitated configuration is attained. Gate electrode 24 meanders through the space between drain pad 16, drain fingers 20, source pad 18, and source fingers 22, and, although not shown, is connected to a gate runner which electrically connects gate electrode 24 to gate pad 14. [0005] Referring next to Figure 1 C, a typical HEMT includes substrate 25, which may be formed from GaN, Si, SiC, or Sapphire, first semiconductor body 26 formed from one πi-nitride semiconductor such as GaN and disposed over substrate 25, and a second semiconductor body 28 formed of another HI- nitride semiconductor of a different band gap such as AlGaN disposed over first semiconductor body 26. First semiconductor body 26 and second semiconductor body 28 form heterojunction 30, which due to piezoelectric polarization forms a two dimensional electronic gas (2DEG) at or near heterojunction 30. The 2DEG so formed is highly conductive and serves as a channel for conducting current between a source finger 20 and a drain finger 22. It should be noted that in a typical device source fingers 22 and drain fingers 20 are connected to second semiconductor body 28 by a highly conductive ohmic contact layer 32.
[0006] In the device shown by Figure 1C, gate electrode 24 is insulated form second semiconductor body 28 by gate insulation layer 34. In another variation, gate electrode 24 can make a schottky contact with second semiconductor body 28, as seen, for example, in Figure ID. [0007] The devices illustrated by Figure 1 C and Figure ID are depletion mode devices, meaning that the device is nominally on and the activation of gate electrode 24 in each device by application of an appropriate voltage interrupts the 2DEG to turn the device off. Enhancement mode HEMTs are shown in U.S. Provisional Application Serial No. 60/544,626, filed February 12, 2004, the disclosure of which is incorporated herein by reference and U.S. patent application entitled El-Nitride Bidirectional Switch, filed in the name of Daniel M. Kinzer and Robert Beach concurrently with the present application, the disclosure of which is incorporated by reference. Bidirectional devices can include one gate electrode, or two gate electrodes. Figure IE illustrates a bidirectional discrete device which includes two gate electrodes. [0008] The prior art devices described with reference to Figures 1A-1E are discrete devices, meaning that each of these devices occupies a single, discrete semiconductor die. Due to the high breakdown voltage and current carrying capabilities El-nitride power devices occupy only a small area on a die. Thus, IE-nitride-based semiconductor power devices are very small compared to silicon-based devices.
[0009] As with other devices, El-nitride semiconductor power devices need to be packaged so that they may be used in an electronic application, such as a power supply application, or motor control application. In a semiconductor package containing a IE-nitride-based power semiconductor device, the packaging elements are thought to contribute the most to the overall size of the package due to the small size of the El-nitride power devices. Because many power applications require more than one power semiconductor device, it is expected that packaging, not the die, will contribute the most to the amount of space that is occupied by IE-nitride-based power semiconductor packages.
SUMMARY OF THE INVENTION
[0010] According to the present invention an integrated device includes two or more El-nitride power semiconductor devices which are formed in a single common semiconductor die. As a result, in applications requiring more than one power device, an integrated device according to the present invention can be packaged in a common package, which results in space saving among other advantages. [0011] A device according to the first embodiment of the present invention is an integrated device that includes two El-nitride-based power devices connected in a half-bridge configuration.
[0012] A device according to the second embodiment of the present invention is an integrated device that includes six IE-nitride-based power devices connected to form three half-bridges for use in, for example, a three phase power application.
[0013] A device according to the third embodiment of the present invention is an integrated device that includes four El-nitride-based power devices connected in a H-bridge configuration.
[0014] A device according to the fourth embodiment of the present invention is an integrated device which includes two IE-nitride based bidirectional devices connected to form a half-bridge and two IE-nitride based devices having a common drain for use in, for example, boost converter applications.
[0015] A device according to the fifth embodiment of the present invention is an integrated device which include four El-nitride based schottky diodes in a full bridge configuration.
[0016] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRTPTION OF THE DRAWINGS
[0017] Figure 1 A is a top plan view of a discrete IE-nitride power device according to the prior art.
[0018] Figure IB is an enlarged view of portion A of an active area of the device shown in Figure 1 A. [0019] Figure 1C is a cross-sectional view of an example of a device according to the prior art taken along line B-B in Figure IB viewed in the direction of the arrows.
[0020] Figure ID is a cross-sectional view of another example of a device according to the prior art taken along line B-B in Figure IB viewed in the direction of the arrows.
[0021] Figure IE shows a top plan view of a bidirectional IE-nitride device which includes two gate electrodes.
[0022] Figure 2 is a top plan view of an integrated half-bridge device according to the first embodiment of the present invention.
[0023] Figure 3 is a top plan view of an integrated three-phase device according to the second embodiment of the present invention.
[0024] Figure 4 is a top plan view of an integrated H-bridge device according to the third embodiment of the present invention.
[0025] Figure 5 is a top plan view of an integrated device according to the fourth embodiment of the present invention, which includes two El-nitride based bidirectional devices connected to form a half-bridge and two IE-nitride based devices having a common drain.
[0026] Figure 6A shows a top plan view of a IE-nitride schottky device according to prior art.
[0027] Figure 6B shows a cross-sectional view of a schottky device according to the prior art taken along line 6B-6B in Figure 6A and viewed in the direction of the arrows.
[0028] Figure 7 shows a top plan view of an integrated IE-nitride based schottky bridge according to the fifth embodiment of the present invention.
[0029] Figures 8A-8C illustrate integrated devices according to the present invention each with a feature for attaining electrical isolation between the two devices. DETAILED DESCRIPTION OF THE FIGURES
[0030] Referring to Figure 2, an integrated device according to the first embodiment of the present invention includes two HEMTs formed on one die and interconnected to form a half-bridge. The term integrated as used herein means that the devices are formed in a common die. Specifically, an integrated device according to the first embodiment includes a high side HEMT 36, which includes drain pad 10, and gate pad 14, and a low side HEMT 38, which includes source pad 12 and gate pad 14. According to the present invention high side HEMT 36 and low side HEMT 38 are formed in a single die. Thus, a device according to the first embodiment can be packaged together, thereby saving space in a power application. [0031] It should be noted that to form a half-bridge the drain pad of low side HEMT 38 and the source pad of high side HEMT 36 are combined into a single pad, switched node pad 40, which serves as the output pad for the half- bridge.
[0032] Referring next to Figure 3, an integrated device according to the second embodiment may include three half-bridges formed in a single die. As seen in Figure 3, drain pads 10 of high side HEMTs 36 are interconnected to form a single pad, bus pad 42, and source pads 12 of low side HEMTs 38 are interconnected to form a single pad, ground pad 44, for the three phase bridge according to the second embodiment of the present invention. [0033] Referring next to Figure 4, an integrated device according to the third embodiment includes four HEMTs formed in a single die and integrated into an H bridge configuration. In this embodiment drain pads 10 of high side HEMTs 36 are connected to one another to form bus pad 42, source pads 12 of low side HEMTs are connected together to form ground pad 44. The source pad of one high side HEMT 36 is common with the drain pad of one low side HEMT 38 to form a first output pad 40A, and the source pad of the other high side HEMT 36 is common with the drain pad of the other low side HEMT 38 to form second output pad 40B.
[0034] Referring next to Figure 5, an integrated device according to the fourth embodiment of the present invention may include two bidirectional HEMTs integrated in a half-bridge configuration. That is, one bidirectional HEMT is a high side device 46 and the other is low side device 48. It should be noted that each bidirectional HEMT in the fourth embodiment includes two gate pads 14A, 14B. Also, it should be noted that due to bidirectionality, HEMTs 36, 38 in the fourth embodiment only include power pads 50, rather than source pads and drain pads. As seen in Figure 5, one power pad 52 is common to both bidirectional HEMTs, and serves as the switched output pad 40.
[0035] A device according to the fourth embodiment includes first HEMT 54 and second HEMT 56 integrated to have a common drain pad 58. Thus, according to the fourth embodiment, a device can be formed which is the integration of two integrated devices. A device according to the fourth embodiment can be used to form a bridgeless boost converter. [0036] IE-nitride semiconductor systems can also be used for forming diodes, such as schottky diodes. Referring for example to Figures 6A, 6B in which like numerals identify like numbers, a schottky diode 60 in IE-nitride system does not include a gate, but rather includes anode electrode 62, which makes a schottky contact with second semiconductor body 28, and cathode electrode 64 which makes an ohmic contact with second semiconductor body 28. It should be noted that similar to a HEMT, anode electrodes 62, and cathode electrodes 64 are connected to respective runners 66 which are in turn electrically connected to anode pad 68 and cathode pad 70. [0037] Referring to Figure 7, an integrated device according to the fifth embodiment is a schottky bridge that includes four IE-nitride schottky diodes that are arranged in a full-bridge configuration. Specifically, anode pads of the first two schottky devices are integrated to form a common anode pad 61, cathode pads of the second two schottky devices are integrated to form a common cathode pad 63, and the cathode pad of each of the first two schottky devices is integrated with the anode pad of one of the other two second schottky devices to form a third common pad 65, and a fourth common pad 67, whereby a schottky bridge is realized.
[0038] It should be noted that in an integrated device according to the present invention, because two or more devices are formed in one die, there may be a need for electrically isolating the devices. To achieve isolation, all or a portion of second semiconductor body 28 may be removed to interrupt the 2DEG whenever desired in order to achieve electrical isolation. Thus, for example, when in an integrated device according to the present invention, two HEMTs 100, 102 are found in a common die, a recess 104 can be formed in second semiconductor body 28 to a depth that will cause an interruption in the 2DEG and thus electrically isolates the two devices as illustrated in Figure 8 A. Recess 104 can be extended through second semiconductor body 28 to first semiconductor body 26 as illustrated in Figure 8B. [0039] Alternatively, as seen, for example, in Figure 8C, second semiconductor layer 28 may include an implanted region 106 that includes crystal damage to first and second semiconductor bodies 26, 28 which causes an interruption in the 2DEG at selected locations between devices 100, 102 to attain electrical isolation between the same. Once an isolated portion of the 2DEG is interrupted, the high resistivity of the first semiconductor body 26 can be relied on for isolation. Thus, two or more devices may be formed on a single die. [0040] It should be noted that an HEMT or a schottky device as described herein as prior art, is preferred as a building block for an integrated device according to the present invention. However, it should be understood that the present invention is not limited to the configurations disclosed herein. [0041] Furthermore, although a GaN/AlGaN heterojunction is preferred, other IE-nitride combinations are within the scope of the present invention. [0042] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims

WHAT IS CLAIMED IS: 1. An integrated semiconductor device comprising: a first El-nitride based semiconductor device; a second IE-nitride based semiconductor device; wherein said first El-nitride based semiconductor device and said second IE-nitride based semiconductor device are formed in a common die to form an integrated device.
2. An integrated device according to claim 1, wherein said first and said second semiconductor device are high electron mobility transistors.
3. An integrated device according to claim 1, wherein said first and said second semiconductor devices are integrated to form a half-bridge.
4. An integrated device according to claim 3, wherein said half- bridge includes a switched node pad electrically connected and common to both said first and said second IE-nitride semiconductor devices.
5. An integrated device according to claim 1, further comprising a third IE-nitride semiconductor device and a fourth IE-nitride semiconductor device formed in said common die.
6. A integrated device according to claim 5, wherein said first, said second, said third, and said fourth semiconductor devices are high electron mobility transistors interconnected to form an H bridge.
7. An integrated device according to claim 5, wherein said first, said second, said third and said fourth semiconductor devices are schottky diodes interconnected to form a rectifier bridge.
8. An integrated device according to claim 5, wherein said first and said second devices are bidirectional and are interconnected to form a half- bridge, and said third and said fourth devices are high electron mobility transistors interconnected to have a common drain.
9. An integrated device according to claim 1, wherein said first and said second semiconductor devices are interconnected to form a first half- bridge, and further comprising a third, a fourth, a fifth and a six IE-nitride semiconductor devices all formed in a common die, wherein said fourth and said third and said fourth device are connected to form a second half-bridge, and said fifth and said sixth semiconductor device are connected to form a third half-bridge.
10. An integrated device according to claim 9, wherein said first, said second, said third, said fourth, said fifth, and said sixth devices are high electron mobility transistors.
11. An integrated device according to claim 9, wherein each half bridge includes a switched node pad common to its respective devices.
12. An integrated device according to claim 9, wherein each half bridge is connected to a common bus pad, and a common ground pad.
13. An integrated device according to claim 1, wherein said IE- nitride semiconductor device are formed in a die which include a first IE- semiconductor body of a first kind, and a second semiconductor body of a second kind, said second semiconductor body having a different band gap than said first semiconductor body.
14. An integrated device according to claim 13, wherein said each semiconductor device includes two spaced ohmic electrodes and a gate electrode.
15. An integrated device according to claim 14, wherein said gate electrode makes a schottky contact with said second semiconductor body.
16. An integrated device according to claim 14, wherem said gate electrode is insulated from said second semiconductor body by a gate insulation body.
17. An integrated device according to claim 13, wherein at least one of said semiconductor devices includes an ohmic electrode and a schottky electrode.
18. An integrated device according to claim 13, wherein said first semiconductor body is comprised of GaN, and said second semiconductor body is comprised of AlGaN.
19. An integrated device according to claim 13, wherein said devices are electrically isolated from one another.
20. An integrated device according to claim 19, wherein a recess is formed in said second semiconductor body to electrically isolate said devices.
21. An integrated device according to claim 20, wherein said recess reaches said first semiconductor body.
22. An integrated device according to claim 19, wherein said second semiconductor body includes implanted region to isolate said semiconductor devices.
PCT/US2005/004388 2004-02-12 2005-02-14 Integrated iii-nitride power devices Ceased WO2005079293A2 (en)

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US20050189562A1 (en) 2005-09-01
KR100868103B1 (en) 2008-11-11
KR20060110357A (en) 2006-10-24

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