WO2005071557A2 - A multiple address two channel bus structure - Google Patents

A multiple address two channel bus structure Download PDF

Info

Publication number
WO2005071557A2
WO2005071557A2 PCT/US2005/001590 US2005001590W WO2005071557A2 WO 2005071557 A2 WO2005071557 A2 WO 2005071557A2 US 2005001590 W US2005001590 W US 2005001590W WO 2005071557 A2 WO2005071557 A2 WO 2005071557A2
Authority
WO
WIPO (PCT)
Prior art keywords
read
write
address
channel
data
Prior art date
Application number
PCT/US2005/001590
Other languages
French (fr)
Other versions
WO2005071557A3 (en
Inventor
Richard Gerard Hofmann
Jaya Prakash Subramaniam Ganasan
Thomas John Lowery
Perry Willmann Remaklus, Jr.
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to BRPI0507033-3A priority Critical patent/BRPI0507033A/en
Priority to JP2006551212A priority patent/JP2007519121A/en
Priority to DE602005010048T priority patent/DE602005010048D1/en
Priority to EP05711605A priority patent/EP1709543B1/en
Priority to CN2005800074451A priority patent/CN1930563B/en
Publication of WO2005071557A2 publication Critical patent/WO2005071557A2/en
Publication of WO2005071557A3 publication Critical patent/WO2005071557A3/en
Priority to IL177023A priority patent/IL177023A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Definitions

  • the present disclosure relates generally to digital systems, and more specifically, to a multiple address two channel bus structure.
  • a bus is a channel or path between components in a computer.
  • a typical computer includes a processor with system memory.
  • a high bandwidth system bus may be used to support communications between the processor and system memory, h addition, there may also be a lower performance bus which is used to transfer data to lower bandwidth components. In some cases, there may also be a configuration bus which is used for the purpose of programming various resources. Bridges may be used to efficiently transfer data between the higher and lower bandwidth buses, as well as provide protocol translation.
  • a shared bus provides a means for any number of components to communicate over a common path or channel.
  • Point-to-point switching connections have become more popular. Point-to-point switching connections provide a direct connection between two components on the bus while they are communicating with each other. Multiple direct links may be used to allow several components to communicate without slowing each other down.
  • Conventional bus design commonly includes independent and separate read, write and one or more address channels.
  • a processor for example, can read or write to system memory by placing an address location on the address channel and sending the appropriate read/write control signal. When the microprocessor writes data to system memory, it sends the data over the write channel. When the microprocessor reads data from system memory, it receives the data over the read channel.
  • a method of communicating between a sending component and a receiving component over a bus includes broadcasting from the sending component on a first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data.
  • the sending component also broadcasts the read and write address information multiple address locations at a time.
  • the method further includes storing the write data broadcast on the first channel at the receiving component based on the write address information, retrieving read data from the receiving component based on the read address information, and broadcasting from the receiving component the retrieved read data on the second channel.
  • a processing system in another aspect of the present invention, includes a bus having first and second channels, a sending component and a receiving component.
  • the sending component is configured to broadcast on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data.
  • the sending component is further configured to broadcast the read and write address information multiple address locations at a time.
  • the receiving component is configured to store the write data broadcast on the first channel based on the write address information, retrieve read data based on the read address information, and broadcast the retrieved read data on the second channel to the sending component.
  • a processing system in a further aspect of the present invention, includes a bus having first and second channels.
  • the processing system also includes means for broadcasting on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data, the read and write address information being broadcast multiple address locations at a time.
  • the processing system further includes means for storing the -write data broadcast on the first channel based on the write address information, retrieving the read data based on the read address information, and broadcasting the retrieved read data on the second channel to the sending component.
  • FIG. 1 is a conceptual block diagram illustrating an example of a point-to- point connection over a two channel bus between two components in a processing system
  • FIG. 2 is a conceptual block diagram illustrating an example of a point-to- point connection over a multiple address two channel bus between two components in a processing system
  • FIG. 3 is a timing diagram showing four address pipelined read operations over a multiple address two channel bus;
  • FIG. 4 is a timing diagram showing six address pipelined read operations over a multiple address two channel bus;
  • FIG. 5 is a timing diagram showing read and write operations over a multiple address two channel bus.
  • FIG. 1 is a conceptual block diagram illustrating an example of a point-to- point connection over a bus between two components in a processing system.
  • the processing system 100 may be a collection of components that cooperate to perform one or more processing functions. Commonly, the processing system will be a computer, or resident in a computer, and capable of processing, retrieving and storing information. The processing system may be a stand-alone system. Alternatively, the processing system may be embedded in any device, including by way of example, a cellular telephone.
  • the processing system 100 is shown with a sending component 102 in communication with a receiving component 104 over a bus 106.
  • the bus 106 is a dedicated bus between the sending component 102 and the receiving component.
  • the sending component 102 communicates with the receiving component 104 with a point-to-point connection over the bus 106 through a bus interconnect (not shown).
  • a bus interconnect not shown.
  • the sending component 102 may be any type of bus mastering component including, by way of example, a microprocessor, a digital signal processor (DSP), a direct memory access controller, a bridge, a programmable logic component, discrete gate or transistor logic, or any other information processing component.
  • DSP digital signal processor
  • a bridge a programmable logic component, discrete gate or transistor logic, or any other information processing component.
  • the receiving component 104 may be any storage component, including, by way of example, registers, memory, a bridge, or any other component capable of retrieving and storing information.
  • the storage capacity at each address location of the receiving component may vary depending on the particular application and the overall design constraints. For the purposes of explanation, the receiving component will be described with a storage capacity of 1-byte per address location.
  • the complexity of the bus 106 may be reduced in this example by eliminating the address channel that is used in conventional bus structures.
  • the elimination of the address channel may be achieved by redefining the write channel as a "transmit channel" 108.
  • the transmit channel 108 may be used as a generic medium for broadcasting information between the sending component 102 and the receiving component 104 in a time division multiplexed fashion.
  • the sending component 102 may read from or write to the receiving component 104.
  • the sending component 102 may sample one or more sideband signals 112 for an acknowledgement that the receiving component 104 is ready to perform a write operation. If the sending component 102 receives an acknowledgement, it may broadcast an address location on the transmit channel 108 followed by write data.
  • the sending component 102 may also use one or more sideband signals 114 to request a write operation and indicate the number data bytes being broadcast. If the write data is multiple bytes, then the receiving component 104 may store the data in a block of sequential address locations beginning with the address location broadcast on the transmit channel 108.
  • the sending device broadcasts an address location IOO HEX followed by 4-bytes of write data
  • the receiving component may write the data to a block of address locations starting at IOO HEX and ending at 103 HEX -
  • the 4- bytes of write data is referred to as the "payload.”
  • the sending component 102 may sample one or more of the sideband signals 112 for an acknowledgement that the receiving component 104 is ready to perform a read operation. If the sending component 102 receives an acknowledgement, it may broadcast an address location on the transmit channel 108. The sending component 102 may use one or more of the sideband signals 114 to request a read operation and indicate the number data bytes being broadcast. If the read data is multiple bytes, then the receiving component may read data from a block of sequential address locations beginning with the address location broadcast on the transmit channel 108. By way of example, if the sending device broadcasts an address location 200 HE X and requests 4-bytes of read data, the receiving component may retrieve the read data from a block of address locations starting at 200 HEX and ending at 203 HE X-
  • FIG. 2 is a conceptual block diagram illustrating an example of a point-to- point connection over a multiple address two channel bus between two components in a processing system.
  • the sending component 102 may use the transmit channel 108 to broadcast two different address locations 104a and 104b within the receiving component 104 at the same time.
  • One or more sideband signals 114a and 114b may be associated with each of the address locations.
  • the sending component 102 may also use the transmit channel 108 to broadcast a single address location to two different receiving components at the same time in shared bus applications. If the receiving component is a bridge, one or both address locations may be used to access the bridge, or alternatively access another receiving component on the other side of the bridge.
  • Alternative embodiments of the bus may include a transmit channel configured to support a simultaneous broadcast of any number of address locations to multiple receiving components, multiple address locations within a receiving component, or any combination thereof.
  • the use of the transmit channel 108 to simultaneously broadcast multiple address locations may improve performance by providing address information to the receiving component sooner, thus decreasing the amount of read latency.
  • the simultaneous broadcast of multiple address locations may allow a more efficient return of read data to the sending component 102 over the read channel 110.
  • the transmit channel 108 may be 64-bits wide to support two 32-bit addresses.
  • the first 32-bit address which will be referred to as "Address A”
  • the second 32-bit address which will be referred to as "Address B”
  • the sending component 102 may initiate (1) two read operations simultaneously, (2) two write operations simultaneously, (3) simultaneous read and write operations at different address locations, or (4) simultaneous read and write operation to the same address location or locations.
  • An implicit addressing scheme may be used to handle simultaneous read and write operation requests to the same address location.
  • the sending component 102 may broadcast the address location for the first operation as Address A, and the address location for the second operation as Address B.
  • the read/write sequence performed by the receiving component 104 will be based on this addressing scheme to maintain sequential consistency.
  • the sending device signals a 1-byte write operation for Address A and a 1-byte read operation for Address B
  • the receiving component 104 will wait until the data broadcast on the transmit channel is written to the address location before providing the newly written data at this address location to the read channel for transmission to the sending component 102.
  • the sending device signals a 1-byte read operation for Address A and a 1-byte write operation for Address B
  • the receiving component 104 will provide the data at this address location to the read channel 110 before writing the new data from the transmit channel 108 to this address location.
  • read and write operation requests to the same address location may be broadcast sequentially.
  • the sending component 102 may broadcast the address location for the first operation as Address A during a first clock cycle, and the address location for the second operation as Address B during the following clock cycle.
  • the receiving component may perform the operation requested during the first clock cycle before performing the operation requested during the second clock cycle.
  • An implicit addressing scheme may also be used to control the sequence of data broadcast on the transmit and read channels 108 and 110.
  • the sending component initiates a read operation from two address locations simultaneously, the receiving component 104 may broadcast the read data associated with Address A followed by the read data associated with Address B.
  • the sending component may broadcast the write data associated with Address A followed by the write data associated with Address B.
  • sideband signaling may be used to control the broadcast sequence of the read and write data.
  • FIG. 3 is a timing diagram showing four address pipelined read operations over a multiple address two channel bus.
  • a System Clock 302 may be used to synchronize communications between the sending component and the receiving component.
  • the System Clock 302 is shown with fourteen clock cycles, with each cycle numbered sequentially for ease of explanation.
  • Two read operations may be initiated by the sending component during the second clock cycle 303. This may be achieved by broadcasting an address location associated with a first read operation R ⁇ as Address A and an address location associated with a second read operation R 2 as Address B over the Transmit Channel 318.
  • the read operation may be selected by asserting read/write signal indicators for Addresses A and B to "1".
  • the read/write signal indicators for Addresses A and B are shown in FIG.
  • the sending component may also alert the receiving component that address locations will be broadcast by asserting ANalidA 304 and ANalidB 310 signals. Finally, the sending component may provide the receiving component with signals indicating the size of the payload for the read operations. These signals are shown in FIG. 3 as SizeA 308 for Address A and SizeB 314 for Address B.
  • the number of clock cycles needed to broadcast the payload commonly referred to in the art as data beats, may be used to indicate the size of the payload.
  • SizeA 308 and SizeB 314 both indicate two data beats. This means that one 16-byte payload is to be read from a block of 16 sequential address locations starting at Address A and another 16-byte payload is to be read from a block of 16 sequential address locations starting at Address B.
  • the receiving component may monitor the ANalidA 304 and ANalidB 310 signals to determine when valid address locations are broadcast on the Transmit Channel 318.
  • the receiving component may sample the address information from the Transmit Channel 318 and sample the read/write signal indicators R/W A 306 and R/W B 312 to determine whether the sending component is requesting a read or write operation for Addresses A and B. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations.
  • the receiving component may also assert a Transfer Ack 316 signal indicating that it has successfully received the broadcast.
  • the sending component may detect the assertion of the Transfer Ack 316 signal, and respond by initiating two more read operations. This may be achieved by broadcasting an address location associated with a third read operation R 3 as Address A and an address location associated with a fourth read operation t as Address B over the Transmit Channel 318, setting the read/write signal indicators R/W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals. In this case, the size of the payload for both read operations is 16-bytes.
  • the receiving component may detect the assertion of the ANalidA 304 and ANalidB 310 signals, sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations. The receiving component may also assert the Transfer Ack 316 signal indicating that it has successfully received the broadcast.
  • the sending component may deassert the ANalidA 304 and ANalidB 310 signals, indicating to the receiving component that a read or write operation will not be requested during the fourth clock cycle 307.
  • the first 8-bytes of the read data Ri(l) associated with the first read operation R may be retrieved from the receiving component and broadcast on the Read Channel 322 during the sixth clock cycle 311, and the second 8-bytes of read data Ri(2) associated with the first read operation R ⁇ may be retrieved from the receiving component and broadcast on the Read Channel 322 during the seventh clock cycle 313.
  • the read data R 2 (l) and R 2 (2) associated with the second read operation R 2 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the eighth and ninth clock cycles 315 and 317
  • the read data R 3 (l) and R (2) associated with the third read operation R 3 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the tenth and eleventh clock cycles 319 and 321
  • .(2) associated with the fourth read operation t may be retrieved from the receiving component and broadcast on the Read Channel 322 during the twelfth and thirteenth clock cycles 323 and 325.
  • the receiving component may assert a Read Ack 324 signal to indicate to the sending component that it is broadcasting read data on the Read Channel 322.
  • FIG. 4 is a timing diagram showing six address pipelined read operations over a multiple address two channel bus. The four read operations described earlier in connection with FIG. 3 are repeated in FIG. 4, and therefore, do not warrant further discussion here.
  • Two additional read operations may be initiated by the sending component in the fourth clock cycle 307 by broadcasting an address location associated with a fifth read operation R 5 as Address A and an address location associated with a sixth read operation R 6 as Address B over the Transmit Channel 318, setting read/write signal indicators R/W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals.
  • the receiving component may deassert the Transfer Ack 316 signal indicating that it cannot currently accept the broadcast because, by way of example, it's address queue is full.
  • the sending component may detect that the Transfer Ack 316 signal is not asserted at the end of the fourth clock cycle 307.
  • the sending component may continue to broadcast the address locations for the fifth and sixth read operations R 5 and R on the Transmit Channel 318, along with the appropriate settings for the read/write signal indicators R/W A 306 and R/W B 312, the ANalidA 304 and ANalidB 310 signals, and the SizeA 308 and SizeB 314 signals, until the sending component detects the assertion of the Transfer Ack 316 signal from the receiving component.
  • the broadcast is repeated in the fifth, sixth and seventh clock cycles 309, 311 and 313.
  • the receiving component may be able to receive a broadcast on the Transmit Channel 318 and perform the requested operation, as indicated by the assertion of the Transfer Ack 316 signal.
  • the sending component determines that it does not need to send a repeat broadcast during the eighth clock cycle 315, and deasserts the ANalidA 304 and ANalidB 310 signals.
  • the sending component may queue the broadcast for the address locations associated with the fifth and sixth read operations when it detects that the Transfer Ack 316 signal is not asserted at the end of the fourth clock cycle 307.
  • the broadcast may be queued until the receiving component indicates that it is ready to accept a broadcast over the Transmit Channel 318 by reasserting the Transfer Ack 316 signal.
  • the sending component may monitor the Transfer Ack 316 signal until it is asserted by the receiving component in the seventh clock cycle 313.
  • the sending component When the sending component detects that the Transfer Ack 316 is asserted, it may rebroadcast the queued address locations over the Transmit Channel 318 in the eighth clock cycle 315, along with the appropriate settings for the read/write signal indicators R/W A 306 and R/W B 312, the ANalidA 304 and ANalidB 310 signals, and the SizeA 308 and SizeB 314 signals.
  • the sending component may broadcast new address locations on the Transmit Channel 318, or broadcast any outstanding write data to the receiving component.
  • the receiving component may be able to receive a broadcast on the Transmit Channel 318 and perform the requested operation in the seventh clock cycle 313. More specifically, the receiving component may sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving the read data at the new address locations.
  • the first 8-bytes of the read data R 5 (l) associated with the fifth read operation R 5 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the fourteenth clock cycle 327, and the second 8-bytes of read data R 5 (2) associated with the fifth read operation R 5 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the fifteenth clock cycle 329.
  • the first 8-bytes of the read data R 6 (l) associated with the sixth read operation R may be retrieved from the receiving component and broadcast on the Read Channel 322 during the sixteenth clock cycle 331, and the second 8-bytes of read data R ⁇ (2) associated with the sixth read operation Re may be retrieved from the receiving component and broadcast on the Read Channel 322 during the seventeenth clock cycle 333
  • FIG. 5 is a timing diagram showing read and write operations over a multiple address two channel bus.
  • Two read operations may be initiated by the sending component during the second clock cycle 303. This may be achieved by broadcasting an address location associated with a first read operation R 1 as Address A and an address location associated with a second read operation R 2 as Address B over the Transmit Channel 318, setting read/write signal indicators R W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals. In this case, the size of the payload for the read operation at both address locations is 16-bytes.
  • the receiving component may detect the assertion of the ANalidA 304 and ANalidB 310 signals, sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations. The receiving component may also assert the Transfer Ack 316 signal indicating that it has successfully received the broadcast.
  • the sending component may detect the assertion of the Transfer Ack 316 signal at the end of the second clock cycle 303. Responsive to the assertion of the Transfer Ack 316 signal, the sending component may deassert the ANalidA 304 and ANalidB signals 310. By deasserting the ANalidA 304 and the ANalidB 310 signals, the sending component is indicating to the receiving component that it will either broadcast write data on the Transmit Channel 318, or nothing at all on the Transmit Channel 318. In this case, nothing will be broadcast on the Transmit Channel 318 because a write operation request has not been made.
  • the sending component may initiate a write operation by broadcasting an address location associated with a first write operation W ⁇ as Address A over the Transmit Channel 318, setting the read/write signal indicator R/W A 306 to "0" to indicate a write operation, asserting the ANalidA 304 signal to alert the receiving component of an address location broadcast, and indicating to the receiving component the size of the payload using the SizeA 308 signal.
  • the size of the payload for the write operation is 32-bytes as indicated in FIG. 5 by four data beats.
  • the receiving component may assert the Transfer Ack 316 signal during the fifth clock cycle 309 indicating that it has successfully received the broadcast.
  • the receiving component may also assert the Write Ack 320 signal during the sixth clock cycle 311 indicating that it is ready to write data to the address location associated with the first write operation Wi.
  • the sending component may deassert the ANalidA signal 304.
  • the sending component is indicating to the receiving component that it will either broadcast write data on the Transmit Channel 318, or nothing at all on the Transmit Channel 318.
  • the receiving component will be looking for the first 8-bytes of the write data associated with the first write operation Wi.
  • a second write operation may be requested at any time by asserting the ANalidA and/or ANalidB signals 304 and 310, the sending component will not send write data for the second write operation until the broadcast of the write data for the first write operation is complete. This approach tends to reduce sideband signaling requirements that might otherwise be required to indicate which write operation the payload is associated with.
  • the sending component may broadcast on the Transmit Channel 318 the first 8-bytes of the write data Wi(l) associated with the first write operation Wi.
  • the receiving component may write the data to the appropriate block of 8 address locations.
  • the first 8-bytes of the read data R ⁇ (l) associated with the first read operation R ⁇ may be retrieved from the receiving component and broadcast on the Read Channel 322.
  • the receiving component may also assert the Read Ack 324 signal indicating that it is sending read data on the Read Channel 322.
  • the sending component may broadcast on the Transmit Channel 318 the second 8-bytes of the write data Wi(2) associated with the first write operation W ⁇ .
  • the receiving component may write the data to the appropriate block of 8 address locations.
  • the second 8-bytes of the read data R t (2) associated with the first read operation R t may be retrieved from the receiving component and broadcast on the Read Channel 322.
  • the receiving component may also assert the Read Ack 324 signal.
  • the sending component may temporarily suspend broadcasting write data to initiate a new write operation followed by a new read operation. This may be achieved by broadcasting an address location W 2 associated with a second write operation as Address A and an address location associated with a third read operation R 3 as Address B over the Transmit Channel 318, setting the read/write indicator signal R/W A 306 to "0," setting the read/write indicator signal R/W B 312 to "1,” asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals.
  • the payload size for both the write and read operations is 16-bytes.
  • the first 8-bytes of the read data R 2 (l) associated with the second read operation R 2 may be retrieved by the receiving component and broadcast on the Read Channel 322.
  • the receiving component may also assert the Read Ack 324 signal.
  • the sending component may deassert the ANalidA 304 and the ANalidB 310 signals indicating to the receiving component that the sending component will resume broadcasting write data on the Transmit Channel 318.
  • the sending component may broadcast on the Transmit Channel 318 the third 8-bytes of the write data W ⁇ 3) associated with the first write operation Wi.
  • the receiving component may write the data to the appropriate block of 8 address locations.
  • the second 8-bytes of the read data R 2 (2) associated with the second read operation R 2 may be retrieved from the receiving component and the broadcast on the Read Channel 322.
  • the receiving component has completed both read operations initiated by the sending component during the second clock cycle 303, and therefore, may deassert the Read Ack 324 signal. Due to the read latency of the receiving component, it may not ready to broadcast the read data associated with the third read operation R 3 .
  • the sending component may broadcast on the Transmit Channel 318 the final 8- bytes of the write data Wi(4) associated with the first write operation W ⁇ in the tenth clock cycle 319.
  • the sending component may also broadcast the first 8-bytes of the write data W 2 (l) associated with the second write operation W 2 in the eleventh clock cycle 321 and the last 8-bytes of the write data W 2 (2) associated with the second write operation W 2 in the twelfth clock cycle 323.
  • the receiving component may write this data to the appropriate block of 16 address locations. With this broadcast, the outstanding write operations are complete, and therefore, the receiving component may deassert the Write Ack 320 signal in the following clock cycle 325.
  • the first 8-bytes of the read data R 3 (l) associated with the third read operation R 3 may be retrieved from the receiving component and broadcast on the Read Channel 322.
  • the second 8-bytes of read data R 3 (2) associated with the third read operation R 3 may be retrieved from the receiving component and broadcast on the Read Channel 322.
  • the receiving component may deassert the Read Ack 324 signal in the fourteenth clock cycle 327.
  • the ability of the processing system to broadcast address information in the middle of a write operation that extends over multiple clock cycles may depend on the buffering capabilities of the sending and receiving components, hi at least one embodiment of the processing system, the sending component may be implemented with a programmable means for enabling or disabling this feature based on potential performance advantages or supported buffering capabilities.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • a storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in the sending and/or receiving component, or elsewhere.
  • processor and the storage medium may reside as discrete components in the sending and/or receiving component, or elsewhere.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Semiconductor Memories (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

A processing system is disclosed with a sending component and a receiving component connected by a multiple address two channel bus. The sending device may broadcast on the first channel of the bus read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component may also broadcast the read and write address information multiple address locations at a time. The receiving component may store the write data broadcast on the first channel based on the write address information, retrieve the read data from the receiving component based on the read address information, and broadcasting the retrieved read data on the second channel of the bus.

Description

A MULTIPLE ADDRESS TWO CHANNEL BUS STRUCTURE BACKGROUND
Related Application
[0000] This application claims priority to U.S. Provisional Application No. 60/538,505, filed January 22, 2004.
Field
[0001] The present disclosure relates generally to digital systems, and more specifically, to a multiple address two channel bus structure.
Background
[0002] Computers have revolutionized the electronics industry by enabling sophisticated processing tasks to be performed with just a few strokes of a keypad. These sophisticated tasks can involve a number of complex components that communicate with one another in a fast and efficient manner using a bus. A bus is a channel or path between components in a computer.
[0003] A typical computer includes a processor with system memory. A high bandwidth system bus may be used to support communications between the processor and system memory, h addition, there may also be a lower performance bus which is used to transfer data to lower bandwidth components. In some cases, there may also be a configuration bus which is used for the purpose of programming various resources. Bridges may be used to efficiently transfer data between the higher and lower bandwidth buses, as well as provide protocol translation.
[0004] Commonly buses resident in a computer have been implemented as shared buses. A shared bus provides a means for any number of components to communicate over a common path or channel. Recently by point-to-point switching connections have become more popular. Point-to-point switching connections provide a direct connection between two components on the bus while they are communicating with each other. Multiple direct links may be used to allow several components to communicate without slowing each other down. [0005] Conventional bus design commonly includes independent and separate read, write and one or more address channels. A processor, for example, can read or write to system memory by placing an address location on the address channel and sending the appropriate read/write control signal. When the microprocessor writes data to system memory, it sends the data over the write channel. When the microprocessor reads data from system memory, it receives the data over the read channel.
[0006] Although this particular bus structure provides a fairly standardized way to communicate between components of a computer, it requires a number of dedicated channels. These channels require driver, receiver and buffer circuits, all which consume power. In integrated circuit applications, these channels occupy valuable chip area. Accordingly, there is a need in the art for a simplified bus structure.
SUMMARY
[0007] In one aspect of the present invention, a method of communicating between a sending component and a receiving component over a bus includes broadcasting from the sending component on a first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component also broadcasts the read and write address information multiple address locations at a time. The method further includes storing the write data broadcast on the first channel at the receiving component based on the write address information, retrieving read data from the receiving component based on the read address information, and broadcasting from the receiving component the retrieved read data on the second channel.
[0008] In another aspect of the present invention, a processing system includes a bus having first and second channels, a sending component and a receiving component. The sending component is configured to broadcast on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component is further configured to broadcast the read and write address information multiple address locations at a time. The receiving component is configured to store the write data broadcast on the first channel based on the write address information, retrieve read data based on the read address information, and broadcast the retrieved read data on the second channel to the sending component.
[0009] In a further aspect of the present invention, a processing system includes a bus having first and second channels. The processing system also includes means for broadcasting on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data, the read and write address information being broadcast multiple address locations at a time. The processing system further includes means for storing the -write data broadcast on the first channel based on the write address information, retrieving the read data based on the read address information, and broadcasting the retrieved read data on the second channel to the sending component.
[0010] It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein:
[0012] FIG. 1 is a conceptual block diagram illustrating an example of a point-to- point connection over a two channel bus between two components in a processing system;
[0013] FIG. 2 is a conceptual block diagram illustrating an example of a point-to- point connection over a multiple address two channel bus between two components in a processing system;
[0014] FIG. 3 is a timing diagram showing four address pipelined read operations over a multiple address two channel bus; [0015] FIG. 4 is a timing diagram showing six address pipelined read operations over a multiple address two channel bus; and
[0016] FIG. 5 is a timing diagram showing read and write operations over a multiple address two channel bus.
DETAILED DESCRIPTION
[0017] The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. Each embodiment described in this disclosure is provided merely as an example or illustration of the present invention, and should not necessarily be construed as preferred or advantageous over other embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the invention.
[0018] FIG. 1 is a conceptual block diagram illustrating an example of a point-to- point connection over a bus between two components in a processing system. The processing system 100 may be a collection of components that cooperate to perform one or more processing functions. Commonly, the processing system will be a computer, or resident in a computer, and capable of processing, retrieving and storing information. The processing system may be a stand-alone system. Alternatively, the processing system may be embedded in any device, including by way of example, a cellular telephone.
[0019] The processing system 100 is shown with a sending component 102 in communication with a receiving component 104 over a bus 106. In one embodiment of the processing system 100, the bus 106 is a dedicated bus between the sending component 102 and the receiving component. In another embodiment of the processing system 100, the sending component 102 communicates with the receiving component 104 with a point-to-point connection over the bus 106 through a bus interconnect (not shown). Moreover, as those skilled in the art will readily appreciate, the inventive aspects described throughout this disclosure are not limited to a dedicated bus or point- to-point switching connection, but may be applied to any type of bus technology including, by way of example, a shared bus.
[0020] The sending component 102 may be any type of bus mastering component including, by way of example, a microprocessor, a digital signal processor (DSP), a direct memory access controller, a bridge, a programmable logic component, discrete gate or transistor logic, or any other information processing component.
[0021] The receiving component 104 may be any storage component, including, by way of example, registers, memory, a bridge, or any other component capable of retrieving and storing information. The storage capacity at each address location of the receiving component may vary depending on the particular application and the overall design constraints. For the purposes of explanation, the receiving component will be described with a storage capacity of 1-byte per address location.
[0022] The complexity of the bus 106 may be reduced in this example by eliminating the address channel that is used in conventional bus structures. The elimination of the address channel may be achieved by redefining the write channel as a "transmit channel" 108. The transmit channel 108 may be used as a generic medium for broadcasting information between the sending component 102 and the receiving component 104 in a time division multiplexed fashion.
[0023] The sending component 102 may read from or write to the receiving component 104. In the case where the sending component 102 writes to the receiving component 104, the sending component 102 may sample one or more sideband signals 112 for an acknowledgement that the receiving component 104 is ready to perform a write operation. If the sending component 102 receives an acknowledgement, it may broadcast an address location on the transmit channel 108 followed by write data. The sending component 102 may also use one or more sideband signals 114 to request a write operation and indicate the number data bytes being broadcast. If the write data is multiple bytes, then the receiving component 104 may store the data in a block of sequential address locations beginning with the address location broadcast on the transmit channel 108. By way of example, if the sending device broadcasts an address location IOOHEX followed by 4-bytes of write data, the receiving component may write the data to a block of address locations starting at IOOHEX and ending at 103HEX- The 4- bytes of write data is referred to as the "payload."
[0024] In the case where the sending component 102 reads from the receiving component 104, the sending component 102 may sample one or more of the sideband signals 112 for an acknowledgement that the receiving component 104 is ready to perform a read operation. If the sending component 102 receives an acknowledgement, it may broadcast an address location on the transmit channel 108. The sending component 102 may use one or more of the sideband signals 114 to request a read operation and indicate the number data bytes being broadcast. If the read data is multiple bytes, then the receiving component may read data from a block of sequential address locations beginning with the address location broadcast on the transmit channel 108. By way of example, if the sending device broadcasts an address location 200HEX and requests 4-bytes of read data, the receiving component may retrieve the read data from a block of address locations starting at 200HEX and ending at 203HEX-
[0025] FIG. 2 is a conceptual block diagram illustrating an example of a point-to- point connection over a multiple address two channel bus between two components in a processing system. In the embodiment shown in FIG. 2, the sending component 102 may use the transmit channel 108 to broadcast two different address locations 104a and 104b within the receiving component 104 at the same time. One or more sideband signals 114a and 114b may be associated with each of the address locations. It will be understood that the sending component 102 may also use the transmit channel 108 to broadcast a single address location to two different receiving components at the same time in shared bus applications. If the receiving component is a bridge, one or both address locations may be used to access the bridge, or alternatively access another receiving component on the other side of the bridge. Alternative embodiments of the bus may include a transmit channel configured to support a simultaneous broadcast of any number of address locations to multiple receiving components, multiple address locations within a receiving component, or any combination thereof.
[0026] The use of the transmit channel 108 to simultaneously broadcast multiple address locations may improve performance by providing address information to the receiving component sooner, thus decreasing the amount of read latency. In addition, the simultaneous broadcast of multiple address locations may allow a more efficient return of read data to the sending component 102 over the read channel 110.
[0027] In multiple address bus applications, the transmit channel 108 may be 64-bits wide to support two 32-bit addresses. The first 32-bit address, which will be referred to as "Address A," maybe used to broadcast one address location 104a. The second 32-bit address, which will be referred to as "Address B," may be used to broadcast the other address location 104b. With this configuration, the sending component 102 may initiate (1) two read operations simultaneously, (2) two write operations simultaneously, (3) simultaneous read and write operations at different address locations, or (4) simultaneous read and write operation to the same address location or locations.
[0028] An implicit addressing scheme may be used to handle simultaneous read and write operation requests to the same address location. By way of example, the sending component 102 may broadcast the address location for the first operation as Address A, and the address location for the second operation as Address B. The read/write sequence performed by the receiving component 104 will be based on this addressing scheme to maintain sequential consistency. Thus, if the same address location is used as Address A and Address B, and the sending device signals a 1-byte write operation for Address A and a 1-byte read operation for Address B, then the receiving component 104 will wait until the data broadcast on the transmit channel is written to the address location before providing the newly written data at this address location to the read channel for transmission to the sending component 102. Conversely, if the sending device signals a 1-byte read operation for Address A and a 1-byte write operation for Address B, then the receiving component 104 will provide the data at this address location to the read channel 110 before writing the new data from the transmit channel 108 to this address location.
[0029] Alternatively, read and write operation requests to the same address location may be broadcast sequentially. By way of example, the sending component 102 may broadcast the address location for the first operation as Address A during a first clock cycle, and the address location for the second operation as Address B during the following clock cycle. In this case, the receiving component may perform the operation requested during the first clock cycle before performing the operation requested during the second clock cycle. [0030] An implicit addressing scheme may also be used to control the sequence of data broadcast on the transmit and read channels 108 and 110. By way of example, if the sending component initiates a read operation from two address locations simultaneously, the receiving component 104 may broadcast the read data associated with Address A followed by the read data associated with Address B. Similarly, if the sending component initiates a write operation to two address locations simultaneously, the sending component may broadcast the write data associated with Address A followed by the write data associated with Address B. Alternatively, sideband signaling may be used to control the broadcast sequence of the read and write data. [0031] The various concepts described thus far may be implemented using any number of protocols. In the detailed description to follow, an example of a bus protocol will be presented. This bus protocol is being presented to illustrate the inventive aspects of a processing system, with the understanding that such inventive aspects may be used with any suitable protocol. The basic signaling used for this protocol is shown below in Table 1. Those skilled in the art will readily be able to vary and/or add signals to this protocol in the actual implementation of the bus structure described herein. TABLE 1
Figure imgf000010_0001
Figure imgf000011_0001
[0032] FIG. 3 is a timing diagram showing four address pipelined read operations over a multiple address two channel bus. A System Clock 302 may be used to synchronize communications between the sending component and the receiving component. The System Clock 302 is shown with fourteen clock cycles, with each cycle numbered sequentially for ease of explanation. [0033] Two read operations may be initiated by the sending component during the second clock cycle 303. This may be achieved by broadcasting an address location associated with a first read operation R\ as Address A and an address location associated with a second read operation R2 as Address B over the Transmit Channel 318. The read operation may be selected by asserting read/write signal indicators for Addresses A and B to "1". The read/write signal indicators for Addresses A and B are shown in FIG. 3 as R/W A 306 and R/W B 312, respectively. The sending component may also alert the receiving component that address locations will be broadcast by asserting ANalidA 304 and ANalidB 310 signals. Finally, the sending component may provide the receiving component with signals indicating the size of the payload for the read operations. These signals are shown in FIG. 3 as SizeA 308 for Address A and SizeB 314 for Address B. The number of clock cycles needed to broadcast the payload, commonly referred to in the art as data beats, may be used to indicate the size of the payload. By way of example, SizeA 308 and SizeB 314 both indicate two data beats. This means that one 16-byte payload is to be read from a block of 16 sequential address locations starting at Address A and another 16-byte payload is to be read from a block of 16 sequential address locations starting at Address B.
[0034] The receiving component may monitor the ANalidA 304 and ANalidB 310 signals to determine when valid address locations are broadcast on the Transmit Channel 318. When the receiving component detects the assertion of the ANalidA 304 and ANalidB 310 signals, it may sample the address information from the Transmit Channel 318 and sample the read/write signal indicators R/W A 306 and R/W B 312 to determine whether the sending component is requesting a read or write operation for Addresses A and B. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations. The receiving component may also assert a Transfer Ack 316 signal indicating that it has successfully received the broadcast.
[0035] At the end of the second clock cycle 303, the sending component may detect the assertion of the Transfer Ack 316 signal, and respond by initiating two more read operations. This may be achieved by broadcasting an address location associated with a third read operation R3 as Address A and an address location associated with a fourth read operation t as Address B over the Transmit Channel 318, setting the read/write signal indicators R/W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals. In this case, the size of the payload for both read operations is 16-bytes.
[0036] The receiving component may detect the assertion of the ANalidA 304 and ANalidB 310 signals, sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations. The receiving component may also assert the Transfer Ack 316 signal indicating that it has successfully received the broadcast.
[0037] Once the sending component detects the assertion of the Transfer Ack 316 signal at the end of the third clock cycle 305, it may deassert the ANalidA 304 and ANalidB 310 signals, indicating to the receiving component that a read or write operation will not be requested during the fourth clock cycle 307.
[0038] Due to the read latency of the receiving component, a several clock cycle delay may be experienced before the read data is available, hi this case, the first 8-bytes of the read data Ri(l) associated with the first read operation R may be retrieved from the receiving component and broadcast on the Read Channel 322 during the sixth clock cycle 311, and the second 8-bytes of read data Ri(2) associated with the first read operation R\ may be retrieved from the receiving component and broadcast on the Read Channel 322 during the seventh clock cycle 313.
[0039] hi a similar fashion, the read data R2(l) and R2(2) associated with the second read operation R2 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the eighth and ninth clock cycles 315 and 317, the read data R3(l) and R (2) associated with the third read operation R3 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the tenth and eleventh clock cycles 319 and 321, and the read data R4(l) and R|.(2) associated with the fourth read operation t may be retrieved from the receiving component and broadcast on the Read Channel 322 during the twelfth and thirteenth clock cycles 323 and 325.
[0040] During this eight clock cycle broadcast, the receiving component may assert a Read Ack 324 signal to indicate to the sending component that it is broadcasting read data on the Read Channel 322.
[0041] FIG. 4 is a timing diagram showing six address pipelined read operations over a multiple address two channel bus. The four read operations described earlier in connection with FIG. 3 are repeated in FIG. 4, and therefore, do not warrant further discussion here.
[0042] Two additional read operations may be initiated by the sending component in the fourth clock cycle 307 by broadcasting an address location associated with a fifth read operation R5 as Address A and an address location associated with a sixth read operation R6 as Address B over the Transmit Channel 318, setting read/write signal indicators R/W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals.
[0043] During the same clock cycle, the receiving component may deassert the Transfer Ack 316 signal indicating that it cannot currently accept the broadcast because, by way of example, it's address queue is full. The sending component may detect that the Transfer Ack 316 signal is not asserted at the end of the fourth clock cycle 307. In response, the sending component may continue to broadcast the address locations for the fifth and sixth read operations R5 and R on the Transmit Channel 318, along with the appropriate settings for the read/write signal indicators R/W A 306 and R/W B 312, the ANalidA 304 and ANalidB 310 signals, and the SizeA 308 and SizeB 314 signals, until the sending component detects the assertion of the Transfer Ack 316 signal from the receiving component. In this case, the broadcast is repeated in the fifth, sixth and seventh clock cycles 309, 311 and 313. During the seventh cycle 313, the receiving component may be able to receive a broadcast on the Transmit Channel 318 and perform the requested operation, as indicated by the assertion of the Transfer Ack 316 signal. In response to the assertion of the Transfer Ack 316 signal, the sending component determines that it does not need to send a repeat broadcast during the eighth clock cycle 315, and deasserts the ANalidA 304 and ANalidB 310 signals.
[0044] Alternatively, the sending component may queue the broadcast for the address locations associated with the fifth and sixth read operations when it detects that the Transfer Ack 316 signal is not asserted at the end of the fourth clock cycle 307. The broadcast may be queued until the receiving component indicates that it is ready to accept a broadcast over the Transmit Channel 318 by reasserting the Transfer Ack 316 signal. In this case, the sending component may monitor the Transfer Ack 316 signal until it is asserted by the receiving component in the seventh clock cycle 313. When the sending component detects that the Transfer Ack 316 is asserted, it may rebroadcast the queued address locations over the Transmit Channel 318 in the eighth clock cycle 315, along with the appropriate settings for the read/write signal indicators R/W A 306 and R/W B 312, the ANalidA 304 and ANalidB 310 signals, and the SizeA 308 and SizeB 314 signals. During the fifth, sixth and seventh clock cycles 309, 311, and 313, the sending component may broadcast new address locations on the Transmit Channel 318, or broadcast any outstanding write data to the receiving component.
[0045] Returning to FIG. 4, the receiving component may be able to receive a broadcast on the Transmit Channel 318 and perform the requested operation in the seventh clock cycle 313. More specifically, the receiving component may sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving the read data at the new address locations. The first 8-bytes of the read data R5(l) associated with the fifth read operation R5 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the fourteenth clock cycle 327, and the second 8-bytes of read data R5(2) associated with the fifth read operation R5 may be retrieved from the receiving component and broadcast on the Read Channel 322 during the fifteenth clock cycle 329. Similarly, the first 8-bytes of the read data R6(l) associated with the sixth read operation R may be retrieved from the receiving component and broadcast on the Read Channel 322 during the sixteenth clock cycle 331, and the second 8-bytes of read data Rδ(2) associated with the sixth read operation Re may be retrieved from the receiving component and broadcast on the Read Channel 322 during the seventeenth clock cycle 333
[0046] FIG. 5 is a timing diagram showing read and write operations over a multiple address two channel bus. Two read operations may be initiated by the sending component during the second clock cycle 303. This may be achieved by broadcasting an address location associated with a first read operation R1 as Address A and an address location associated with a second read operation R2 as Address B over the Transmit Channel 318, setting read/write signal indicators R W A 306 and R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals. In this case, the size of the payload for the read operation at both address locations is 16-bytes.
[0047] The receiving component may detect the assertion of the ANalidA 304 and ANalidB 310 signals, sample the address information from the Transmit Channel 318, and sample the read/write signal indicators R/W A 306 and R/W B 312. Based on this information, and the size of the payload indicated by the SizeA 308 and SizeB 314 signals, the receiving component may begin retrieving read data at the appropriate address locations. The receiving component may also assert the Transfer Ack 316 signal indicating that it has successfully received the broadcast.
[0048] The sending component may detect the assertion of the Transfer Ack 316 signal at the end of the second clock cycle 303. Responsive to the assertion of the Transfer Ack 316 signal, the sending component may deassert the ANalidA 304 and ANalidB signals 310. By deasserting the ANalidA 304 and the ANalidB 310 signals, the sending component is indicating to the receiving component that it will either broadcast write data on the Transmit Channel 318, or nothing at all on the Transmit Channel 318. In this case, nothing will be broadcast on the Transmit Channel 318 because a write operation request has not been made.
[0049] In the fifth clock cycle 503, the sending component may initiate a write operation by broadcasting an address location associated with a first write operation W\ as Address A over the Transmit Channel 318, setting the read/write signal indicator R/W A 306 to "0" to indicate a write operation, asserting the ANalidA 304 signal to alert the receiving component of an address location broadcast, and indicating to the receiving component the size of the payload using the SizeA 308 signal. In this case, the size of the payload for the write operation is 32-bytes as indicated in FIG. 5 by four data beats.
[0050] In response to this broadcast, the receiving component may assert the Transfer Ack 316 signal during the fifth clock cycle 309 indicating that it has successfully received the broadcast. The receiving component may also assert the Write Ack 320 signal during the sixth clock cycle 311 indicating that it is ready to write data to the address location associated with the first write operation Wi.
[0051] In the sixth clock cycle 311, the sending component may deassert the ANalidA signal 304. As explained earlier, by deasserting the ANalidA 304 signal, the sending component is indicating to the receiving component that it will either broadcast write data on the Transmit Channel 318, or nothing at all on the Transmit Channel 318. In this case, the receiving component will be looking for the first 8-bytes of the write data associated with the first write operation Wi. Although a second write operation may be requested at any time by asserting the ANalidA and/or ANalidB signals 304 and 310, the sending component will not send write data for the second write operation until the broadcast of the write data for the first write operation is complete. This approach tends to reduce sideband signaling requirements that might otherwise be required to indicate which write operation the payload is associated with.
[0052] With the ANalidA signal 304 deasserted, the sending component may broadcast on the Transmit Channel 318 the first 8-bytes of the write data Wi(l) associated with the first write operation Wi. The receiving component may write the data to the appropriate block of 8 address locations.
[0053] Concurrently, the first 8-bytes of the read data R\(l) associated with the first read operation R\ may be retrieved from the receiving component and broadcast on the Read Channel 322. The receiving component may also assert the Read Ack 324 signal indicating that it is sending read data on the Read Channel 322.
[0054] With the Write Ack 320 signal still asserted in the seventh clock cycle 313, the sending component may broadcast on the Transmit Channel 318 the second 8-bytes of the write data Wi(2) associated with the first write operation W\. The receiving component may write the data to the appropriate block of 8 address locations.
[0055] Concurrently, the second 8-bytes of the read data Rt(2) associated with the first read operation Rt may be retrieved from the receiving component and broadcast on the Read Channel 322. The receiving component may also assert the Read Ack 324 signal.
[0056] In the eighth clock cycle 315, the sending component may temporarily suspend broadcasting write data to initiate a new write operation followed by a new read operation. This may be achieved by broadcasting an address location W2 associated with a second write operation as Address A and an address location associated with a third read operation R3 as Address B over the Transmit Channel 318, setting the read/write indicator signal R/W A 306 to "0," setting the read/write indicator signal R/W B 312 to "1," asserting the ANalidA 304 and ANalidB 310 signals, and indicating to the receiving component the size of the payload using the SizeA 308 and SizeB 314 signals. In this case, the payload size for both the write and read operations is 16-bytes.
[0057] During the same eighth clock cycle 315, the first 8-bytes of the read data R2(l) associated with the second read operation R2 may be retrieved by the receiving component and broadcast on the Read Channel 322. The receiving component may also assert the Read Ack 324 signal.
[0058] In the ninth clock cycle 317, the sending component may deassert the ANalidA 304 and the ANalidB 310 signals indicating to the receiving component that the sending component will resume broadcasting write data on the Transmit Channel 318. With the Write Ack 320 signal still asserted, the sending component may broadcast on the Transmit Channel 318 the third 8-bytes of the write data W^3) associated with the first write operation Wi. The receiving component may write the data to the appropriate block of 8 address locations.
[0059] Concurrently, the second 8-bytes of the read data R2(2) associated with the second read operation R2 may be retrieved from the receiving component and the broadcast on the Read Channel 322. With this broadcast, the receiving component has completed both read operations initiated by the sending component during the second clock cycle 303, and therefore, may deassert the Read Ack 324 signal. Due to the read latency of the receiving component, it may not ready to broadcast the read data associated with the third read operation R3.
[0060] With the Write Ack 320 signal still asserted through the twelfth clock cycle 323, the sending component may broadcast on the Transmit Channel 318 the final 8- bytes of the write data Wi(4) associated with the first write operation W\ in the tenth clock cycle 319. The sending component may also broadcast the first 8-bytes of the write data W2(l) associated with the second write operation W2 in the eleventh clock cycle 321 and the last 8-bytes of the write data W2(2) associated with the second write operation W2 in the twelfth clock cycle 323. The receiving component may write this data to the appropriate block of 16 address locations. With this broadcast, the outstanding write operations are complete, and therefore, the receiving component may deassert the Write Ack 320 signal in the following clock cycle 325.
[0061] hi the twelfth clock cycle 323, the first 8-bytes of the read data R3(l) associated with the third read operation R3 may be retrieved from the receiving component and broadcast on the Read Channel 322. In the following clock cycle 325, the second 8-bytes of read data R3(2) associated with the third read operation R3 may be retrieved from the receiving component and broadcast on the Read Channel 322. At the completion of the final broadcast of read data, the receiving component may deassert the Read Ack 324 signal in the fourteenth clock cycle 327.
[0062] The ability of the processing system to broadcast address information in the middle of a write operation that extends over multiple clock cycles may depend on the buffering capabilities of the sending and receiving components, hi at least one embodiment of the processing system, the sending component may be implemented with a programmable means for enabling or disabling this feature based on potential performance advantages or supported buffering capabilities.
[0063] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
[0064] The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in the sending and/or receiving component, or elsewhere. In the alternative, the processor and the storage medium may reside as discrete components in the sending and/or receiving component, or elsewhere. [0065] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of communicating between a sending component and a receiving component over a bus, the bus comprising first and second channels, the method comprising: broadcasting from the sending component on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data, and wherein the sending component broadcasts the read and write address information multiple address locations at a time; storing the write data broadcast on the first channel at the receiving component based on the write address information; retrieving read data from the receiving component based on the read address information; and broadcasting from the receiving component the retrieved read data on the second channel.
2. The method of claim 1 further comprising signaling from the sending component to the receiving component to indicate the sequence in which the receiving component will store the write data, retrieve the read data, or store the write data and retrieve the read data for each of the multiple address location broadcasts.
3. The method of claim 1 wherein the sequence in which the receiving component stores the write data, retrieves the read data, or stores the write data and retrieves the read data for each of the multiple address location broadcasts is based on the manner in which the multiple address locations are broadcast.
4. The method of claim 1 wherein the first channel comprises a plurality of lines with each of the address locations for each of the multiple address location broadcasts occupying a portion of the lines, and wherein the sequence in which the receiving component stores the write data, retrieves the read data, or stores the write data and retrieves the read data for each of the multiple address location broadcasts is based on the manner in which the multiple address locations are apportioned among the lines.
5. The method of claim 1 wherein each of the multiple address location broadcasts comprises two of the read address locations, two of the write address locations, or one of the read address locations and one of the write address locations.
6. The method of claim 1 wherein the first channel comprises a plurality of lines with a first portion of the lines allocated for one of the multiple address locations and a second portion of the lines allocated for the other multiple address location for each of the multiple address location broadcasts, and wherein the receiving component performs the operation associated with the address location allocated to the first portion of the lines before performing the operation associated with the address location allocated to the second portion of lines.
7. The method of claim 1 wherein at least a portion of the write data is broadcast on the first channel concurrently with the broadcast of at a least a portion of the retrieved read data on the second channel.
8. The method of claim 1 wherein at least a portion of the read or write address information is broadcast on the first channel concurrently with the broadcast of at least a portion of the retrieved read data on the second channel.
9. The method of claim 1 wherein the sending component broadcasts the read address information, the write address information and the write data on the first channel in a time division multiplexed fashion.
10. The method of claim 9 wherein the write data comprises a plurality of payloads, and wherein the receiving component stores each of the payloads based on one of the write address locations.
11. The method of claim 10 wherein the sending component performs one of the multiple address location broadcasts between first and second portions of one of the payloads.
12. The method of claim 11 wherein the multiple address broadcast between the first and second portions of said one of the payloads comprises two of the read address locations, two of the write address locations, or one of the read address locations and one of the write address locations.
13. The method of claim 1 further comprising signaling from the receiving component to the sending component to acknowledge each of the address locations for each of the multiple address location broadcasts.
14. The method of claim 13 further comprising repeat broadcasting one of the address locations for one of the multiple address location broadcasts in response to the receiving component failing to acknowledge said one of the address locations.
15. The method of claim 1 further comprising signaling from the sending component to the receiving component to indicate when each of the multiple address location broadcasts is occurring on the first channel.
16. A processing system, comprising: a bus having first and second channels; and a sending component configured to broadcast on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data, the sending component being further configured to broadcast the read and write address information multiple address locations at a time; and a receiving component configured to store the write data broadcast on the first channel based on the write address information, retrieve read data based on the read address information, and broadcast the retrieved read data on the second channel to the sending component.
17. The processing system of claim 16 wherein the receiving component is further configured to store the write data, retrieve the read data, or store the write data and retrieve the read data for each of the multiple address location broadcasts in a sequence based on signaling from the sending component.
18. The processing system of claim 16 wherein the receiving component is further configured to store the write data, retrieve the read data, or store the write data and retrieve the read data for each of the multiple address location broadcasts in a sequence based on the manner in which the multiple address locations are broadcast.
19. The processing system of claim 16 wherein the first channel comprises a plurality of lines with each of the address locations for each of the multiple address location broadcasts occupying a portion of the lines, and wherein the receiving component is further configured to store the write data, retrieve the read data, or store the write data and retrieve the read data for each of the multiple address location broadcasts in a sequence based on the manner in which the multiple address locations are apportioned among the lines.
20. The processing system of claim 16 wherein each of the multiple address location broadcasts comprises two of the read address locations, two of the write address locations, or one of the read address locations and one of the write address locations.
21. The processing system of claim 20 wherein the first channel comprises a plurality of lines with a first portion of the lines allocated to one of the multiple address locations and a second portion of the lines allocated to the other multiple address location for each of the multiple address location broadcasts, and wherein the receiving component is further configured to perform the operation associated with the address location allocated to the first portion of the lines before performing the operation associated with the address location allocated to the second portion of lines.
22. The processing system of claim 16 wherein the sending component is further configured to broadcast at least a portion of the write data on the first channel at the same time the receiving component broadcasts at least a portion of the retrieved read data on the second channel.
23. The processing system of claim 16 wherein the sending component is further configured to broadcast at least a portion of the read or write address information on the first channel at the same time the receiving component broadcasts at least a portion of the retrieved read data on the second channel.
24. The processing system of claim 16 wherein the sending component is further configured to broadcast the read address information, the write address information and the write data on the first channel in a time division multiplexed fashion.
25. The processing system of claim 24 wherein the write data comprises a plurality of payloads, and wherein the receiving component is further configured to store each of the payloads based on one of the write address locations.
26. The processing system of claim 25 wherein the sending component is further configured to perform one of the multiple address location broadcasts between first and second portions of one of the payloads.
27. The processing system of claim 26 wherein the sending component is further configured to perform said one of the multiple address location broadcasts between the first and second portions of said one of the payloads by concurrently broadcasting two of the read address locations, two of the write address locations, or one of the read address locations and one of the write address locations.
28. The processing system of claim 16 wherein the receiving component is further configured to signal the receiving component to acknowledge each of the address location for each of the multiple address location broadcasts.
29. The processing system of claim 28 wherein the sending component is configured further comprising repeat broadcasting one of the address locations for one of the multiple address location broadcasts if the receiving component does not acknowledge said one of the address locations.
30. The processing system of claim 16 wherein the sending component is further configured to signal the receiving component to indicate when each of the multiple address location broadcasts is occurring on the first channel.
31. A processing system, comprising: a bus having first and second channels; means for broadcasting on the first channel read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data, the read and write address information being broadcast multiple address locations at a time; and means for storing the write data broadcast on the first channel based on the write address information, retrieving read data based on the read address information, and broadcasting the retrieved read data on the second channel.
PCT/US2005/001590 2004-01-22 2005-01-20 A multiple address two channel bus structure WO2005071557A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
BRPI0507033-3A BRPI0507033A (en) 2004-01-22 2005-01-20 a two-channel multi-address bus structure
JP2006551212A JP2007519121A (en) 2004-01-22 2005-01-20 Multiple address 2-channel bus structure
DE602005010048T DE602005010048D1 (en) 2004-01-22 2005-01-20 MORE ADDRESS TWO CHANNEL BUS STRUCTURE
EP05711605A EP1709543B1 (en) 2004-01-22 2005-01-20 A multiple address two channel bus structure
CN2005800074451A CN1930563B (en) 2004-01-22 2005-01-20 A multiple address two channel bus structure
IL177023A IL177023A (en) 2004-01-22 2006-07-23 Multiple address two channel bus structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US53850504P 2004-01-22 2004-01-22
US60/538,505 2004-01-22
US10/833,716 US20050182884A1 (en) 2004-01-22 2004-04-27 Multiple address two channel bus structure
US10/833,716 2004-04-27

Publications (2)

Publication Number Publication Date
WO2005071557A2 true WO2005071557A2 (en) 2005-08-04
WO2005071557A3 WO2005071557A3 (en) 2005-11-17

Family

ID=34811353

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/001590 WO2005071557A2 (en) 2004-01-22 2005-01-20 A multiple address two channel bus structure

Country Status (12)

Country Link
US (1) US20050182884A1 (en)
EP (1) EP1709543B1 (en)
JP (1) JP2007519121A (en)
KR (1) KR100881049B1 (en)
CN (1) CN1930563B (en)
AT (1) ATE409913T1 (en)
BR (1) BRPI0507033A (en)
DE (1) DE602005010048D1 (en)
ES (1) ES2313297T3 (en)
IL (1) IL177023A (en)
TW (1) TW200535624A (en)
WO (1) WO2005071557A2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010112445A1 (en) 2009-03-31 2010-10-07 Societe De Technologie Michelin Method and device for producing a three-layer cord
WO2010112444A1 (en) 2009-03-31 2010-10-07 Societe De Technologie Michelin Method and device for producing a three-layer cord
WO2011144472A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Multi-layered metal cord rubberised in situ by an unsaturated thermoplastic elastomer
WO2011144471A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Method for the production of a three-layer metal cord of the type that is rubberised in situ
WO2011144473A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Method for the production of a multi-layer metal cord that is rubberised in situ using an unsaturated thermoplastic elastomer
WO2011144469A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Triple-layered metal cord rubberised in situ by an unsaturated thermoplastic elastomer

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7209998B2 (en) * 2004-02-04 2007-04-24 Qualcomm Incorporated Scalable bus structure
US7975079B2 (en) * 2005-02-07 2011-07-05 Broadcom Corporation Computer chip set having on board wireless interfaces to support parallel communication
US7617343B2 (en) * 2005-03-02 2009-11-10 Qualcomm Incorporated Scalable bus structure
FR2901082B1 (en) * 2006-05-09 2008-08-08 Viaccess Sa METHODS FOR BROADCAST MULTIMEDIA PROGRAM DELIVERY AND RECEPTION, TERMINAL AND NETWORK HEAD FOR SUCH METHODS
US7958281B2 (en) * 2006-06-20 2011-06-07 Freescale Semiconductor, Inc. Method and apparatus for transmitting data in a flexray node
US8463589B2 (en) 2006-07-28 2013-06-11 Synopsys, Inc. Modifying a virtual processor model for hardware/software simulation
US8644305B2 (en) * 2007-01-22 2014-02-04 Synopsys Inc. Method and system for modeling a bus for a system design incorporating one or more programmable processors
US8325633B2 (en) * 2007-04-26 2012-12-04 International Business Machines Corporation Remote direct memory access
US20090089515A1 (en) * 2007-10-02 2009-04-02 Qualcomm Incorporated Memory Controller for Performing Memory Block Initialization and Copy
US8599886B2 (en) 2010-08-26 2013-12-03 Qualcomm Incorporated Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus
CN103929415B (en) * 2014-03-21 2018-03-06 华为技术有限公司 The method, apparatus and network system of reading and writing data under RDMA
DE102017204186A1 (en) * 2017-03-14 2018-09-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Efficient multi-user addressing
US11422707B2 (en) * 2017-12-21 2022-08-23 Advanced Micro Devices, Inc. Scheduling memory requests for a ganged memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725836A (en) * 1986-01-27 1988-02-16 Snap Systems, Inc. Series port connection of a plurality of terminals to a master processor
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
GB2341766A (en) * 1998-09-18 2000-03-22 Pixelfusion Ltd Bus architecture

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4162536A (en) * 1976-01-02 1979-07-24 Gould Inc., Modicon Div. Digital input/output system and method
US4468737A (en) * 1982-06-09 1984-08-28 Gte Automatic Electric Inc. Circuit for extending a multiplexed address and data bus to distant peripheral devices
JPS61269750A (en) * 1985-05-24 1986-11-29 Fujitsu Ltd Storage device control system
US5539389A (en) * 1991-11-15 1996-07-23 Pittway Corporation Enhanced group addressing system
US5793990A (en) * 1993-06-11 1998-08-11 Vlsi Technology, Inc. Multiplex address/data bus with multiplex system controller and method therefor
GB2285524B (en) * 1994-01-11 1998-02-04 Advanced Risc Mach Ltd Data memory and processor bus
US5761714A (en) * 1996-04-26 1998-06-02 International Business Machines Corporation Single-cycle multi-accessible interleaved cache
US6208655B1 (en) * 1996-11-27 2001-03-27 Sony Europa, B.V., Method and apparatus for serving data
US6195674B1 (en) * 1997-04-30 2001-02-27 Canon Kabushiki Kaisha Fast DCT apparatus
GB2352065B (en) * 1999-07-14 2004-03-03 Element 14 Ltd A memory access system
US6704820B1 (en) * 2000-02-18 2004-03-09 Hewlett-Packard Development Company, L.P. Unified cache port consolidation
US6708239B1 (en) * 2000-12-08 2004-03-16 The Boeing Company Network device interface for digitally interfacing data channels to a controller via a network
JP2002215606A (en) * 2001-01-24 2002-08-02 Mitsubishi Electric Corp Data processor
US6931468B2 (en) * 2002-02-06 2005-08-16 Hewlett-Packard Development Company, L.P. Method and apparatus for addressing multiple devices simultaneously over a data bus
US6982892B2 (en) * 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725836A (en) * 1986-01-27 1988-02-16 Snap Systems, Inc. Series port connection of a plurality of terminals to a master processor
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
GB2341766A (en) * 1998-09-18 2000-03-22 Pixelfusion Ltd Bus architecture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010112445A1 (en) 2009-03-31 2010-10-07 Societe De Technologie Michelin Method and device for producing a three-layer cord
WO2010112444A1 (en) 2009-03-31 2010-10-07 Societe De Technologie Michelin Method and device for producing a three-layer cord
WO2011144472A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Multi-layered metal cord rubberised in situ by an unsaturated thermoplastic elastomer
WO2011144471A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Method for the production of a three-layer metal cord of the type that is rubberised in situ
WO2011144473A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Method for the production of a multi-layer metal cord that is rubberised in situ using an unsaturated thermoplastic elastomer
WO2011144469A1 (en) 2010-05-20 2011-11-24 Societe De Technologie Michelin Triple-layered metal cord rubberised in situ by an unsaturated thermoplastic elastomer

Also Published As

Publication number Publication date
BRPI0507033A (en) 2007-06-05
JP2007519121A (en) 2007-07-12
CN1930563B (en) 2011-04-20
EP1709543A2 (en) 2006-10-11
ATE409913T1 (en) 2008-10-15
US20050182884A1 (en) 2005-08-18
TW200535624A (en) 2005-11-01
CN1930563A (en) 2007-03-14
KR20060122934A (en) 2006-11-30
KR100881049B1 (en) 2009-02-05
IL177023A0 (en) 2006-12-10
EP1709543B1 (en) 2008-10-01
WO2005071557A3 (en) 2005-11-17
DE602005010048D1 (en) 2008-11-13
ES2313297T3 (en) 2009-03-01
IL177023A (en) 2010-12-30

Similar Documents

Publication Publication Date Title
EP1709543B1 (en) A multiple address two channel bus structure
US7739425B2 (en) Two channel computer bus architecture
US7913021B2 (en) Scalable bus structure
KR20120040535A (en) Bus system and operating method thereof
US8521914B2 (en) Auxiliary writes over address channel
KR100874073B1 (en) Method and apparatus for allocating bandwidth on a transmit channel of a bus
EP1856619B1 (en) Scalable bus structure
MXPA06008326A (en) A two channel bus structure to support address information, data, and transfer qualifiers

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPEN Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 177023

Country of ref document: IL

WWE Wipo information: entry into national phase

Ref document number: 2005711605

Country of ref document: EP

Ref document number: 2006551212

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 953/MUMNP/2006

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 1020067016881

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 200580007445.1

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2005711605

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020067016881

Country of ref document: KR

ENP Entry into the national phase

Ref document number: PI0507033

Country of ref document: BR