WO2005062349A1 - Containing capacitors and method of forming - Google Patents
Containing capacitors and method of forming Download PDFInfo
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- WO2005062349A1 WO2005062349A1 PCT/US2004/040252 US2004040252W WO2005062349A1 WO 2005062349 A1 WO2005062349 A1 WO 2005062349A1 US 2004040252 W US2004040252 W US 2004040252W WO 2005062349 A1 WO2005062349 A1 WO 2005062349A1
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- Prior art keywords
- silicon nitride
- silicon
- over
- construction
- region
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 270
- 238000010276 construction Methods 0.000 claims abstract description 97
- 239000003989 dielectric material Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 90
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 47
- 239000004020 conductor Substances 0.000 claims description 38
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 13
- 239000007772 electrode material Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 239000005388 borosilicate glass Substances 0.000 claims description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 87
- 230000002093 peripheral effect Effects 0.000 description 29
- 239000012634 fragment Substances 0.000 description 19
- 230000000873 masking effect Effects 0.000 description 11
- 239000000203 mixture Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000007847 structural defect Effects 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Definitions
- the invention pertains to semiconductor constructions, and to methods of forming capacitor devices.
- Capacitor constructions continue to have increasing aspect ratios in higher generation integrated circuitry fabrication. For example, dynamic random access memory (DRAM) capacitors now have elevations of from 2 to 3 microns, with widths of about 0.1 micron. Further, it is a continuing goal to increase the density of semiconductor devices, with a corresponding goal to reduce the footprint associated with individual devices. As the packing density of capacitor devices becomes increasingly greater, the available surface area for capacitance decreases.
- a common capacitor construction is a so-called container device. One of the electrodes of such device is shaped as a container, and subsequently dielectric material and another capacitor electrode are formed within the container.
- Another type of capacitor structure is a so-called pedestal (or post) device.
- One of the electrodes of the device is shaped as a pedestal, and subsequently dielectric material and another capacitor electrode are formed over and around the pedestal.
- the invention includes a method of forming a plurality of capacitor devices. Conductive storage node material is formed within openings in a mass.
- a retaining structure (which can be a lattice structure) is provided in physical contact with at least some of the conductive storage node material, and subsequently at least some of the mass is removed while utilizing the retaining structure to prevent collapse of the conductive storage node material. After removal of at least some of the mass, the conductive storage node material is incorporated into the plurality of capacitor devices.
- the conductive storage node material can be in the form of a plurality of container shapes in some aspects of the invention, and in the form of a plurality of pedestals (or posts) in other aspects of the invention.
- the invention encompasses methods of forming capacitor devices in which a construction comprising a first material is formed over a substrate, and a retaining structure is formed over at least a portion of the first material. Openings are formed to extend into the first material, and a first conductive layer is formed within the openings. The first conductive layer within the openings forms container structures having outer sidewalls along the first material. At least some of the first material is removed to expose at least portions of the outer sidewalls of the container structures while utilizing the retaining structure to support the container structures and avoid collapse of the container structures. A capacitor dielectric material is formed along the exposed portions of the outer sidewalls and within the container structures. A second conductive layer is formed over the capacitor dielectric material.
- the invention encompasses a method of forming capacitor devices utilizing a construction comprising a memory array region, a region other than the memory array region, and a location between the memory array region and said other region.
- the other region can be, for example, a peripheral region where logic circuitry is ultimately to be formed.
- a first material is formed to extend over the memory array region, the other region, and the location between the memory array region and said other region.
- a second material is formed over at least a portion of the first material that is over the memory array region, and over an entirety of the first material that is over said other region.
- Openings are formed to extend into the first material, and a trench is formed within the first material over the location between the memory array region and said other region.
- a first conductive layer is formed within the openings and within the trench.
- the first conductive layer within the openings forms container structures having outer sidewalls along the first material.
- After forming the first conductive layer and the second material at least some of the first material is removed to expose at least portions of the outer sidewalls of the container structures.
- a capacitor dielectric material is formed along the exposed portions of the outer sidewalls and within the container structures, and a second conductive layer is formed over the capacitor dielectric material.
- the first conductive layer, second conductive layer and dielectric material are together incorporated into capacitor devices.
- the invention includes semiconductor constructions.
- An exemplary semiconductor construction comprises a substrate having a memory array region defined therein together with a region other than the memory array region and a location between the memory array region and said other region.
- a plurality of container structures are across the memory array region.
- the container structures are electrically conductive.
- the container structures comprise inner sidewalls within the container structures and outer sidewalls in opposing relation to the inner sidewalls.
- An electrically insulative material is over said other region.
- the electrically insulative material has a lateral sidewalk
- An electrically conductive liner is along the sidewall of the material.
- a capacitor dielectric material is along the inner and outer sidewalls of the container structures.
- a second conductive layer is over the capacitor dielectric material.
- Fig. 1 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment at a preliminary processing stage of an exemplary aspect of the present invention.
- Fig. 2 is a fragmentary top view of a semiconductor wafer fragment comprising the cross-section of Fig. 1 along the line 1 -1.
- Fig. 3 is a diagrammatic, cross-sectional view of the Fig. 1 wafer fragment shown at a processing step subsequent to that of Fig. 1.
- Fig. 4 is a fragmentary top view of a semiconductor construction comprising the fragment of Fig.
- Fig. 5 is a diagrammatic, cross-sectional view of the semiconductor wafer fragment of Fig. 1 at a processing stage subsequent to that of Fig. 3.
- Fig. 6 is a diagrammatic top view of a semiconductor construction comprising the fragment of Fig. 5 along the line 5-5.
- Fig. 7 is a view of the cross-section of Fig. 1 shown at a processing stage subsequent to that of Fig. 5.
- Fig. 8 is a diagrammatic top view of a semiconductor wafer fragment comprising the cross-section of Fig. 7 along the line 7-7.
- Fig. 9 is a diagrammatic, cross-sectional view along the line 9-9 of the Fig.
- Fig. 10 is a view of the cross-section of Fig. 1 shown at a processing stage subsequent to that of Fig. 7.
- Fig. 11 is a diagrammatic top view of a semiconductor construction comprising the cross-section of Fig. 10 along the line 10-10.
- Fig. 12 is a diagrammatic cross-section along the line 12-12 of Fig. 11.
- Fig. 13 is a view along the line 12-12 of Fig. 11 , and shows a processing stage alternative to that of Fig. 12.
- Fig. 14 is a view of the cross-section of Fig.
- Fig. 15 is a diagrammatic top view of a fragment of a semiconductor construction comprising the cross-section of Fig. 14 along the line 14-14.
- Fig. 16 is a diagrammatic, cross-sectional view along the line 16-16 of Fig. 15.
- Fig. 17 is a view of the Fig. 1 cross-section shown at a processing stage subsequent to that of Fig. 14.
- Fig. 18 is a diagrammatic top view of a semiconductor wafer fragment comprising the cross-section of Fig. 17 along the line 17-17.
- Fig. 19 is a diagrammatic, cross-sectional view along the line 19-19 of Fig. 18.
- Fig. 20 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment at an exemplary processing stage of an aspect of the present invention alternative to that of Fig. 1.
- Fig. 21 is a view of the Fig. 20 cross-section shown at a processing stage subsequent to that of Fig. 20.
- Fig. 22 is a view of the Fig. 20 cross-section shown at a processing stage subsequent to that of Fig. 21.
- Fig. 23 is a diagrammatic, top view of a semiconductor wafer fragment shown at a preliminary processing stage in accordance with a third aspect of the present invention.
- Fig. 24 is a view along the cross-section 24-24 of Fig. 23.
- Fig. 25 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment shown at a preliminary processing stage of a fourth aspect of the present invention.
- Fig. 26 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment shown at a preliminary processing stage in accordance with a fifth aspect of the present invention.
- Fig. 27 is a view of the Fig. 26 cross-section shown at a processing stage subsequent to that of Fig. 26, with the processing stage of Fig. 27 being analogous to the stage shown in Fig. 10.
- Fig. 28 is a diagrammatic, cross-sectional view of the portion illustrated as 28 in Fig.
- Fig. 29 is a diagrammatic top view of a fragment of a semiconductor construction illustrating an exemplary liner formed in accordance with an aspect of the present invention.
- Fig. 30 is a diagrammatic top view of a fragment of a semiconductor construction illustrating another exemplary liner formed in accordance with an aspect of the present invention.
- One aspect of the invention includes methodology for forming capacitor constructions in which a retaining structure, or lattice, is utilized to hold capacitor electrode structures (such as containers or pedestals) as outer sidewalls of the capacitor electrode structures are exposed with an etch.
- the retaining structure can thus alleviate, and preferably prevent, toppling and other structural defects occurring to the capacitor electrode structures as the outer surfaces of the structures are exposed.
- the capacitor electrode structures can be storage node structures.
- a particular aspect of the invention includes methodology for forming container capacitor constructions in which a retaining structure, or lattice, is utilized to hold conductive containers as outer sidewalls of the containers are exposed with an etch.
- the retaining structure can thus alleviate, and preferably prevent, toppling and other structural defects occurring to the containers as the outer surfaces of the containers are exposed.
- the lattice utilized to retain the containers is rigid enough to provide support for the containers, but also has holes, or grooves, patterned into it to allow wet or gaseous removal of material from adjacent the containers, which ultimately exposes outer surfaces of the containers.
- the removal of material from adjacent the containers can be accomplished using an isotropic etch.
- a semiconductor wafer will have one region corresponding to a memory array, and another region peripheral to the memory array in which logic or other circuitry is to be formed.
- Methodology of the present invention can form the retaining lattice over the memory array, while utilizing the same material as that utilized in the lattice to form a protective layer over the peripheral region to protect the peripheral region from the etch utilized to expose outer surfaces of capacitor electrode structures in the memory array.
- the invention can also encompass formation of a trench in a location between the memory array region and the peripheral region, and provision of a protective material within the trench which protects a lateral periphery of, the peripheral region from attack by etchants utilized to remove material from the memory array region during exposure of outer surfaces of the capacitor electrode structures.
- a semiconductor wafer fragment 10 is shown at a preliminary processing stage of an exemplary aspect of the present invention.
- Fragment 10 comprises a substrate 12.
- Substrate 12 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with background p-type dopant.
- substrate 12 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with background p-type dopant.
- the terms "semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- Substrate 12 refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
- Substrate 12 is divided into three defined regions 14, 16 and 18.
- Region 14 corresponds to a memory array region.
- Region 18 corresponds to a region other than the memory array region, and can correspond to, for example, a so-called peripheral region.
- the region is referred to as a peripheral region because it is peripheral to the memory array region.
- logic circuitry and other circuitry associated with the control of data flow to and from memory devices associated with memory array region 14 would be associated with peripheral region 18.
- Region 16 corresponds to a location between the memory array region 14 and the peripheral circuitry associated with region 18.
- a plurality of electrically conductive node locations 20, 22, 24 and 26 are shown within memory array region 14 of substrate 12. Node locations 20, 22, 24 and 26 can correspond to, for example, conductively-doped diffusion regions within a semiconductive material of substrate 12, and/or to conductive pedestals associated with substrate 12. Although the node locations are shown to be electrically conductive at the processing stage of Fig. 1 , it is to be understood that the electrically conductive materials of the node locations could be provided at a processing stage subsequent to that of Fig. 1 in various other aspects of the invention (not shown).
- Node locations 20, 22, 24 and 26 can ultimately be electrically connected with transistor constructions (not shown in Fig. 1) and can correspond to source/drain regions of the transistor constructions, or can be ohmically connected to source/drain regions of the transistor constructions.
- Transistor gates and other components of the transistor constructions can be present within memory array region 14 at the processing stage of Fig. 1 , or can be formed in subsequent processing.
- a mass 28 is formed over substrate 12.
- Mass 28 can comprise a single homogeneous layer (as shown), or can comprise multiple layers of differing composition and/or physical properties. Mass 28 can comprise, consist essentially of, or consist of one or more electrically insulative materials.
- mass 28 will comprise, consist essentially of, or consist of one or more of borophosphosilicate glass (BPSG), spin-on-glass (SOG), silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), undoped glass, and silicon nitride.
- mass 28 will comprise, consist essentially of, or consist of silicon and oxygen.
- Mass 28 can have a thickness over substrate 12 of, for example, from about 5,OO ⁇ A to about 50,OO ⁇ A, and typically will have a thickness of about 20,OO ⁇ A.
- a retaining structure (also referred to as a lattice structure) 30 is formed over mass 28.
- Retaining structure 30 can comprise a single homogeneous composition, or can comprise two or more layers of differing composition. In subsequent processing (described below) at least some of mass 28 is selectively etched relative to at least some of retaining material 30. Accordingly, retaining material 30 preferably comprises a composition to which at least some of mass 28 can be selectively etched. In particular aspects, mass 28 can be considered to comprise a first material, and structure 30 can be considered to comprise a second material to which the first material is ultimately selectively etched. In some aspects, retaining structure 30 will comprise, consist essentially of, or consist of silicon and nitrogen.
- mass 28 will comprise, consist essentially of, or consist of borophosphosilicate glass and retaining structure 30 will comprise, consist essentially of, or consist of silicon nitride.
- mass 28 will comprise, consist essentially of, or consist of doped or undoped silicon-containing glass and composition 30 will comprise one or more layers consisting essentially of, or consisting of silicon nitride; together with one or more layers consisting essentially of, or consisting of silicon.
- the layers consisting essentially of silicon, or consisting of silicon can comprise amorphous silicon and/or polycrystalline silicon.
- retaining structure 30 consists essentially of, or consists of silicon nitride
- the structure can have a thickness of from about 5 ⁇ to about 3,OO ⁇ A, and typically will have a thickness of about 700A.
- structure 30 comprises a stack of layers of silicon nitride and silicon; the layers of silicon nitride can have a thickness of from about 5 ⁇ A to about 3,OO ⁇ A, with a typical thickness being about 30 ⁇ A; and the layers of silicon can have a thickness of from about 5 ⁇ A to about 1 ,OO ⁇ A, with a typical thickness being about 20 ⁇ A.
- structure 30 can comprise a layer consisting essentially of, or consisting of silicon nitride sandwiched between a pair of layers consisting essentially of, or consisting of silicon.
- the layers of silicon can have thicknesses of from about 5 ⁇ A to about 50 ⁇ A, with a typical thickness being about 20 ⁇ A; and the middle layer of silicon nitride can have a thickness of from about 5 ⁇ A to about 1 ,000A, with a typical thickness being about 30 ⁇ A.
- Fig. 2 shows a top view of a semiconductor wafer fragment comprising the Fig. 1 cross-section, and shows retaining structure 30 extending entirely across the upper surface of the semiconductor construction.
- openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 are formed through retaining structure 30, mass 28, and to the node locations associated with an upper surface of substrate 12, (with the node locations 20, 22, 24 and 26 being shown in Fig. 3).
- the openings can have a very high aspect ratio, and ultimately are utilized for forming capacitor containers (as discussed below).
- the openings can have an elevation of from about 2 to about 3 microns, and a maximum width of about 0.1 micron.
- the openings are shown to have circular outer peripheries (as illustrated by the top view of Fig. 4), but it is to be understood that the openings can have other shapes.
- the openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, and 54 are ultimately utilized to form containers of capacitor constructions, as discussed in more detail below.
- the openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, and 54 are formed over memory array region 14 of construction 10, and while the openings are formed a trench 56 is formed within location 16 of construction 10.
- trench 56 is shown formed simultaneously with the openings over memory array region 14, and accordingly is shown formed utilizing the same etch as that used to form the openings, it is to be understood that the trench can be, in alternative processing (not shown), formed with an etch separate from that utilized to form the openings over the memory array region.
- the etch utilized to form the trench can be conducted either prior to, or after, the etch utilized to form the container openings associated with memory array region 14.
- the formation of the container openings within memory array region 14 and the trench within location 16 would typically be accomplished by first forming a photoresist mask (not shown) with photolithographic processing, and subsequently transferring a pattern from the patterned mask to underlying materials 28 and 30, followed by removal of the patterned photoresist mask.
- the photolithographic requirements associated with formation of the patterned mask can be relatively stringent, and accordingly an anti reflective layer (not shown) can be incorporated into structure 30, formed beneath structure 30, or formed over structure 30 in various aspects of the present invention.
- the antireflective coating can comprise, for example, either a hard film (for example, dielectric antireflective coating, (DARC)), or a spin-on film (for example, bottom antireflective coating, (BARC)).
- DARC dielectric antireflective coating
- BARC bottom antireflective coating
- openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 are described as extending through material 28 to underlying conductive nodes (such as nodes 20, 22, 24, and 26) it is to be understood that one or more other layers (not shown) can be provided between the nodes and material 28, and that the openings can stop on the other layers.
- an etch stop layer (not shown) can be provided between material 28 and nodes 20, 22, 24, and 26 so that the openings stop on the etch stop layer.
- the etch stop layer can protect underlying materials (such as the surface of substrate 12 and/or electrical devices (not shown) supported by the surface during a subsequent isotropic etch of material 28 (discussed below).
- the openings can be extended through the etch stop and to nodes 20, 22, 24, and 26 with a second etch after the etch through material 28.
- the etch stop can comprise any suitable material to which material 28 can be selectively etched, and can, for example, comprise, consist essentially of or consist of silicon nitride.
- a conductive layer 60 is formed within openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54, as well as within trench 56.
- Electrically conductive layer 60 can be a homogeneous composition of electrically conductive material, or can comprise multiple layers of electrically conductive material. Accordingly, layer 60 can comprise, consist essentially of, or consist of one or more electrically conductive materials.
- the electrically conductive materials within layer 60 can comprise any suitable materials, including, for example, conductively-doped silicon, metal, and metal compounds. In particular aspects, layer 60 will comprise titanium nitride.
- Portions of layer 60 within the openings in memory array region 14 can be considered to form container structures within the openings. For instance, Fig. 5 shows the portions of layer 60 within openings 40, 42, 44 and 46 corresponding to container constructions 62, 64, 66 and 68.
- the container constructions can be considered to comprise inner surfaces 70 within the openings and outer surfaces 72 laterally opposed to the inner surfaces. The outer surfaces 72 extend along mass 28 and retaining structure 30.
- Conductive layer 60 is ultimately incorporated into a capacitor electrode, and in particular aspects can be incorporated into a capacitor storage node. Accordingly, layer 60 can be referred to as capacitor electrode material, and in particular aspects can be referred to as electrically conductive storage node material.
- Conductive material 60 is shown to only partially fill the openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54, and thus to form container structures within the openings. In other aspects of the invention (not shown) the conductive material 60, either alone or in combination with other conductive materials, can completely fill the openings to form pedestal (or post) structures within the openings.
- conductive material 60 is removed from over an upper surface of structure 30 to electrically isolate conductive structures within openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 (such as, for example, the container structures 62, 64, 66 and 68 of Fig. 7) from one another.
- An exemplary method for removing conductive material 60 from over upper surface 30 is chemical-mechanical polishing.
- a patterned mask 80 is formed over memory array region 14, peripheral region 18, and the location 16 between regions 14 and 18.
- Mask 80 entirely covers regions 16 and 18, but is patterned over region 14 to form rows 82 connecting pairs of capacitor rows. Portions of material 60 in openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 are shown in phantom view in Fig. 8 to indicate that such portions are covered by masking material 80.
- An exemplary material of mask 80 is photoresist, and such can be formed into the shown pattern utilizing photolithographic processing.
- the illustrated shape of patterned mask 80 is but one of many possible patterns that can be utilized in methodology of the present invention.
- the shown shape of patterned mask 80 has strips extending horizontally relative to the view of Fig. 8. In other exemplary shapes (not shown) patterned strips of material 80 can extend to entirely cover particular containers, to extend diagonally relative to the view of Fig. 8 and/or to extend vertically relative to the view of Fig. 8.
- the conductive material 60 within trench 56 is shown in phantom view in Fig. 8 to indicate that such material is covered by masking material 80.
- Containers 84 and 86 extend to node locations 85 and 87, which can comprise similar constructions to those described above relative to node location 22.
- Container constructions 84 and 86 comprise the interior peripheries 70 and outer peripheries 72 described previously with reference to containers 62, 64, 66 and 68 of Fig. 5.
- masking material 80 extends into openings 34, 42 and 50. Specifically, the masking material extends along the interior lateral surfaces 70 of each of the openings, and in the shown aspect extends entirely along at least one of the interior lateral surfaces 70 of each of the openings.
- a sacrificial material (not shown) would be provided in openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 during the above-described chemical-mechanical polishing of layer 60.
- the sacrificial material can be removed from within the openings at any suitable processing stage, which may be a stage before provision of masking material 80, or a stage after provision of masking material 80. If the sacrificial material remains in the openings during provision of masking material 80, the sacrificial material may preclude material 80 from entering the openings. In such aspects, material 80 may not be along the interior surfaces of the openings, but instead would be over the openings.
- Fig. 9 illustrates a slightly different aspect of the invention than Figs. 7 and 8.
- Retaining structure 30 physically contacts the material 60 of the capacitor containers within each row.
- the retaining structure 30 can contact all of the container structures associated with an array over memory device region 14, and in other aspects the retaining structure can contact only some of the capacitor devices. It can be preferred, however, that the retaining structure contact all of the devices in order to alleviate (and preferably prevent) toppling and other structural defects from occurring in the devices in subsequent processing (described below).
- Figs. 10 and 12 illustrate structures in which material 30 is removed relative to material 28 with high selectivity so that effectively little or none of material 28 has been removed during the removal of material 30.
- Fig. 13 illustrates construction 10 at the processing stage of Fig.
- an etch is considered to be selective for a first material relative to a second material if the etch removes the first material at a faster rate than the second material, including, but not limited to, conditions in which the second material is substantially not removed during the removal of the first material (i.e., conditions in which the rate of removal of the second material is essentially 0).
- the removal of material 28 exposes outer surfaces 72 of the container structures (such as, for example, the container structures 62, 64, 66 and 68 of Fig. 14). In the shown aspect of the invention, material 28 is substantially entirely removed from over memory region 14, and accordingly an entirety of outer surfaces 72 are exposed.
- the invention encompasses other aspects in which only a portion of material 28 is removed by the isotropic etch, and accordingly wherein only portions of the outer surfaces 72 are exposed.
- a material resistant to the etch of material 28 i.e., an etch stop
- the etch stop material can be provided under material 28 in aspects of the invention which are not shown. If the etch stop material is present, such can protect features underlying the etch stop during the isotropic etch of material 28.
- Retaining material 30 remains in physical contact with portions of conductive mate ⁇ al 60 of the containers formed from material 60, and accordingly supports the containers. Retaining structure can thus alleviate, and even prevent, toppling or other structural defects from occurring within an array of container structures.
- Structural material 30 can enable container structures having a high aspect ratio to be formed, and to have outer surfaces (72) exposed, while alleviating, and in particular aspects even preventing, toppling of the containers.
- retaining material 30 connects alternating pairs of rows of a container structure array.
- the conductive material 60 associated with individual containers is shown in Figs. 14-16 to be in the a shape of an annulus or a ring. It is to be understood, however, that the invention encompasses other aspects in which material 60 is formed in different shapes. Also, as discussed previously, the invention encompasses aspects in which material 60 (alone or in combination with other conductive materials) is in the shape of a pedestal instead of being in the shown shape of a container.
- the retaining material 30 can provide structural support to the pedestals in such aspects of the invention.
- the conductive material 60 within trench 56, together with the material 30 over periphery 18 forms a protective barrier (or shield) so that the isotropic etching of material 28 over memory region 14 does not extend into the material 28 associated with peripheral region 18.
- Such can alleviate damage to circuitry (not shown) associated with peripheral region 18 that could otherwise occur if an isotropic etch penetrated into the material 28 associated with peripheral region 18.
- the protective material 60 within trench 56 forms a protective trough (or moat) 71 which protects material 28 of peripheral region 18 from the isotropic etch utilized in removing material 28 from over memory array region 14.
- the moat is double-sided.
- conductive material 60 covers both sides of trench 56. It is to be understood, however, that the invention includes other aspects (not shown) in which the conductive material is only along the side of trench 56 nearest peripheral region 18, and is thus not on the side of trench 56 nearest memory array region 14.
- the illustrated double-sided trough (or moat) 71 has a pair of spaced sidewalls 73 and 75. Electrically insulative material 28 has a lateral sidewall 77 at a lateral periphery of region 18, and sidewall 75 of trough 71 is a liner along the lateral 77 of material 28. In the shown aspect of the invention, sidewall 75 is directly against (i.e., physically contacts) the portion of material 30 over region 18.
- the sidewall 75 can be directly against both the BPSG of layer 28 and the silicon nitride of layer 30 that extends over region 18.
- Conductive material 60 can, for example, comprise, consist essentially of, or consist of titanium nitride. Accordingly, the invention encompasses aspects in which a liner containing titanium and nitrogen is directly against both the material 28 (which can be, for example, BPSG) and the layer 30 (which can be, for example, silicon nitride).
- Sidewall 73 of trough 71 has an inner surface facing first sidewall 75 and an opposing outer surface facing memory array region 14. A portion of material 30 is shown directly against the outer surface and extending over memory array region 14.
- the portion of material 30 extending over memory array region 14 comprises the segments (or rows) 102 which connect adjacent rows of capacitor container structures to one another.
- the trough 71 of material 60 forms a shield which protects a lateral periphery of material 28 over region 18 from the isotropic etching conditions utilized to remove material 28 from over memory array region 14.
- the trough 71 formed by conductive material 60 is electrically isolated from any circuitry associated with construction 10.
- a portion of retaining structure 30 is shown jutting from a surface of the conductive material 60 within trench 56 (such portion is labeled as 95 in Fig. 14). In particular aspects, the portion 95 can be eliminated.
- a dielectric material 100 and a conductive material 103 are formed within openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54, as well as along outer sidewall edges 72 of the container structures.
- Conductive material 60 of the capacitor container structures can be referred to as a first capacitor electrode, and conductive material 103 can be referred to as a second capacitor electrode.
- the capacitors are container capacitors, it is to be understood that the capacitors can also be pedestal capacitors (i.e., can comprise the dielectric material 100 and the conductive material 103 extending around pedestals of material 60) in accordance with various aspects of the invention discussed above.
- retaining structure 30 consist of electrically insulative materials so that the retaining structure can remain in construction 10 (as shown in Figs. 17- 19), without shorting between capacitor container structures in physical contact with retaining structure 30.
- the invention can encompass other aspects (not shown) in which structure 30 is removed after formation of one or both of dielectric material 100 and second capacitor electrode 102; and in such aspects retaining structure 30 can comprise electrically conductive materials in addition to, or alternatively to, electrically insulative materials.
- Retaining structure can be removed after formation of one or both of dielectric material 100 and second capacitor electrode 102 since the dielectric material and second capacitor electrode can each provide structural stability to the container structures (such as, for example, structures 62, 64, 66 and 68 of Fig. 14), so that the container structures can be supported without retaining structure 30.
- retaining structure 30 is to be removed, such can be accomplished utilizing, for example, photolithographic patterning to form a mask (not shown), followed by an appropriate etch, or etches, to penetrate any materials over retaining structure 30 and subsequently remove retaining structure 30.
- a gap 104 is illustrated beneath the portion of retaining structure 30 jutting outwardly from the protective material 60 within trench 56.
- gap 104 can, in particular aspects, be filled through appropriate deposition of one or both of dielectric material 100 and conductive material 102.
- the gap 104 is provided to show one aspect of the invention. Conditions can typically be chosen under which dielectric material 100 and conductive material 102 deposit well on the underside of supporting layer 30, and accordingly there would be no gap 104.
- Transistor structures 110, 112, 114 and 116 are diagrammatically illustrated in Fig. 17. The transistor structures would have source/drain regions either encompassing node locations 20, 22, 24 and 26, or ohmically connected with node locations 20, 22, 24 and 26.
- the transistor devices and capacitor constructions formed in accordance with methodology of the present invention can be together incorporated into an array of DRAM cells.
- FIG. 19 shows regions 120 and 122 beneath the retaining structure 30 filled with materials 100 and 102.
- a single homogeneous retaining structure (30) was shown over an upper surface of mass 28.
- the invention encompasses other aspects in which more than one retaining structure (or alternatively considered, a retaining structure comprising more than one layer) is utilized.
- the invention also comprises aspects in which a retaining structure is provided at an elevational location other than the top surface of mass 28.
- Figs. 20-22 illustrate processing in which three retaining structures are utilized at different elevational locations within mass 28. In referring to Figs. 20-22 similar numbering will be utilized as was used above in describing Figs. 1-19, where appropriate.
- Construction 200 similar to the construction 10 of Fig. 1 is illustrated.
- Construction 200 comprises substrate 12 and node locations 20, 22, 24 and 26.
- Construction 200 also comprises insulative mass 28 and retaining structure 30 over mass 28.
- Construction 200 differs from the construction of Fig. 1 in that construction 200 further comprises a second retaining structure 202 over an upper surface of substrate 12 and beneath mass 28; and a third retaining structure 204 elevationally located within the thickness of mass 28.
- Retaining structures 202 and 204 are shown to extend over memory array region 14 of construction 200, but not over peripheral region 18 of the construction (although in other aspects, not shown, one or both of retaining structures 202 and 204 can also extend over peripheral region 18).
- Structures 202 and 204 can comprise compositions similar to those previously described for structure 30. Accordingly, structures 202 and 204 can consist essentially of, or consist of silicon nitride. Alternatively, structures 202 and 204 can comprise, consist essentially of, or consist of a silicon nitride layer together with one or more layers consisting essentially of, or consisting of materials other than silicon nitride. The layers other than silicon nitride can include, for example, dielectric materials, such as, for example, aluminum oxide. [0086] Referring to Fig. 21 , construction 200 is illustrated at a processing stage analogous to that previously described with reference to Fig. 3. Openings 40, 42, 44 and 46 extend through mass 28, as well as through retaining structures 202, 204 and 30.
- trench 56 extends through retaining structure 30 and mass 28.
- the shown aspect is but one aspect of the invention, and in other aspects, structures 202 and 204 can be outside of trench 56 so that a periphery of the trench does not extend to the structures.
- construction 200 is shown at a processing stage analogous to that described previously with reference to Fig. 14. Specifically, retaining structure 30 has been patterned and subsequently material 28 has been exposed to an isotropic etch which is selective for material 28 relative to the material of retaining structures 30 and 204. Retaining structure 204 protects the material 28 thereunder from exposure to the etch, and accordingly the etch effectively stops at retaining structure 204. [0088] The construction 200 of Fig.
- FIG. 22 comprises container-shaped capacitor electrodes 62, 64, 66 and 68 similar to the electrodes of Fig. 14 (and in other processing, not shown, could comprise pedestal-shaped capacitor electrodes).
- the electrodes of Fig. 22 only have portions of their outer sidewall surfaces (72) exposed, rather than having an entirety of the outer sidewall surfaces exposed.
- the retaining structure 204 can thus provide additional structural integrity to the container structures 62, 64, 66 and 68 beyond that provided by retaining structure 30 alone.
- Figs. 23 and 24 illustrate a construction 300 at a processing stage analogous to that of Fig. 1. Structure 300 is shown in a top view in Fig.
- FIG. 24 shows a cross section of Fig. 23 along the line 24-24, with such cross section being analogous to the cross section of Fig. 9, but being at a processing stage earlier than that of Fig. 9.
- Construction 300 comprises the retaining structure 204 described previously with reference to Figs. 20-22, but does not contain the retaining structure 30 described previously with reference to Figs. 1 -22, nor does it contain the retaining structure 202 described with reference to Figs. 20-22.
- Openings 34, 42 and 50 are illustrated in phantom in Fig. 24 to indicate where the openings will be formed, and to indicate that the openings are not yet formed at the processing stage of Fig. 24.
- Retaining structure 204 is shown patterned so that the locations of openings 34, 42 and 50 extend to structure 204.
- the location of patterned structure 204 is shown in phantom view in Fig. 23, where it can be seen that the retaining structure has a pattern comparable to that adopted by patterned structure 30 in Fig. 11. Accordingly, retaining structure 204 extends to locations where capacitor container openings will ultimately be formed.
- the container openings can be formed through mass 28, and can be formed to have a periphery comprising retaining structure 204.
- the construction of Figs. 23 and 24 can be formed by initially forming a first portion of material 28, and then forming the patterned retaining structure 204 over the first portion of material 28. Subsequently, a second portion of material 28 can be formed over the patterned retaining structure.
- retaining structures (such as, for example, structures 30, 202 and 204) can comprise single layers, or multiple layers.
- Figs. 25- 28 illustrate exemplary aspects of the invention in which retaining structure (or lattice) 30 comprises multiple layers of material.
- FIG. 25 a construction 500 is illustrated at the processing step described previously with reference to Fig. 1.
- Construction 500 is similar to the construction 10 described in Fig. 1 , except that the material 30 of Fig. 25 is illustrated comprising two separate layers 502 and 504.
- One of layers 502 and 504 can, in particular aspects of the invention, comprise, consist essentially of, or consist of silicon nitride.
- the other of layers 502 and 504 can, in particular aspects of the invention, comprise, consist essentially of, or consist of silicon, and can be in the form of, for example, amorphous silicon and/or polycrystalline silicon.
- one aspect of the invention is a selective etch for material 28 relative to retaining structure 30.
- it can be desired to have a thin layer of silicon nitride be the predominate material of layer 30, in that silicon nitride is an electrically insulative material which is, relatively cheap and easy to deposit and pattern.
- a problem in utilizing silicon nitride can be that it is difficult to etch materials commonly utilized for mass 28 relative to silicon nitride. For instance, if mass 28 comprises borophosphosilicate glass, it can be difficult to selectively etch the borophosphosilicate glass relative to silicon nitride to the extent desired in various applications.
- the silicon nitride is preferably very thin, and yet mass 28 is very thick, so if the selectivity for the material of mass 28 is not extremely high, the silicon nitride will be etched by the time that the entirety of mass 28 is etched. Accordingly, it can be advantageous to utilize a component of structure 30 for which the etch of material 28 has enhanced selectivity relative to the selectivity of the etch toward silicon nitride.
- Suitable materials can be materials consisting essentially of, or consisting of silicon. If the silicon remains undoped, such can effectively be an insulative material, and accordingly can have advantages similar to those of silicon nitride.
- the silicon can be in any form, including, polycrystalline, either smooth grain or hemispherical grain, and/or amorphous.
- a polysilicon layer can be more resistant than silicon nitride to the chemistries typically utilized during the etching back of glasses (such as, for example, the 25:1 HF chemistry utilized to etch borophosphosilicate glass).
- the silicon can be either the top layer or the bottom layer. Silicon on the top can be removed by subsequent container chemical-mechanical polishing (CMP).
- CMP container chemical-mechanical polishing
- FIG. 26 shows a structure 550 illustrating an alternative aspect of the present invention.
- Structure 550 is shown at a processing stage analogous to that of structure 500 in Fig. 25.
- Structure 550 is similar to the structure 500 of Fig. 25, except that the retaining structure 30 of construction 550 comprises three layers, instead of the two of structure 500.
- the three layers of the retaining structure of construction 550 are labeled 552, 554 and 556, respectively.
- layers 552 and 556 (the outer layers of the retaining structure stack 30) can comprise, consist essentially of, or consist of silicon; and layer 554 (the inner material of the retaining structure stack 30) can consist essentially of, or consist of silicon nitride.
- retaining structure 30 comprises a pair of materials 604 and 606.
- Materials 604 and 606 can be similar to the materials 502 and 504 described with reference to Fig. 25.
- material 604 can consist essentially of silicon nitride or consist of silicon nitride
- material 606 can consist essentially of silicon or consist of silicon.
- a spacer 610 is provided over an exposed sidewall of the material 604.
- Spacer 610 can be formed by, for example, forming a layer of appropriate material and subsequently anisotropically etching the layer.
- Spacer 610 can comprise the same composition as layer 606, and accordingly can consist essentially of, or consist of silicon.
- the utilization of layers 610 and 606 provides protection to exposed sidewalls of material 604 as well as to an upper surface of the material during a subsequent etch of material 28 (such as, for example, the etch described previously with reference to Fig. 14).
- Fig. 28 shows an expanded view of the region 28 of structure 600 in accordance with an alternative aspect of the invention relative to that shown in Fig. 27.
- the expanded region comprises structure 30, and shows the structure to comprise a layer 612 in addition to the layers 604 and 606.
- Layer 612 is under layer 604, and in particular aspects layer 612 can consist essentially of, or consist of silicon.
- the stack comprising layers 612, 604 and 606 can be a layer consisting of silicon (612), a layer consisting of silicon nitride (604), and a layer consisting of silicon (606) over the silicon nitride.
- the sidewall spacer 610 is shown formed along an exposed sidewall of the stack containing layers 612, 604 and 606. As discussed above, the composition of 610 can consist essentially of or consist of silicon.
- layer 604 can comprise silicon nitride, and such layer can be entirely surrounded by layers consisting essentially of, or consisting of silicon (the shown layer 606, 610 and 612).
- layers 606, 610 and 612 can comprise the same composition as one another, it is to be understood that the invention also encompasses aspects in which layers 606, 610 and 612 comprise different compositions relative to one another.
- layer 610 comprises silicon
- the silicon utilized to form the layer can extend into the container openings associated with memory region 14 (such as, for example, the container openings for 40, 42 44 and 46 of Fig. 27).
- the silicon can subsequently be removed from within the container openings by an appropriate etch.
- the silicon can be left within the container openings, conductively doped, and incorporated into a capacitor electrode.
- the surrounding of a silicon nitride material 604 with materials more resistant to an etch than silicon nitride can be advantageous.
- the etch utilized to remove material 28 is typically an isotropic etch. Accordingly portions of silicon nitride material 604 would ultimately be exposed to the etch unless the portions are covered by a protective material, regardless of whether the portions are on the top, bottom or side of the silicon nitride material.
- the utilization of polysilicon and/or amorphous silicon within material 30 can enable the material to function as a hard mask during formation of the container openings and trench at the processing stage of Figs.
- the trench can have a different critical dimension and/or other patterning aspects than the container openings. Utilization of a hard mask without overlying photoresist can be advantageous in forming the different patterning aspects and/or critical dimension of the trench and container openings. Specifically, the hard mask can allow for more consistent etch rates between the trench and the container openings than would occur with a photoresist mask. As discussed in more detail below, the trench can extend entirely around memory array circuitry. If the trench is etched too deeply and/or widely, the etch can penetrate into the peripheral circuitry and cause damage to various circuit devices, such as, for example, digit lines. Frequently a silicon nitride etch stop will be provided over the peripheral circuitry, but the etch to form the trench may even penetrate through an etch stop if it is overly enhanced relative to etching utilized to form container openings.
- the trough 71 described with reference to Figs. 14-17 can be advantageously utilized to entirely surround a region of a semiconductor construction.
- the trough is created by forming an electrically conductive material in trough-shaped configuration between a memory array region and a peripheral region (see, for example, Figs. 14 and 15 where the trough 71 is described as being formed from conductive material 60 over the region 16 between memory array region 14 and peripheral region 18).
- Figs. 29 and 30 illustrate exemplary configurations in with the trough is formed to protect a lateral periphery of a peripheral region from the isotropic etch utilized to remove material from region 14 (an exemplary isotropic etch is described above with reference to Figs.
- FIG. 29 shows a top view of an exemplary construction 700 comprising a substrate having a memory array region 14 (diagrammatically illustrated as a box bounded by dashed line 708), a region 18 peripheral to the memory array where logic or other circuitry can be formed (diagrammatically illustrated as a box bounded by dashed line 704), and a region 16 between the memory array region 14 and the peripheral region 18.
- the memory array region has a lateral periphery defined to entirely laterally surround the memory array region, with such lateral periphery corresponding to dashed line 708, and the peripheral region has a similar lateral periphery defined by dashed line 704.
- Trough 71 of conductive material 60 is shown laterally surrounding an entirety of the lateral periphery of memory array region 14, and thus the liner 75 defined by a sidewall of the trough entirely laterally surrounds the memory array region 14.
- Fig. 30 shows a top view of the construction 700 illustrating that the trough 71 of conductive material 60 can extend entirely around the lateral periphery of the peripheral region as well as extending entirely around the lateral periphery of the memory array region.
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Abstract
Description
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JP2006542721A JP5007465B2 (en) | 2003-12-10 | 2004-12-01 | Method for forming capacitor device |
EP04812703.9A EP1700332B1 (en) | 2003-12-10 | 2004-12-01 | Capacitors and method of forming the same |
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KR (1) | KR100868812B1 (en) |
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- 2004-12-01 EP EP04812703.9A patent/EP1700332B1/en not_active Not-in-force
- 2004-12-01 KR KR1020067011542A patent/KR100868812B1/en not_active IP Right Cessation
- 2004-12-01 CN CNB2004800369167A patent/CN100405541C/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
WO2005062349B1 (en) | 2005-09-15 |
KR100868812B1 (en) | 2008-11-14 |
TW200531146A (en) | 2005-09-16 |
US20060063345A1 (en) | 2006-03-23 |
JP2007512716A (en) | 2007-05-17 |
KR20060110321A (en) | 2006-10-24 |
JP5007465B2 (en) | 2012-08-22 |
TWI252511B (en) | 2006-04-01 |
EP1700332A1 (en) | 2006-09-13 |
US20060063344A1 (en) | 2006-03-23 |
US7449391B2 (en) | 2008-11-11 |
JP2012146993A (en) | 2012-08-02 |
US20050287780A1 (en) | 2005-12-29 |
US7271051B2 (en) | 2007-09-18 |
US7125781B2 (en) | 2006-10-24 |
US7420238B2 (en) | 2008-09-02 |
CN1890778A (en) | 2007-01-03 |
EP1700332B1 (en) | 2014-11-26 |
US20050054159A1 (en) | 2005-03-10 |
CN100405541C (en) | 2008-07-23 |
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