WO2005041256A2 - An integrated circuit micro-cooler using self-assembled nano structures - Google Patents
An integrated circuit micro-cooler using self-assembled nano structures Download PDFInfo
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- WO2005041256A2 WO2005041256A2 PCT/US2004/027449 US2004027449W WO2005041256A2 WO 2005041256 A2 WO2005041256 A2 WO 2005041256A2 US 2004027449 W US2004027449 W US 2004027449W WO 2005041256 A2 WO2005041256 A2 WO 2005041256A2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01057—Lanthanum [La]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- Y10S977/763—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less formed along or from crystallographic terraces or ridges
Definitions
- This invention relates to the removal of heat generated by an integrated circuit and the components used in chip assembly and packaging to facilitate said heat removal. More specifically, this invention discloses the application of self-assembled nano-structures for improving the performance of heat sink structures coupled to integrated circuit devices.
- Prior art used to cool semiconductor ICs incorporates the use of large and expensive chip packaging having externally mounted, filmed heat sinks coupled to the ceramic or plastic encapsulated IC chip.
- the power generated by these chips also increases, often in geometric proportion to increasing density and functionality, the video processing and CPU application areas, the ability to dissipate the heat being generated by current ICs is becoming a serious limitation in the advance of technology.
- relatively large interface-thermal-resistances are added when the die is 'attached' to a heat spreader, heat pipe or heat sink. These multiple interfaces have the undesired side effect of increasing total die to heat sink resistance and making heat transfer more difficult.
- FIG. 1 is a cross section schematic view of a simplified integrated circuit structure.
- Transistor structure 102 is formed near the top surface of substrate 100.
- Electrical interconnects 106 are used to make contact with transistor 102 and numerous other similar devices (not shown) on the substrate 100.
- "Solder balls" 104 are utilized to complete the interconnect of the integrated circuit to a printed circuit board or wire leadframe. This type of package is often referred to as a "flip chip” device.
- heat generated by transistor 1 02 is extracted through the substrate 100 to the back surface of the chip.
- a heat transfer bonding layer 108 may be utilized to enhance heat conduction by reducing interfacial heat tiansfer resistance created by air gaps and surface irregularities.
- this layer may be composed of a thermal grease or thermally conductive epoxy These materials, while better that solid surface/surface contact, still have a relatively poor thermal conductivity when compared to solid metals As a result, the backside chip surface interface still presents a significant thermal resistance which limits the power that can be extracted from the chip.
- US Patent Application Publication number US2003/0117770 has disclosed a process of forming a thermal interface that employs carbon nano-tubes to l educe thermal resistance between an electronic device and a heat sink.
- Bundles of aligned nano-tubes receive injected polymeric material m molten form to produce a composite w hich l s p laced b etween t he e lectronic d evice a nd t he h eat sink
- the nanotubes are aligned parallel to the direction of heat energy.
- the polymeric filler does little to spread heat laterally, potentially creating localized hot spots on the device surface.
- the use of bundles of aligned carbon nano-tubes may result m reduced thermal conduction as well.
- interstitial voids between the nano-tubes are not filled m ordei to maintain flexibility.
- This disclosure fails to provide any method to reduce matting and nano-tube to nano-tube contact, which reduces the effective thermal conductivity of the structure
- CVD diamond films are good conductors, they may not be thermally compatible (from an expansion perspective) with a number of other metallic materials utilized in various heat sink structures.
- commonly known techniques for growing carbon nano-tubes would preclude carbon nanotube deposition directly on a silicon circuit die, since these techniques require temperatures in the range of 700 to 800 °C. Exposing a completed circuit die to these elevated temperatures is not a recommended practice. What is needed is a method and structure by which interface resistances are minimized by integrating several thermal components to maximize heat transfer from hot surfaces on the integrated circuit.
- a method for fabricating a micro- cooler device includes fashioning a shallow cavity in a mounting surface of a heat sink body, growing rod-like nano-structures within the shallow cavity, and depositing a thermally conductive material in interstitial voids between the rod-like nano-structures.
- Figure 1 is a cross section schematic view of an integrated circuit structure
- Figure 2 is a schematic side view of integrated micro-cooler device attached to a flip chip integrated circuit according to an embodiment of the present invention
- Figure 3 i s a s chematic side view of integrated micro-cooler device attached to multiple flip chip integrated circuits according to an embodiment of the present invention
- Figure 4 is a cross section schematic view of a finned integrated micro-cooler device showing the details of construction according to an embodiment of the present invention
- Figure 5 is a cross section schematic view of an integrated micro-cooler device having internal flow channels according to an embodiment of the present invention
- Figure 6 i s an e lectron m icroscope p hoto o f c arbon n ano-tubes according to an embodiment of the present invention
- Figure 7 is a cross section schematic view of an integrated micro-cooler device bonded to multiple flip chip integrated circuits according to an embodiment of the present invention
- Figure 8 is a process flow diagram illustrating the steps for manufacture of a finned integrated micro-cooler device according to an embodiment of the present invention
- Figure 9 is a process flow diagram illustrating the steps for manufacture of an integrated micro-cooler device having internal flow channels according to an embodiment of the present invention.
- Figure 10 is a partial cross section view of the nano-structure array subsequent to a planarization process according to an embodiment of the present invention.
- Figure 1 (prior art) has been addressed above in the Background section of this disclosure.
- Figure 2 is a schematic side view 200 of integrated micro-cooler device 202 attached to a flip chip integrated circuit 206 according to an embodiment of the present invention.
- the integrated micro-cooler device 202 is a separate structure from chip 206 containing highly conductive, self assembled nano structures, integrated with heat sinking devices. It provides a low thermal resistance path for heat transferred from surface 208 of the i ntegrated c ircuit chip 206 m ounted on e ircuit b oard 210 b elow.
- Thermal interface layer 204 provides a low resistance interface containing nano-structures to enhance heat conduction from chip 206, reduce the impact of local hot spots in chip 206, and laterally conduct heat to a heat sink structure 202 of greater footprint than the chip 206.
- Structural details of micro-cooler device 202 are disclosed below.
- Chip 206 and micro-cooler 202 may be bonded together using eutectic layers or thermal bonding adhesives (not shown), as is known to those skilled in the art. Additionally, micro-cooler device 202, integrated circuit chip 206, and circuit board 210 maybe held together with mechanical straps, clips, or holding devices (not shown).
- FIG. 3 is a schematic side view 300 of integrated micro-cooler device 302 attached to multiple flip chip integrated circuits (306a-306d) according to an embodiment of the present invention.
- both the upper and lower surfaces of micro- cooler device 302 are utilized to remove heat energy from flip chip ICs 306a-306d.
- Chips 306 and micro-cooler 302 may be bonded together using eutectic layers or thermal bonding adhesives (not shown), as is known to those skilled in the art. Additionally, micro-cooler device 302, integrated circuit chips 306, and circuit boards 310 may be held together with mechanical straps, clips, or holding devices (not shown). Although the embodiment shown in Figure 3 contains four integrated circuits, it should be evident to those of ordinary skill in the art that any number of additional integrated circuit flip chips 306 maybe added by increasing the scale of device 302.
- Figure 4 is a cross section schematic view of a finned integrated micro-cooler device 400 showing the details of construction according to an embodiment of the present invention.
- the device 400 comprises a heat sink body 404 for extracting thermal energy from surface 418 of flip chip 402.
- Heat energy is delivered to heat sink surface 420 by an enhanced heat transfer interface structure containing layers 408, 410, and 412.
- Heat sink body 404 is fabricated with fins 414 (or pin shaped structures) to enhance heat extraction by convection, typically forced air flow generated by fans or other devices. However, natural convection may also be employed if suitable.
- fins 414 may be immersed in a liquid such as water or another liquid phase coolant for removal of high energy fluxes.
- Heat sink body 404 may be made from silicon, metals, or heat conductive ceramics. Metals such as copper or aluminum are preferred, but structures fashioned from silicon substrates may also be used. If silicon is used, the fin surfaces may be coated with a metal to enhance 1 ateral h eat c onduction.
- H eat s preading c avity 416 i s fashioned w ithin h eat sink body 404 by methods well known to those skilled in the art, to contain heat transfer interface layers 408, 410, and 412.
- Layer 408 contains individually separated, rod-like nano-structures that provide very high thermal conductivity to reduce interface contact resistance. These structures may be comprised of metallic nano-wires, or preferably multi walled carbon nano-tubes (MWCNT) or multi-wall carbon nano-fibers.
- MWCNT multi walled carbon nano-tubes
- Metallic nanowires for example Au, Cu, Ni, zinc oxide, and metal borides
- metallic nanowires are metal crystals having the shape of a wire with dimensions comparable to the phonon mean free path (usually tens of nanometers at room temperature) so as to benefit from quantum confinement phenomena allowing for efficient heat transport characteristics and thermal contact.
- metal boride nanowires are believed to have good thermal contact resistance since low ohmic contact resistance has been demonstrated with Ni electrodes.
- the MWCNTs are oriented (with their longitudinal axis) approximately perpendicular to surfaces 420 and 418, parallel to the direction of heat flow. MWCNTs have very high (on axis) thermal conductivity, generally within the range of 800 to 3000 W/m-°K.
- the MWCNT may be up to a factor of two better than solid CVD diamond films. They are preferably grown on the micro-cooler 400 surface as an array of free standing, vertically aligned, individually separated carbon nanotubes (or nanofibers) that occupy between about 15 and 40% of the surface from which they are grown.
- the MWCNT are grown by plasma enhanced CVD (PECVD) growth methods. For example, the methods described by Jun Li et al. (Applied Physics Letters, vol. 81, no.5, July 2002) and L. Delzeit et al. (J. Appl. Physics 91, 6027, May, 2002) can be used.
- lateral thermal conduction in the non-axial direction from nano-tube to nano-tube
- lateral thermal conduction in the non-axial direction from nano-tube to nano-tube
- lateral contact between axially aligned nano-tubes can reduce their effective axial thermal conductivity. If the number of carbon nano-tubes attached to substrate is too high (for example, > 40%> CNT density) Van der Waals force will create a bundle or mat situation resulting in poor thermal conduction. If, on the other hand the coverage density is too low (for example, ⁇ 15%), thermal c onduction will also be lower due to the reduced number of conducting nanotubes.
- a preferred range a coverage density is between about 15 and 40%, with 25% to 40% being most preferred.
- thermally conductive material is placed within the interstitial voids between the MWCNTs.
- the thermally conducting material provides lateral heat conduction within the nano-tube containing layer. Lateral heat conduction facilitates the spreading of heat from a relatively small silicon die surface to the much larger surface area of the heat sink body 404. It also reduces localized hot spots on surface 418 of chip 402.
- the thermally conductive material may be a metal or metal alloy, thermally conductive ceramics, CVD diamond, or thermally conductive polymers.
- the thermally conductive material is a metal such as copper, aluminum, silver, gold, or their alloys.
- metal materials copper and copper alloys are the most preferable. This is generally due to the high thermal conductivity, ease of deposition via electroplating or electrochemical deposition, and low cost. Copper electroplating is well known to those skilled in the art of dual Damascene processing c ommon i n t he p roduction o f m odern i ntegrated c ircuits. D epending o n the thermal conductivity of the thermally conductive filler material, layer 408 would typically be between 50 and 1000 microns in thickness.
- metal as a filler material is that it is significantly lower in hardness than the MWCNTs.
- planarization of layer 408 is used to maintain flatness for good "long range” contact.
- “short range” surface irregularities on the order of a few microns) can also contribute significantly to interface thermal resistance. It is therefor desirable to have some portion of the MWCNTs extend from the bulk of layer 408 so that the exposed ends may conform to these surface irregularities and improve thermal contact.
- layer 408 is planarized, the softer metal material is eroded more than the harder nanotubes, resulting in an undercutting of the metal layer. This undercutting leaves a portion of the nanotubes extending from the composite layer 408.
- bonding layer 406 is an interface material which can be used with a silicon heat sink body 404. Typically, layer 412 would be composed of silicon nitride compounds.
- metal heat sink bodies 404 layer 412 is optional, is only required to aid in the adhesion of catalyst metal layer 410.
- Metal catalyst layer 410 is used to initiate and control growth of the nanotubes in layer 408.
- Metal catalyst layer 410 may chosen from among Ti, Co, Cr, Pt, Ni and their alloys.
- metal catalyst layer 410 are Ni and Ni alloys. Further process conditions related to these layers are discussed below.
- Figure 5 is a cross section schematic view of an integrated micro-cooler device
- the device 500 comprises a heat sink body 504 for extracting thermal energy from surface 518 of flip chip 502. Heat energy is delivered to heat sink surface 520 by an enhanced heat transfer interface structure containing layers 508, 510, and 512. Layers 508-512 reside in heat spreading cavity 516 fashioned in body 504.
- heat sink body 504 contains enclosed flow passages 514 to remove the thermal energy transferred from chip 502. Both liquid and gas cooling is possible, but for this embodiment liquid cooling is preferred due to the specific heat capacity of a liquid coolant such as water. A refrigerant is also possible for use in very high heat removal systems, or where sub ambient junction temperatures are required for very high speed processors.
- FIG. 506-512 have the same function and are composed of the same materials as described above for corresponding layers 406-412.
- Figure 6 i s an e lectron m icroscope p hoto o f c arbon n ano-tubes according to an embodiment of the present invention.
- Figure 7 is a cross section schematic view of an integrated micro-cooler device 700 attached to multiple flip chip integrated circuits according to an embodiment of the present invention.
- the device 700 comprises a heat sink body 704 for extracting thermal energy from heat generating multiple flip chips 702a and 702b.
- Heat energy is delivered to heat sink surfaces 720a and 720b by an enhanced heat transfer interface structure containing layers 508a-512a and 508b-512b. Layers 508a- 12a and 508b-512b reside in heat speading cavities 716a and 716b, respectively.
- heat sink body 704 contains enclosed flow passages 714 to remove the thermal energy transferred from chip 502.
- liquid cooling is preferred due to the specific heat capacity of a liquid coolant such as water.
- FIG. 8 is a process flow diagram 800 illustrating examplary steps for manufacture of a finned integrated micro-cooler device according to an embodiment of the present invention.
- a suitable material is selected for the substrate or heat sink body (e.g., 404).
- the subsequent steps refer to a process where silicon is chosen as the substrate.
- heat spreading cavities e.g., 416) are patterned in a first (or bottom) surface.
- the heat spreading cavities are etched, and at 808, an interface material (e.g., 412) is deposited in the cavities (e.g., 416).
- this interface material is silicon nitride in some embodiments. Numerous techniques are known to those skilled in the art to deposit silicon nitride, examples of which are CVD, or sputtering. Alternatively, the heat spreading cavities can be fabricated by machining if the heat sink body material is chosen to be a metal or ceramic.
- an optional conductive layer is deposited over the interface layer, to facilitate the deposition and adhesion of the subsequent catalyst layer. The conductive layer would be composed of Ti, Cr, or Pt with thickness in the range of 3nm - 200nm.
- a conductive layer may not be required.
- a catalyst material chosen from among Ti, Co, Cr, Pt, Ni, and their alloys is deposited using CVD, PVD, electroplating or electroless deposition to a layer thickness of 3 nm to 30 nm.
- a carbon nanotube array (e.g., as part of layer 408) of individually separated carbon nanotubes is grown. In some embodiments, the array is grown via PECVD per the method of J. Li and A. Delzeit referenced previously.
- a thermally conductive material is deposited between the carbon nanotubes.
- the material is typically deposited by electrochemical deposition or CVD as is known to those skilled in the art. If a CVD diamond interstitial material is used, CVD processes known in the art can be used.
- the carbon nanotube containing layer e.g., 408 is planarized by CMP, electrochemical etching, or a combination of both.
- an optional eutectic bonding layer e.g., 406 of appropriate thickness is added if desired.
- fins e.g., 414) are patterned in a second (or top) surface for silicon substrates.
- the fins are etched by well known methods.
- the fins are coated with an optional metal coating or CVD diamond, deposited at the appropriate thickness required to minimize temperature gradients along the fins' surfaces.
- the fins are fabricated by well known machining processes.
- Figure 9 is a process flow diagram 900 illustrating examplary steps for manufacture of an integrated micro-cooler device having internal flow channels according to an embodiment of the present invention.
- the flow passages e.g., 514 are fabricated in the heat transfer body (e.g., 504).
- the heat transfer body e.g., 504
- fins may be fabricated as described in the embodiments shown in figure 8.
- FIG. 10 is a partial cross section view 1000 of the nano-structure array subsequent to a planarization process according to an embodiment of the present invention.
- Carbon nanotubes or nanowires 1008 are grown from the metal/catalyst layer 1002 in an approximately parallel structure as shown.
- a thermally conductive filler material 1004 is placed in the voids between the nano- strucures 1008. Planarization of the nano-structures produces a gap 1006 between the ends of the nano-structures and the recessed planarized surface of the filler material.
- Gap 1006 results from a chemical-mechanical planarization (CMP) process when a composite material c ontaining c omponents o f s ignificantly d ifferent h ardness i s p lanarized.
- CMP chemical-mechanical planarization
- the planarization process will undercut the filler since the metal is much softer than the carbon nanotubes.
- the same effect can be created by chemical (or electrochemical) etching of the filler metal, since base metals such as copper are more reactive and susceptible to chemical dissolution than the relatively chemically inert carbon nanotubes.
- the unsupported nano-structures in gap 1006 are relatively flexible, allowing the exposed ends to twist and bend (on a micron scale) to conform to undulations and imperfections in the heat generating surface of the integrated circuit chip. This "hair brush" effect produces intimate contact with the ends of the nano-structures, allowing heat extraction along the axis of the nanotubes, where their thermal conductivity is the greatest.
- the expected gap dimension 1006 depends on the surface flatness of the circuit, silicon die and of the planarized micro-cooler surface.
- the RMS value of the surface asperity is believed to lie in the range of 0.2 um to 3 um with preferred values being at the lower end of the range.
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Abstract
Description
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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EP04809610A EP1658634A4 (en) | 2003-08-25 | 2004-08-25 | System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US49784903P | 2003-08-25 | 2003-08-25 | |
US60/497,849 | 2003-08-25 |
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Also Published As
Publication number | Publication date |
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US7109581B2 (en) | 2006-09-19 |
WO2005041256A3 (en) | 2006-04-13 |
KR20070027482A (en) | 2007-03-09 |
US8039953B2 (en) | 2011-10-18 |
CN100416781C (en) | 2008-09-03 |
EP1658634A2 (en) | 2006-05-24 |
EP1658634A4 (en) | 2009-10-28 |
US20060270116A1 (en) | 2006-11-30 |
CN1856871A (en) | 2006-11-01 |
US20050046017A1 (en) | 2005-03-03 |
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