WO2005038926A1 - Semiconductor device and method of manufacturing such a semiconductor device - Google Patents

Semiconductor device and method of manufacturing such a semiconductor device Download PDF

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Publication number
WO2005038926A1
WO2005038926A1 PCT/IB2004/052109 IB2004052109W WO2005038926A1 WO 2005038926 A1 WO2005038926 A1 WO 2005038926A1 IB 2004052109 W IB2004052109 W IB 2004052109W WO 2005038926 A1 WO2005038926 A1 WO 2005038926A1
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die
side face
connection regions
semiconductor device
device
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PCT/IB2004/052109
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French (fr)
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Hans-Martin Ritter
Wolfgang Schnitt
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Philips Intellectual Property & Standards Gmbh
Koninklijke Philips Electronics N.V.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

The invention relates to a semiconductor device (10) with a die (1) having a number of side faces (2,3,4,5) and comprising a semiconductor body with a substrate and comprising at least one semiconductor element with at least three electrical connection regions (6,7,8,9) at the surface of the die (1) for electrically connecting the semiconductor element, wherein the connection regions (6,7,8,9) are positioned on the surface of the die (1) in a hexagonal spacing. According to the invention the semiconductor device (10) is a discrete device (10) or an integrated discrete device (10) and at least a first side face (2) of the die runs parallel to a line (L) connecting two connection regions (6,8) that are closest 10 neighbors and at least a second side face (3) that borders the first side face (2) makes an angle of about 60 or 120 degrees with the first side face (2). In this way the device (10) may have equal-sided triangular or parallelogram-shaped dies (1,1') which take full advantage of the hexagonal spacing of the connection regions (6,7,8,9). In this way the largest number of devices (10) can be obtained from a wafer. The invention also comprises a method of manufacturing a device (10) according to the invention.

Description

Semiconductor device and method of manufacturing such a semiconductor device

The invention relates to a semiconductor device with a die having a number of side faces and comprising a semiconductor body with a substrate and comprising at least one semiconductor element with at least three electrical connection regions at the surface of the die for electrically connecting the semiconductor element, wherein the connection regions are positioned on the surface of the die in a hexagonal spacing. The invention also relates to a method of manufacturing such a device.

A device as mentioned in the opening paragraph is known from US patent 4,616,406 which was issued on October 14, 1986. Therein such a device is described which comprises a semiconductor body comprising a large number of semiconductor elements in the foπn of an IC (= Integrated Circuit) which consequently comprises a large number of connection regions which are arranged on the surface of the die of the device in a hexagonal spacing. In this way, the die - and thus the device — may contain the largest number of connection regions for a given surface of the die. This is due to the fact that such a hexagonal spacing results in the closest packing of connection regions on the surface. A drawback of the above device is that it is not optimal for every type of semiconductor device with respect to the occupation of the die by the connection regions.

It is therefore an object of the present invention to avoid the above drawback and to provide a device which is optimal with respect to the occupation of the die by the connection regions. To achieve the above object a device of the kind mentioned in the opening paragraph is characterized in that the semiconductor device is a discrete or an integrated discrete device and that at least a first side face of the die runs parallel to a line connecting two connection regions that are closest neighbors and at least a second side face that borders the first side face makes an angle of about 60 or 120 degrees with the first side face. The present invention is firstly based on the recognition that in the known device the occupation of the die is not optimal near the side faces of a square die, that is to say near at least two side faces of the die. This is caused by the fact that the hexagonal spacing corresponds with alternating lines of connection regions which are mutually displaced over half the distance between two neighboring connection regions. The invention further is based on the recognition that this loss of surface is very minimal in an IC like the known device, as such a device comprises a very large number of connection regions and thus the number of connection regions that border the (two) side faces in question is relatively small. The inventor realizes that this is different in a discrete or an integrated discrete device which comprises a relatively small number of connection regions, as a consequence of which a relatively large number of connection regions borders a side face in question. Finally, the invention is based on the recognition that by providing the side faces of the die of such a discrete or integrated discrete device with an angle of 60 or 120 between those side faces, the occupation of the surface by the connection regions again becomes optimal. Moreover, such a non-conventional angle has fewer negative consequences in an (integrated) discrete device which is relatively small than in a relatively large IC as in the former an encapsulation of the device forms a larger part of the final device than in the latter case. Thus in a device according to the invention the surface occupation of connection regions is maximal and thus for a given number of connection regions the surface of the die may be minimal. In this way, the largest number of dies can be obtained from a wafer in which the dies are formed and thus the cost of manufacturing is smaller per die. In a first preferred embodiment of a device according to the invention the die has three side face and the third side faces borders the first and second side face and makes an angle of about 60 degrees with those side faces. In this way the die has the form of a triangle with equal sides. The die may in this case preferably contain a semiconductor element like a bipolar transistor or a field effect transistor, each having three connection regions that may be positioned close to the edges of the triangle with equal sides. However, the die may also comprise as a semiconductor element two diodes with one common electrode or a single diode and a passive two-way electrical element, also having one connection in common with the diode. In a second preferred embodiment of a device according to the invention the die has four side faces, a third side face running parallel to the first side face and a fourth side face running parallel to the second side f ace. In this case the die has the form of parallelogram and the, e.g. four, connection regions are again positioned close to the edges thereof. The semiconductor element may be in such a case a device like a thyristor. However, it also may be a transistor with a passive element in common connection or two diodes in a parallel or anti-parallel configuration with no connection in common. Of course, the advantage of the invention remains if the triangular or parallelogram-shaped die of the above embodiments comprises a larger number of semiconductor (and other) elements with a corresponding larger number of connection regions. Optimal results in case of a triangular device are obtained in devices where the maximum number of connection regions is 3, 6, 10, 15 and so on. For a die having the shape of a parallelogram, the maximum number of connection regions in such an integrated discrete device may be 2, 4, 6, 8 and so on. For technical reasons, e.g. related to the specific semiconductor and other element(s) in the (integrated) discrete device, a smaller number of connection regions may be present on the surface of a die configured to contam a certain maximum number of connection regions. Preferably the connection regions are provided with balls of a metal or of a solder. In this way the device according to the invention becomes surface mountable, which in particular for discrete or integrated discrete devices is a very attractive way of mounting as the volume occupied by the device may be minimal. In a further attractive embodiment, the substrate of the device is a semiconductor substrate, of which the surface has a <111> orientation. Such an orientation implies for the usual semiconductor materials like silicon, germanium, galliumarsenide and other so-called III-V materials or II- VI materials, which all have diamond-like lattices, that natural cleavage planes are present which make an angle of (about) 60 degrees with each other. If a device according to the invention is formed by e.g. sawing, but the depth of the sawing trench in the wafer comprising a large number of dies is chosen to be less than the thickness of the die, breaking of the dies along these parts in order to completely separate the individual dies is more easy and the resulting form of the die is more regular. Also if another separation technique is chosen, such as etching, advantage may be taken of the crystal properties inherent to the orientation chosen. Preferably, in a device according to the invention the side faces of the die and the surface of the die opposite to the surface provided with the connection regions are covered with an electrically insulating encapsulation. Such an encapsulation may be e.g. a resin on for example epoxy base. A method of manufacturing a semiconductor device with a die having a number of side faces and comprising a semiconductor body with a substrate and comprising at least one semiconductor element with at least three electrical connection regions at the surface of the die for electrically connecting the semiconductor element, . wherein the connection regions are positioned on the surface of the die in a hexagonal spacing, is according to the invention characterized in that the semiconductor device is formed as a discrete or an integrated discrete device and at least a first side face of the die is formed such that it runs parallel to a line connecting two connection regions that are closest neighbors and at least a second side face that borders the first side face is formed such that it makes an angle of about 60 degrees with the first side face. In this way devices according to the invention are obtained. In a preferred embodiment of a method according to the invention a large number of dies are foπned in a wafer stage next to each other and the individual dies are obtained by sawing along lines, of which the position corresponds to the positions of the side faces of the individual dies to be formed. In this way triangular dies are formed by sawing along three sets of parallel lines that make an angle of 60 degrees with each other and dies having the shape of a parallelogram are obtained by sawing along two of such sets of lines. In the case of triangular dies, the connection region of each edge of the triangle has the shape of a pie-piece. By forming a larger connection region which has the form of a (larger) round spot of which the center is positioned above an edge of a die to be formed, six pie pieces are formed from the spot during the sawing process which form the connection regions of one edge of six dies that border each other at the location of said edge. It is to be noted in this respect that a connection region in this application is defined as an electrically conducting region, preferably in the form of a metal spot, on the surface of the die. The size and position of such a connection region may differ with the size and position of the actual semiconductor regions formed in the semiconductor body of which the connection region provides a possible electrical connection to the outside world. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter, to be read in conjunction with the drawing, in which

Fig 1 is a three-dimensional view of a first embodiment of a semiconductor device according to the invention, Fig 2 is a view in projection of the semiconductor device of Fig. 1 at a stage in the manufacture of the device by means of a first embodiment of a method in accordance with the invention, Fig 3 is a three-dimensional view of a second embodiment of a semiconductor device according to the invention, and Fig 4 is a view in projection of the a semiconductor device of Fig. 3 at a stage in the manufacture of the device by means of a second embodiment of a method in accordance with the invention.

The figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various Figures. Figure 1 shows in a three-dimensional view a first embodiment of a semiconductor device according to the invention and Figure 2 shows in projection the semiconductor device of Figure 1 at a stage in the manufacture of the device by means of a first embodiment of a method in accordance with the invention. The device 10 comprises a semiconductor body 1 which comprises in this case a silicon substrate and an epitaxial silicon layer on top thereof, also not shown separately. In this semiconductor body 1 e.g. a bipolar transistor is formed, of which the base, emitter and collector are connected to three, here pie-piece shaped, connection regions 6,7,8 on top of the surface of the die 1 and not shown separately in the drawing in this case (comprising) a metal region, e.g. of gold. On top of said connection regions 6,7,8 there are solder balls 11 which make the device 10 suitable for surface mounting. The die itself is triangular in this example, the side face 2,3,4 of the die 1 making an angle with each other of 60 degrees. Circular metal spots 22 (see Figure 2) from which the pie-piece shaped connection regions 6,7,8 of the dies 1 are formed, are positioned in hexagonal spacing on the surface of a wafer 100 in a final stage of the manufacturing of many dies 1 in a wafer 100. In this way the optimal packing density of connection regions 6,7,8 on the die is obtainable. Moreover, such optical configuration is obtained in this example by the equal-sided triangular shape of individual dies 1,1'. The direction of the side faces 2,3,4 are parallel to a connecting line between two neighboring connection regions 6-7, 7-8, 8-6 of the die(s) 1,1'. In the final stage of manufacturing (see Figure 2), the dies 1,1', which, like in this example, are preferably provided already with the solder balls 11 - not shown in Figure 2 - are separated by a sawing process from the wafer 100 in which they are jointly formed by semiconductor technology. The wafer is first sawn along parallel and equidistant lines L, next this process is repeated along lines M and N that make an angle of 60 degrees with lines L. In Figure 2 only 4 of such lines L,M,N are shown and indicated by means of subscripts 1-4. Preferably one group of lines, here lines L, runs parallel to a facet 20 of the wafer 100 which in this example has the <111> orientation. In this way the side face 2,3,4 of the dies 1,1' to be formed are roughly parallel to natural cleavage planes of the crystal of the die 1. This makes (partly) breaking of the dies 1,1' more easy and is favorable also if other separation techniques, like etching, are used . Figure 3 shows in a three-dimensional view a second embodiment of a semiconductor device according to the invention and Figure 4 shows in projection the semiconductor device of Figure 3 at a stage in the manufacture of the device by means of a second embodiment of a method in accordance with the invention. The main difference between the device 10 of Figure 4 and that of Figure 1 is that the die 1 now is provided with four side faces 2,3,4,5 which either make an angle of 60 degrees (side faces 2,5 and 3,4) or of 120 degrees with each other (side faces 2,3 and 4,5). The connection regions 6,7,8,9 are now positioned at a small distance from of the edges of the parallelogram shaped die 1. Again solder balls 11 are present thereon. In this example the die 1 contains four connection regions 6,7,8,9 e.g. corresponding to two discrete diodes formed in the semiconductor body 1. In Figure 4 a number of parallelogram shaped dies 1,1' are visible in a final stage of the manufacturing of the dies 1,1' in a wafer 100. In this view one may clearly notice that the connection regions 6,7,8,9 are again positioned in a hexagonal spacing, implying that they extend in lines which are alternatingly translated over half the distance between two neighboring connection regions 6,7 in a line. In this case the sawing is done only along two sets of lines L,M making an angle of 120 degrees with each other. After sawing group L, the sawing blade is rotated through said angle and group M is sawn. For both embodiments disclosed above, it holds that after the separation process of the dies 1,1', either completely sawing or by partly by sawing and breaking, individual dies 1,1' can be picked up, e.g. by vacuum tweezers, from a rubber foil - not shown in the drawing - on which the wafer 100 was attached before the sawing process. Side faces 2,3,4(5) of the dies 1,1' as well as the face opposite to the face comprising the connection regions 6,7,8(9) may be provided with an electrically insulating encapsulation, also not shown in the drawing. Alternatively, such an encapsulation may be provided in the wafer stage after the sawing operation, by filling the sawing lanes with the encapsulation, and transferring the wafer to another rubber foil in order to provide the back side with encapsulation. Individual dies 1,1' can then be obtained by renewed sawing in the filled sawing lanes, but using a thinner sawing blade. The sawing lanes may also be enlarged before filling by extending the foil. After encapsulation - and testing - individual devices 10 are obtained that are suitable for surface mounting on e.g. a PCB (= Printed Circuit Board). It will be obvious that the invention is not limited to the examples described herein, and that within the scope of the invention many variations and modifications are possible to those skilled in the art. For example, instead of a triangle with equal sides or a parallelogram, a device according to the invention may have other shapes, such as a regular hexagonally shaped die ("benzene ring structure"). In such a case sawing from a wafer is not very practical. Instead other separation techniques like laser scribing or etching or other separation techniques may be used in such a case, possibly in combination with breaking or cleaving of a thin remainder part of the semiconductor body connecting the dies. It is further noted that a device according to the invention, may also be a wire-bonded device. In such a case the device may be mounted on a lead frame. The device may be completely surrounded in such a case by e.g. a resin encapsulation which also covers and protects the wire bonds between the connection regions on the surface of the die and the inner parts of the leads of the lead frame.

Claims

CLAIMS:
1. Semiconductor device (10) with a die (1) having a number of side faces (2,3,4,5) and comprising a semiconductor body with a substrate and comprising at least one semiconductor element with at least three electrical connection regions (6,7,8,9) at the surface of the die (1) for electrically connecting the semiconductor element, wherein the connection regions (6,7,8,9) are positioned on the surface of the die (1) in a hexagonal spacing, characterized in that the semiconductor device (10) is a discrete device (10) or an integrated discrete device (10) and at least a first side face (2) of the die runs parallel to a line (L) connecting two connection regions (6,8) that are closest neighbors and at least a second side face (3) that borders the first side face (2) makes an angle of about 60 or 120 degrees with the first side face (2).
2. Semiconductor device (10) according to claim 1, characterized in that the die (1) has three side faces (2,3,4) and the third side face (4) borders the first and second side face (2,3) and makes an angle of about 60 degrees with those side faces (2,3).
3. Semiconductor device (10) according to claim 2, characterized in that the semiconductor element is a transistor, of which the connection regions (6,7,8) are positioned close to the edges of the triangle with equal sides formed by the three side faces (2,3,4) of the die (1).
4. Semiconductor device (10) according to claim 1, characterized in that the die has four side faces (2,3,4,5), a third side face (4) running parallel to the first side face (2) and a fourth side face (5) running parallel to the second side face (3).
5. Semiconductor device (10) according to claim 4, characterized in that the at least one semiconductor element has four connection regions (6,7,8,9) which are positioned close to the edges of the parallelogram formed by the four side faces (2,3,4,5) of the die (1).
6. Semiconductor device (10) according to any one of the preceding claims, characterized in that the connection regions (6,7,8,9) are provided with balls (11) of a metal or of a solder.
7. Semiconductor device (10) according to any one of the preceding claims, characterized in that the substrate is a semiconductor substrate, of which the surface has a <111> orientation.
8. Semiconductor device (10) according to any one of the preceding claims, characterized in that the side faces (2,3,4,5) of the die (1) and the surface of the die (1) opposite to the surface provided with the connection regions (6,7,8,9) are covered with an electrically insulating encapsulation.
9. Method of manufacturing a semiconductor device (10) with a die (1) having a number of side faces (2,3,4,5) and comprising a semiconductor body with a substrate and comprising at least one semiconductor element with at least three electrical connection regions (6,7,8,9) at the surface of the die (1) for electrically connecting the semiconductor element, wherein the connection regions (6,7,8,9) are positioned on the surface of the die (1) in a hexagonal spacing, characterized in that the semiconductor device (10) is formed as a discrete or an integrated discrete device (10) and at least a first side face (2) of the die (1) is formed such that it runs parallel to a line connecting two connection regions (6,7) that are closest neighbors and at least a second side face (3) that borders the first side face (2) is formed such that it makes an angle of about 60 or 120 degrees with the first side face (2).
10. Method as claim in claim 9, characterized in that a large number of dies
(1,1') are formed in a wafer (100) stage next to each other and in that individual dies (1,1') are obtained by sawing along lines (L,M,N), of which the position corresponds to the positions of the side faces (2,3,4,5) of the individual dies (1,1') to be formed.
PCT/IB2004/052109 2003-10-21 2004-10-15 Semiconductor device and method of manufacturing such a semiconductor device WO2005038926A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009017448A1 (en) * 2007-07-27 2009-02-05 Syntune Ab Method for producing electronic devices on a wafer.
EP2190015A1 (en) * 2007-09-12 2010-05-26 Aisin Seiki Kabushiki Kaisha Power semiconductor chip, power semiconductor module, inverter device, and inverter-integrated type motor
US20110168317A1 (en) * 2010-01-12 2011-07-14 Fujifilm Corporation Controlled Bond Wave Over Patterned Wafer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3169837A (en) * 1963-07-31 1965-02-16 Int Rectifier Corp Method of dicing semiconductor wafers
US4253280A (en) * 1979-03-26 1981-03-03 Western Electric Company, Inc. Method of labelling directional characteristics of an article having two opposite major surfaces
US5744858A (en) * 1992-07-17 1998-04-28 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US20030052417A1 (en) * 2000-03-08 2003-03-20 Takashi Hosaka Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3169837A (en) * 1963-07-31 1965-02-16 Int Rectifier Corp Method of dicing semiconductor wafers
US4253280A (en) * 1979-03-26 1981-03-03 Western Electric Company, Inc. Method of labelling directional characteristics of an article having two opposite major surfaces
US5744858A (en) * 1992-07-17 1998-04-28 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US20030052417A1 (en) * 2000-03-08 2003-03-20 Takashi Hosaka Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009017448A1 (en) * 2007-07-27 2009-02-05 Syntune Ab Method for producing electronic devices on a wafer.
EP2190015A1 (en) * 2007-09-12 2010-05-26 Aisin Seiki Kabushiki Kaisha Power semiconductor chip, power semiconductor module, inverter device, and inverter-integrated type motor
EP2190015A4 (en) * 2007-09-12 2015-04-22 Aisin Seiki Power semiconductor chip, power semiconductor module, inverter device, and inverter-integrated type motor
US20110168317A1 (en) * 2010-01-12 2011-07-14 Fujifilm Corporation Controlled Bond Wave Over Patterned Wafer

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