WO2004114386B1 - Methods and system for processing a microelectronic topography - Google Patents

Methods and system for processing a microelectronic topography

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Publication number
WO2004114386B1
WO2004114386B1 PCT/US2004/019349 US2004019349W WO2004114386B1 WO 2004114386 B1 WO2004114386 B1 WO 2004114386B1 US 2004019349 W US2004019349 W US 2004019349W WO 2004114386 B1 WO2004114386 B1 WO 2004114386B1
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WO
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Application
Patent type
Prior art keywords
method
process
step
comprises
microelectronic topography
Prior art date
Application number
PCT/US2004/019349
Other languages
French (fr)
Other versions
WO2004114386A2 (en )
WO2004114386A3 (en )
Inventor
Igor C Ivanov
Weiguo Zhang
Artur Kolics
Original Assignee
Blue29 Corp
Igor C Ivanov
Weiguo Zhang
Artur Kolics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

Methods and systems are provided which are adapted to process a microelectronic topography, particularly in association with an electroless deposition process. In general, methods are provide which include loading a topography into a chamber and supplying fluids to an enclosed area about the topography. In particular, a method is provided for forming a hydrated metal oxide layer. In addition, a method is provided for selectively depositing a dielectric layer and a metal layer upon a topography. A topography having a single layer with at least four elements lining a lower surface and sidewalls of a metal feature is also provided. A process chamber which includes a gate configured to either seal or provide an air passage to the chamber and a substrate holder comprising a clamping jaw with a lever are contemplated herein. A process chamber with a reservoir arranged above a substrate holder is also provided.

Claims

AMENDED CLAIMS [received by the International Bureau on 07 July 2005 (07.07.2005); original claims 10, 12-20, 22, 29, 31, 34, 37, 39, 47, 50, 51, 53-56, 61, 68, 70-73, 75, 82-86,
88, 92, 98, 105, 123, 130 and 134-136 amended; claims 1-9, 11, 32, 33, 36 38, 48, 49, 59, 60,
62-67, 74, 87, 93, 110, 111, 113-122, 128, 129 and 131-133 canceled; claims 139-162 added]
10. Λ microelectronic topography process chamber, comprising: a substrate hold r; at least two outer enclosure components configured to: couple with each other to form a first enclosed area about and including the substrate holder; and uncouple from each other lo provide access to the substrate holder; and at least two inner enclosure components comprising a lower component spaced below the substrate holder and an upper component spaced above the substrate holder, wherein the inner enclosure components are configured to- couple with each other lo form a second enclosed area about and including the substrate holder within the first enclosed area; and uncoil]. lc fiom each other to provide access to the substrate holder. 12. he microelectronic topography pi ocess chamber of claim 10, wherein the microelectronic topography piocess clumber is adapted to; perform a succession of different process steps witliin the process chamber; couple the outer enclosure components prior to the succession o -tie different process steps; and couple and uncouple the inner enclosure components between the different process steps without uncoupling the outer enclosure components.
13. The microelectronic topography process chamber of claim 10, wherein the microelectronic topography process chamber is adapted to couple the inner enclosure components prior to an clectroless deposition process and uncouple the inner enclosure components subsequent to the elec-rυless deposition process.
14. The micioclecπonic topography process chamber of claim 10, wherein the microelectronic topography process chamber is adapted to uncouple the outer enclosure components for a drying process of the microelectronic topo iaphy. 15, The microelectronic topography process chamber of claim 10, wherein the microelectronic topography process cha ber is adapted to dispense different processing fluids into the first and second enclosed areas during the iffcici.t process sreps.
16. The microelectronic topography process chamber of claim 15, wherein the microelectronic topography process chamber comprises: at least one first oullet within one of the outer enclosure components; and at least one second outlet witliin one of the inner enclosure components.
58 17 , The microelectronic topography process chamber of claim 16, wherein the microelectronic topography process chamber is adapted to prevent processing fluids in the first enclosed area from entering the second enclosed area.
1 R. The microelectronic topography process chamber of claim 11, wherein the microelectronic topography process chamber comprises a means for spinning the substrate holder.
10, The microelectronic topography process chamber of claim 15, wherein a means for dispensing the different process fluids comprises an inlet positioned below the substrate holder and configured to project one or more of the different process fluids toward a predetermined region above the substrate holder.
20. Λ method for processing a microelectronic topography, comprising: loading the microelectronic topography into a process chamber; closing the process chamber to form a first enclosed area about the microelectronic topography; supplying a first set of fluids lo -lie first enclosed area to process -lie microelectronic topography in one or more process steps; forming a second, distinct enclosed area about the mjcroclectionic topography within the first enclosed area subsequent to the step of supplying the first set of fluids; and supplying a second set of fluids to the second enclosed area to further process the microelectronic topography m one or more other process steps.
21. The method of claim 20, wherein the first set of fluids comprises fluids for preparing the microelectronic topography for an clecirolcss deposition process, and -wherein the second set of fluids comprises a deposition solution for the clccti olcss deposition process.
22. The method of claim 21, further comprising disengaging the second enclosed area .subsequent to t step of supplying the second set of fluids; and supplying a third set of fluids to -lie first enclosed area to process the microelectronic topography subsequent to the electroless deposition process.
23. The method of claim 22, further comprising spinning the microelectronic topography, wherein the step of spinning comprises spinning die microelectronic topography at a sufficient rate during the steps of supplying the first and ihiid sels of fluids lo prevent the first and third sets of fluids from dispensing through one of a plurality of outlets within the process chamber.
24. The method of claim 23, wherein the step of spinning the microelectronic topography comprises spinning the microelectronic topography between approximately 0 rpm and approximately 8000 rpm.
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25. The method of claim 23, wherein the step of spinning the microelectronic topogiaphy comprises: spinning the microelectronic topography between approximately 0 rpm and approximately 20 rpm during Ihe step of supplying the set second set of fluids, and spinning the microelectronic topogiaphy between appioximately 40 ipm and appioximatcly 300 rpm during the steps of supplying the first and third sets of fluids.
26. 1 he method of claim 22, wherein the step of supplying the fluid set of fluids comprises introducing a gas into -lie proces . chamber to dry the microelectionic topography.
27. The method of claim 26, wherein the step of introducing the gas comprises opening the process chambci to ambient air
28. The method of claim 26, wherein the step of introducing the gas comprises injecting the gas through a gas
2! Ihe method of claim 20, wherein the first set of fluids comprises a deposition solution for an electroless deposition process, and wherein the second set of fluids compn .es fluids for processing the microelectronic topography M-bscquent to the electroless deposition process
30. '- he method of cl-um 20, wherem the second enclosed area is smaller than the fust enclosed area, and w eiem the step offoιm.ι.fi the second enclosed area comprises moving a cover plate arranged wilhm the first enclosed area toward a base plate of the process chamber.
31. Λ melhod of minimizing the acci.i--ul-.lion of bubbles upon a wafer during an electroless deposition pioccss, compiisnig: loading the wafer into an electroless deposition chamber; sealing the electroless deposition chamber to foim an enclosed area about the wafer; piessu-i ing flic enclosed area between approximately 5 psi and approximately 100 psi; supplying a deposition solution to the enclosed area; and agitiiling ihe deposition solution to create an amount of motion sufficient to form a layer having substantially uniform thickness, wherein the step of agitating comprises pulsing Ihe deposition solution from a spray bar.
34. '1 he method of claim 31, wherein the steps of agitating and pressurizing collectively reduce ihe amount of bubbles formed upon the wafer during the electroless deposition process
35 The method of claim 31, wherein the step of loading the wafer comprises positioning the wafer face-up williin ihe electroless deposition chamber
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37. The method of claim 31, wherein the step of agitating comprises spiaymg the deposition solution at a rate beiwecn appioximately 0.1 gallons per minute and approximately 10 gallons per minute.
39. The method of claim 31 , wherein the step of pulsing comprises pulsing ihe spray at a frequency between approximately 0.1 Hz and about 10 KHz.
40. The method of claim 31, wherein the step of agitating comprises exposing ihe deposition solution to acoustic waves.
41, The method of claim 40, wherein the step of agitating comprises propagating the acoustic waves at an angle between approximately 0° and approximately 90° relative lo a treating surface of the wafer.
42. The method of claim 40, wherein the acoustic waves compnse ultrasonic waves.
43. The method of claim 40, wherein the acoustic waves comprise megasonic waves.
44, The method of claim 31, wherein the step of agitating comprises moving a device through the deposition solution and above the wafer.
45. The method of claim 44, wherein the step of moving the device composes sweeping a brush through the deposition solution and above the wafer
46, The method of claim 45, wherein ihe step of sweeping the brush comprises sweeping the brush in contact with an upper sυiface of the wafer.
47. Λ pioccssing chamber, compi isiug: a first set of supply lines for supplying a deposition solution to the processing chamber for an electroless deposition process; a second set of supply lines for supplying fluids to the processing chamber for processes performed prior to or subsequent to the electroless deposition piocess, at least one inlet coupled to the first set of supply lines for introducing the deposition solution into the processing chambei, and A means of agitating the deposition fluid, wheiein the means of agitating is distinct fio the at least one inlet and comprises a device configured 10 move wilhin an enclosed region of the elec-rolcss deposition chamber.
50. 'I he processing chamber of claim 47, further comprising a platen configured to hold a wafer within the enclosed region during the electroless deposition process, wherein the device is configured to come into contact with an upper sniface of ihe wafei
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51. The processing chamber of claim 47, wherein the device comprises a brash.
52. The processing chamber of claim 47, wherein the means of agitating is further configured to agitate the fluids from the second set of supply lines during processes prior to or subsequent to the electroless deposition process.
53. Λ method for processing a microelectronic topography, comprising: forming a first metal layer upon the microelectronic topography; converting at least a portion of the fust metal layer to a hydrated metal oxide layer; depositing a second metal layer upon the hydrated metal oxide layer; and converting the hydrated metal oxide layer to a metal oxide layer subsequent to the step of depositing ihe second metal layer.
54. The method of claim 53, wherein the step of converting at least a portion of the first metal layer comprises exposing Ihe first elal layer to an oxidizing plasma.
55. The method of claim 53, wherein the step of converting at least a portion of the first metal layer comprises exposing the first metal layer to an oxidizing fluid,
56. The method of claim 53, wherein the step of converting at least a portion of the first metal layer comprises exposing the first metal layer to irradiating photons.
57. The method of claim 53, wherein the first metal layer comprises tantalum and the hydrated metal oxide layer comprises tantalic acid.
5δ. The method of claim 53, wherein the step of forming the first metal layer comprises forming a metal layer selected from a group consisting of tantalum, tantalum nitride, lanlalum silicon nitiide, tantalum carbon nitride, titanium, titanium nitride, titanium silicou nitride, tungsten and tungsten nitride.
61. The method of claim 53, wherein the step of converting the hydrated metal oxide layer to a metal oxide layer comprises heating the microelectronic topography to a temperature greater than approximately 400° C.
GS. Λ ethod for processing a microelectronic topography, comprising: depositing a barrier layer upon the microelectronic topography; hydratinjj at least a port ion of the barrier layer to form a metal oxide sub-layer; depositing a first metal layer above the metal oxide sub-layer using an electroless deposition process; and converting the melal oxide sub-layer into a second melal layer subsequent to the step of depositing the first metal layer.
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69. The method of claim 68, wherein the barrier layer comprises a material selected froin a group consisting of tantalum, lanlalum mtride, tantalum silicon nitride, tantalum catbon nitride, titanium, titanium nitride, titanium silicon mtnde, tungsten, tungsten nitride, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbidc, and silicon oxycarbon nitride.
70. The method of claim 68, wherein the first metal layer comprises copper.
71. The method of claim 68, wherein the step of depositing the barrier layer comprises lining a trench of a microelectronic topography and wherein the step of depositing the first metal layer comprises filling a substantial portion of the trench.
72. 1 he method of claim 68, further comprising depositing an activation seed layer upon the metal oxide sublayer prior lo the step of depositing the first metal layer.
73. 1 he method of claim 68, wherein the slep of depositing the first metal layer comprises depositing the first metal layer directly upon and in contact with the metal oxide sub-layer.
75. Λ method for processing a microelectronic topography, comprising: selectively depositing a second dielectric layer upon a first dielectric layer; exposing the microelectronic topography to deionized water to strengthen the adherence of the second dielectric layer to the first dielectric layer; and subsequently selectively depositing a metal layer upon portions of the topography arranged adjacent to the first dielectric layer.
76. The method of claim 75, wherein the step of selectively depositing the second dielectric layer comprises depositing a hydrophobia material.
77. The method of claim 75, wherein the step of depositing the hydrophobic material comprises depositing dichloiodimclhylsilanc.
78. The method of claim 75, further comprising removing the second dielectric layer subsequent to the step of selectively depositing the metal layer.
79. '1 he method of claim 75, wherein the slep of selectively depositing the metal layer comprises depositing the melal layer using an electroless deposition process.
80. The method of claim 75, wherein the step of selectively depositing the second dielectric comprises depositing the second dielectric layer using organic vapor phase deposition.
81. The method of claim 75, wherein the step of selectively depositing the second dielectric reduces the deposition of the metal layer upon the first dielectric.
82. Λ microelectronic topography, comprising: a metal feature comprising a second metal layer formed upon and in contact with a first metal layer; and a dielectric portion comprising a lower layer of hydrOphilic material and upper layer of hydropbobic material, wherein an upper surface of the lower layer is substantially coplanar with an upper surface of the fust metal layer.
83. The microelectronic topography of claim 82, wherein a lower surface of the lower layer and a lower surface of the melal feature are substantially coplanar,
84. 'ihe microelectronic topography of claim 82, wherein a thickness of the upper layer is less than approximately 500 angstroms.
85. Λ microelectronic topography comprising a metal feature having a single layer lining a lower surface and sidewalls of the metal feature, wherein the single layer comprises: three elements each comprising between approximately 0.1 % and approximately 20% of a molar concentration of the .single layer; and a fourth element comprising the balance of the molar concentration.
86. The microelectronic topography of claim 85, wherein the ihree- elements are selected from a group consisting of boron, chromium, molybdenum, phosphorus, rhenium, and tungsten.
88. The microelectronic topography of claim 85, wherein the fourth element comprises cobalt or nickel.
89. The microelectronic topography of claim 85, wherein the single barrier layer is configured to substantially prevent oxidation.
90. The microelectionic topography of claim 85, wherein the metal feature further comprises a bulk metal layer an -iπgcd upon and in contact with the single banier layer, wherein the single barrier layer is configured to substantially prevent diffusion of the bulk metal layer to other layers within the microelectronic topography.
* I . The microelectronic topography of claim 90, wherein the metal feature further comprises a second single harrier layer arranged upon and in contact with the bulk metal layer, wherein the second single baπ ier layer comprises at lcasl four elements.
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92. A system, comprising: a processing chamber configured to conduct an electroless deposition process and processes performed prior to or subsequent to the electroless deposition process; analytical lest equipment coupled lo the processing chamber for monitoring fluids used for the electroless deposition process and processes performed prior to or subsequent to the electroless deposition process, wherein the analytical test equipment is configured to measure Lhe concentration of at least four components within the fluids selected from a group consisting of boron, chromiurn, cobalt, molybdenum, nickel, phosphorus, rhenium, and tungsten; and a carrier medium comprising program instructions executable on a computer system for adjusting compositions of the fluids based upon the analysis performed by the analytical test equipment.
94. T e system of claim 92, wherein the analytical test equipment is coupled lo an outlet of the processing cha ber.
95. The syslcm of claim 92, wherein lhe analytical test equipment is coupled to an inlet of the processing chamber. 6. The system of claim 92, furthe comprising a plurality of storage tanks comprising the fluids, wherein the analytical test equipment is coupled to one or more of the storage tanks,
97. The system of claim 92, wherein the carrier medium comprises programs instructions executable on a computer system for adjusting the compositions of the fluids during the electroless deposition process or processes prior lo or subsequent to the electroless deposition process.
98. Λ process chambci, comprising: a wall with an opening; a gate casing arranged adjacent to the wall such that an opening within the gate casing is spaced laterally adjacent to the wall opening; and a gate latch configured to align barriers with the wall opening and the gate casing opening, wherein a portion of the gate latch comprising the barriers is configured to move such that the two openings are either sealed or provide an air passage to the process chamber when the barriers are respectively aligned with the two openings, and wherein the gate latch is configured to simultaneously move the barriers in a substantially similar lateral direction for sealing the openings or for providing the air passage.
99. The process chamber of claim 98, wherein the barriers prevent fluids within lhe process chamber from flowing through flic wall opening and gale casing opening whenever die barriers arc respectively aligned with the two openings.
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100. 1 he process chamber of claim 98, wherein the process chamber is adapted to draw air through the ail- passage and into the process chamber.
101. The pioccss chamber of claim 98, wbciem the gate latch is further configured to move the baiπcrs such that ihe ban lets are not in aligiunent with the wall opening and gate casing opening.
102 The process cliamber of claim 101 , wherein the gate casing opening is spaced in lateral alignment with lhe wall opening.
1 3 lhe process chamber of claim 102, wherein the wall opening and the gate casing opening comprise dimensions large enough to allow one or moie wafers to be loaded within the process cliamber when the barriers arc not in alignment with the two openings.
104. 'Hie process cliamber of claim 98, wherein the gate latch is configured to move within the space between Ihe wall and gale casing
105. Λ method for pi ocessmg a micioelectronic topography within a process chamber, comprising; sealing an opening of the process chamber with a gate latch; exposing the microelectronic topography to a first set of process steps subsequent to the step of sealing; opening the gate latch such that an air passage is provided to Hie process chamber subsequent to the step of exposing the microelectionic topography to the first set of process steps; and exposing the microelectronic topography to a second set of process steps subsequent to the step of opening the gate latch, whcioin the opened gate latch is configured to inhibit liquids within the piocess chamber from entenng the air passage during the step of exposing the microelectronic topogiaphy to the second set of process steps.
106. 'J he method of claim 105, wherein the second set of process steps comprises drying the microelectionic topography.
107. The method of claim 105, wherein the first set of process steps comprises electrolessly depositing a layer upon the niioioelcctrouic topography,
108, The method of claim 105, An (her comprising loading the microelectronic topogiaphy into the pioccss chamber.
J 09 The method of claim 108, wherein the step of loading comprises intioducing the microelectronic topography into the process chamber through lhe opening.
1 12, The method of claim 108, wherein the step of loading comprises introducing the microelectionic topogi aphy into the process chamber through a different opening of the process chamber.
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123. Λ process chamber, comprising: a substrate holder; and a reservoir arranged above the suhstrate holder and within sidewalls of the process chamber, wherein the process chamber is adapted to move the reservoir proximate to the substrate holder, wherein the reservoir comprises a hatch, and wherein the process chamber is adapted to uncouple the hatch from the reservoir and rotate the liatch within the reservoir.
124. The process chamber of claim 123, wherein the reservoir is adapted to hold one or more fluids for processing a microelectronic topography.
125. The process chamber of claim 124, wherein the reservoir is adapted to hold one or more single-phase fluids
126. The process chamber of claim 124, further adapted to replenish the fluids within the reservoir.
127. The process chamber of claim 123, wherein lhe reservoir comprises one or more valves, and wherein the process chamber is adapted to open the valves upon moving the reservoii proximate to the substrate holder.
130. Λ method for processing a microelectronic topography witliin a process chamber, comprising: moving a reservoir proximate to a substrate holder upon which the microelectronic topography is arranged; and dispensing the fluids contained within the reservoir into an enclosed area laterally bound by lhe microelectronic topography and the reservoir, wherein the step of dispensing comprises: opening a hatch arranged along the base of the reservoir; raising lhe hatch within the reservoir; and rotating the hatch subsequent to the step of opening the hatch.
1 4. The method of claim 130, wherein the step of rotating (he hatch is conducted at rate suflϊcient lo prevent the accumulation of bubbles upon lhe microelectronic topography during processing.
135. The method of claim 130, further comprising: closing the hatch; and raising the reservoir to a level spaced above the substrate holder subsequent to closing the hatch.
136. '1 he method of claim 130, wherein the step of dispensing further comprises opening one or more valves arranged along a base of the reservoir.
137. The method of claim 136, further comprising backflowing the fluids tlirough the valves upon completing lhe processing of the microelectronic loρogτaphy.
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138. The method of claim 130, fmther comprising replenishing the fluids within the reservoir while processing the microelectronic topography.
139. The microelectronic topography process chamber or ajm 10, further comprising a means for spinning at least one of the inner enclosure components arranged above the substrate holder.
140. The process chamber of claim 47, further comprising a platen configured to hold a wafer within the enclosed region during lhe electroless deposition process, wherein the device is configured to ove at a level spaced above an upper surface of the wafer within the enclosed region.
141. The process chamber of claim 47, wherein the device is a rod. a block or a plate.
142. The method of claim 68, wherein the step of bydrariυg the metal oxide layer comprises annealing the microelectronic topography in an ambient comprising hydrogen.
143. The method of claim 75, wherein the step of exposing the microelectronic topography to deionii-ed water is conducted during the step of depositing the second dielectric layer.
144. The method of claim 75, wherein the step of exposing the microelectronic topography to deionized water is con ucted subsequent to the step of depositing the second dielectric layer.
145. A microelectronic topography process chamber, comprising: a substrate holder; a means for sealing peripheral walls of the microelectronic topography process chamber to form a first enclosed region about and including the subsirale holder; and a et of enclosure components aπanged witliin the peripheral walls and configured to couple with each other to form a second distinct enclosed area about and including the substrate holder, wherein the microelectronic topography process chamber is adapted to dispense different processing fluids into the first and second enclosed areas during a succession of different process steps, wherein a lower enclosure component of the set of enclosure components comprises an outlet, and wherein the microelectronic topography process cliamber is adapted to pieveut processing fluids in the first enclosed area from entering the outlet.
146. The micioelectronic topography process cliamber of claim 145, wherein the microelectronic topography process chamber is configured to couple and uncouple the set of enclosure components between the different process steps without unsealing the peripheral walls.
147. The microelectronic topography process cliamber of claim 145, fmther comprising a means for spinning an upper enclosure component of the set of euclosute components.
68 148 The microelectronic topography process chamber of claim 145, further comprising a device configured to move within the second enclosed region to agitate one or more of the different processing fluids.
149. A method of minimizing the accumulation of bubbles upon a wafer during an electroless deposition process, comprising: loading the wafer into an electroless deposition chamber; sealing the electroless deposition chamber to form an enclosed area about the wafer; supplying a deposition solution lo the enclosed aiea; and agitating the deposition solution to create an amount of motion sufficient to form a layer having substantially unifoim thickness, wherein the slep of agitaling comprises moving a biush through the deposition solution and above the wafer,
150. The method of claim 149, wherein the step of moving the brush comprises moving lhe brush at a level spaced above the wafer,
151. The method of claim 149, wherein the slep of moving the brush comprises moving the brush along a surface of the wafer.
152. The method of claim 149, wherein the step of agitating is sufficient to create laminar agitation witliin the deposition solution.
153. A mcihod of minimising the accumulation of bubbles upon a wafer during an electroless deposition process, comprising: loading the wafer into an electroless deposition chamber; sealing the electroless deposition chamber to form an enclosed area about the wafer; supplying a deposition solution to the enclosed area; and agitating the deposition solution to create an amount of motion sufficient to form a layer having substantially uniform thickness, wherein the slep of agitating comprises exposing the deposition solution to acoustic waves propagated at an angle greater than approximately 0° and less than approxin lately 90° relative to a treating surface of the wafer.
154. The method of claim 153, wherein the step of agitaling furihcr comprises exposing the deposition solution to acoustic waves propagated parallel to the treating surface of the wafer.
155, The method of claim 153, wherein the step of agitating furllier comprises exposing the deposition solution 1<> acoustic waves propagated perpendicular to the treating surface of the wafer,
156. 'ihe method of claim 153, wherein the step of agitating is sufficient to create laminar agitation within the deposition solution.
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157. A substrate holder, comprising: a shaft coupled to a base platen; and a rod inserted within an opening of the shafl and coupled to a second platen arranged above the base platen, wherein the substrate holder is configured to slide the rod witliin the shaft to move the second platen relative lo lhe base platen.
158. The substrate holder of claim 157, further comprising one or more clamping jaws configured to inhibit vertical and lateral movement of a substrate arranged above the second platen.
159. The substrate holder of claim 158, wherein at least one of the one or more clamping jaws comprises: a support member rigidly coupled to the base platen passing through the second platen; and a lever pivotally coupled to the support member, wherein the lever is configuied to tilt upon raising the second platen such that a portion of the lever is positioned over a portion of lhe substrate.
160. 'J he substrate holder of claim 157, lurtlicr comprising one or more pins rigidly coupled to the base platen and slidingly inserted within openings of the second platen.
161. The substrate holder of claύn 160, wherein the one or more pins are configured to support o substrate when the second platen is lowered to a level below upper surfaces of the one or more pins.
162. The subsuate holder of claim 157, further comprising an annular seal arranged upon the second platen.
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PCT/US2004/019349 2003-06-16 2004-06-16 Methods and system for processing a microelectronic topography WO2004114386B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US10462180 US6860944B2 (en) 2003-06-16 2003-06-16 Microelectronic fabrication system components and method for processing a wafer using such components
US10/462,343 2003-06-16
US10462343 US7883739B2 (en) 2003-06-16 2003-06-16 Method for strengthening adhesion between dielectric layers formed adjacent to metal layers
US10462167 US6881437B2 (en) 2003-06-16 2003-06-16 Methods and system for processing a microelectronic topography
US10/462,167 2003-06-16
US10/462,180 2003-06-16

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