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WO2004109750A3 - Wiring for semiconductor device, thin film transistor array panel including wiring, and manufacturing method thereof - Google Patents

Wiring for semiconductor device, thin film transistor array panel including wiring, and manufacturing method thereof

Info

Publication number
WO2004109750A3
WO2004109750A3 PCT/KR2004/001381 KR2004001381W WO2004109750A3 WO 2004109750 A3 WO2004109750 A3 WO 2004109750A3 KR 2004001381 W KR2004001381 W KR 2004001381W WO 2004109750 A3 WO2004109750 A3 WO 2004109750A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
gate
line
layer
forming
data
Prior art date
Application number
PCT/KR2004/001381
Other languages
French (fr)
Other versions
WO2004109750A2 (en )
Inventor
Beom-Seok Cho
Hee-Jung Yang
Chang-Oh Jeong
Jae-Gab Lee
Myung-Mo Sung
Original Assignee
Samsung Electronics Co Ltd
Beom-Seok Cho
Hee-Jung Yang
Chang-Oh Jeong
Jae-Gab Lee
Myung-Mo Sung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Abstract

A method of manufacturing a thin film panel is provided, which includes: forming a gate line (20) on a substrate (10), the gate line including a gate electrode; forming a gate insulating layer on the gate line; forming a silicon layer formed on the gate insulating layer; forming a data line intersecting the gate line and a drain electrode separated from the data line on the silicon layer or on the gate insulating layer; and forming a self assembled monolayer (SAM) (30) on at least one of the gate line and the data line.
PCT/KR2004/001381 2003-06-10 2004-06-10 Wiring for semiconductor device, thin film transistor array panel including wiring, and manufacturing method thereof WO2004109750A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR10-2003-0037148 2003-06-10
KR20030037148A KR20040105975A (en) 2003-06-10 2003-06-10 Wiring for semiconductor device, method for manufacturing the wiring, thin film transistor array panel including the wiring, and method for manufacturing the panel

Publications (2)

Publication Number Publication Date
WO2004109750A2 true WO2004109750A2 (en) 2004-12-16
WO2004109750A3 true true WO2004109750A3 (en) 2006-01-26

Family

ID=33509642

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2004/001381 WO2004109750A3 (en) 2003-06-10 2004-06-10 Wiring for semiconductor device, thin film transistor array panel including wiring, and manufacturing method thereof

Country Status (2)

Country Link
KR (1) KR20040105975A (en)
WO (1) WO2004109750A3 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009535637A (en) * 2006-05-03 2009-10-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Biosensor device
KR20100091663A (en) 2009-02-11 2010-08-19 삼성전자주식회사 Surface modifying agent, laminated structure using the same, method of manufacturing the structure, and transistor including the same
US8415252B2 (en) * 2010-01-07 2013-04-09 International Business Machines Corporation Selective copper encapsulation layer deposition
KR20140107968A (en) 2013-02-28 2014-09-05 한국전자통신연구원 Method for transferring graphene

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395454B1 (en) * 1997-08-04 2002-05-28 Infineon Technologies Ag Integrated electrical circuit with passivation layer
US20020084252A1 (en) * 2000-12-28 2002-07-04 Buchwalter Stephen L. Self-assembled monolayer etch barrier for indium-tin-oxide useful in manufacturing thin film transistor-liquid crystal displays
US6433359B1 (en) * 2001-09-06 2002-08-13 3M Innovative Properties Company Surface modifying layers for organic thin film transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395454B1 (en) * 1997-08-04 2002-05-28 Infineon Technologies Ag Integrated electrical circuit with passivation layer
US20020084252A1 (en) * 2000-12-28 2002-07-04 Buchwalter Stephen L. Self-assembled monolayer etch barrier for indium-tin-oxide useful in manufacturing thin film transistor-liquid crystal displays
US6433359B1 (en) * 2001-09-06 2002-08-13 3M Innovative Properties Company Surface modifying layers for organic thin film transistors

Also Published As

Publication number Publication date Type
WO2004109750A2 (en) 2004-12-16 application
KR20040105975A (en) 2004-12-17 application

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