WO2004102407A3 - Ubs host controller with dma capability - Google Patents

Ubs host controller with dma capability Download PDF

Info

Publication number
WO2004102407A3
WO2004102407A3 PCT/IB2004/050643 IB2004050643W WO2004102407A3 WO 2004102407 A3 WO2004102407 A3 WO 2004102407A3 IB 2004050643 W IB2004050643 W IB 2004050643W WO 2004102407 A3 WO2004102407 A3 WO 2004102407A3
Authority
WO
WIPO (PCT)
Prior art keywords
host controller
controller
system memory
dma
associated system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2004/050643
Other languages
French (fr)
Other versions
WO2004102407A2 (en
Inventor
Chee E Lee
Constantin Socol
Jerome Tjia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to DE602004008064T priority Critical patent/DE602004008064T2/en
Priority to JP2006530805A priority patent/JP5146796B2/en
Priority to US10/556,453 priority patent/US7340554B2/en
Priority to EP04732372A priority patent/EP1627312B1/en
Publication of WO2004102407A2 publication Critical patent/WO2004102407A2/en
Publication of WO2004102407A3 publication Critical patent/WO2004102407A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.
PCT/IB2004/050643 2003-05-15 2004-05-12 Ubs host controller with dma capability Ceased WO2004102407A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE602004008064T DE602004008064T2 (en) 2003-05-15 2004-05-12 USB HOST CONTROLLER WITH DMA ABILITY
JP2006530805A JP5146796B2 (en) 2003-05-15 2004-05-12 Host controller
US10/556,453 US7340554B2 (en) 2003-05-15 2004-05-12 USB host controller with DMA capability
EP04732372A EP1627312B1 (en) 2003-05-15 2004-05-12 Usb host controller with dma capability

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SGPCT/SG03/00129 2003-05-15
SG0300129 2003-05-15

Publications (2)

Publication Number Publication Date
WO2004102407A2 WO2004102407A2 (en) 2004-11-25
WO2004102407A3 true WO2004102407A3 (en) 2005-01-06

Family

ID=33448782

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2004/050643 Ceased WO2004102407A2 (en) 2003-05-15 2004-05-12 Ubs host controller with dma capability

Country Status (6)

Country Link
EP (1) EP1627312B1 (en)
JP (1) JP5146796B2 (en)
CN (1) CN100414523C (en)
AT (1) ATE369588T1 (en)
DE (1) DE602004008064T2 (en)
WO (1) WO2004102407A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007111752A2 (en) 2005-12-22 2007-10-04 U.S. Government As Represented By The Secretary Of The U.S. Army Modular prosthetic foot
JP5456434B2 (en) 2009-10-22 2014-03-26 ルネサスエレクトロニクス株式会社 Pipe arbitration circuit, pipe arbitration method
CN112100107A (en) * 2019-06-17 2020-12-18 广州慧睿思通信息科技有限公司 USB data transmission method, device and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US6266715B1 (en) * 1998-06-01 2001-07-24 Advanced Micro Devices, Inc. Universal serial bus controller with a direct memory access mode
US20020178310A1 (en) * 2001-05-22 2002-11-28 Akihiro Nozaki USB transmission control circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02123447A (en) * 1988-10-12 1990-05-10 Advanced Micro Devicds Inc Input/output controller and data transfer therefor
JP2765267B2 (en) * 1990-05-22 1998-06-11 日本電気株式会社 Direct memory access transfer controller
TW276312B (en) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
JPH0773059A (en) * 1993-03-02 1995-03-17 Tandem Comput Inc Fault-tolerant computer system
US6185641B1 (en) * 1997-05-01 2001-02-06 Standard Microsystems Corp. Dynamically allocating space in RAM shared between multiple USB endpoints and USB host

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US6266715B1 (en) * 1998-06-01 2001-07-24 Advanced Micro Devices, Inc. Universal serial bus controller with a direct memory access mode
US20020178310A1 (en) * 2001-05-22 2002-11-28 Akihiro Nozaki USB transmission control circuit

Also Published As

Publication number Publication date
JP5146796B2 (en) 2013-02-20
DE602004008064T2 (en) 2008-04-24
CN100414523C (en) 2008-08-27
WO2004102407A2 (en) 2004-11-25
DE602004008064D1 (en) 2007-09-20
ATE369588T1 (en) 2007-08-15
CN1882929A (en) 2006-12-20
EP1627312A2 (en) 2006-02-22
EP1627312B1 (en) 2007-08-08
JP2007502476A (en) 2007-02-08

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