WO2004082180A3 - Method for optimizing high frequency performance of via structures - Google Patents

Method for optimizing high frequency performance of via structures Download PDF

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Publication number
WO2004082180A3
WO2004082180A3 PCT/US2003/006836 US0306836W WO2004082180A3 WO 2004082180 A3 WO2004082180 A3 WO 2004082180A3 US 0306836 W US0306836 W US 0306836W WO 2004082180 A3 WO2004082180 A3 WO 2004082180A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
method
sub
high frequency
circuit
backplane
Prior art date
Application number
PCT/US2003/006836
Other languages
French (fr)
Other versions
WO2004082180A2 (en )
Inventor
Franz Gisin
Mahamud Khandokar
William Panos
Original Assignee
Sanmina Sci Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0005Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, and noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, and noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/163Monitoring a manufacturing process

Abstract

A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
PCT/US2003/006836 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures WO2004082180A3 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2003/006836 WO2004082180A3 (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
PCT/US2003/006836 WO2004082180A3 (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures
KR20057016653A KR101041555B1 (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures
EP20030816274 EP1625680A4 (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures
JP2004569398T JP2006526883A (en) 2003-03-06 2003-03-06 Method for optimizing the high frequency performance of via structures
CN 03826090 CN1989503B (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures

Publications (2)

Publication Number Publication Date
WO2004082180A2 true WO2004082180A2 (en) 2004-09-23
WO2004082180A3 true true WO2004082180A3 (en) 2006-12-28

Family

ID=32986322

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/006836 WO2004082180A3 (en) 2003-03-06 2003-03-06 Method for optimizing high frequency performance of via structures

Country Status (5)

Country Link
EP (1) EP1625680A4 (en)
JP (1) JP2006526883A (en)
KR (1) KR101041555B1 (en)
CN (1) CN1989503B (en)
WO (1) WO2004082180A3 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1916915A (en) 2005-08-19 2007-02-21 鸿富锦精密工业(深圳)有限公司 Method for improving resistance of via hole
JP4834385B2 (en) * 2005-11-22 2011-12-14 株式会社日立製作所 PCB and electronic devices
CN101236078B (en) 2007-02-02 2011-01-05 鸿富锦精密工业(深圳)有限公司;鸿海精密工业股份有限公司 Capacitance to via hole guide wire length checking system and method
CN101373488B (en) 2007-08-21 2011-06-15 京元电子股份有限公司 Stack designing system and method for printed circuit board
JP4585587B2 (en) * 2008-08-20 2010-11-24 株式会社東芝 Method for producing a high frequency multi-layer substrate and the high frequency multi-layer substrate
JP5582248B2 (en) 2011-03-30 2014-09-03 日本電気株式会社 Transmission system and backplane system construction method
WO2012133781A1 (en) 2011-03-30 2012-10-04 日本電気株式会社 Transmission system and method for constructing backplane system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512377B1 (en) * 2001-06-29 2003-01-28 Nortel Networks Limited Method and apparatus for extraction of via parasitics
US20030151133A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman RF transition for an area array package

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0944549A (en) * 1995-07-31 1997-02-14 Mitsubishi Electric Corp Circuit designing method and layout designing method
JPH09274623A (en) * 1996-04-08 1997-10-21 Oki Electric Ind Co Ltd Transmission line simulation system and transmission line simulation method using the same
JPH1049568A (en) * 1996-05-31 1998-02-20 Sharp Corp Circuit board designing method and recording medium
JP4204150B2 (en) * 1998-10-16 2009-01-07 パナソニック株式会社 Multi-layer circuit board
US6538538B2 (en) * 1999-02-25 2003-03-25 Formfactor, Inc. High frequency printed circuit board via
JP2000252716A (en) * 1999-03-03 2000-09-14 Sony Corp Distributed constant filter, its manufacture and distributed constant filter printed circuit board
JP3285010B2 (en) * 1999-06-22 2002-05-27 日本電気株式会社 Stub circuit, adjustment method, and the oscillator of the stub circuit
JP3482958B2 (en) * 2000-02-16 2004-01-06 株式会社村田製作所 High-frequency circuit device and a communication device
JP2001308547A (en) * 2000-04-27 2001-11-02 Sharp Corp High-frequency multilayer circuit board
JP4184590B2 (en) * 2000-12-04 2008-11-19 松下電器産業株式会社 Implementation cost evaluation method and apparatus of the circuit board
JP4734723B2 (en) * 2001-01-31 2011-07-27 凸版印刷株式会社 Method for manufacturing a multilayer wiring board using a coaxial hole
US20020147575A1 (en) * 2001-02-12 2002-10-10 Bois Karl J. Method and system for modeling dielectric losses in a transmission line

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512377B1 (en) * 2001-06-29 2003-01-28 Nortel Networks Limited Method and apparatus for extraction of via parasitics
US20030151133A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman RF transition for an area array package

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LOW ET AL.: 'Via design optimization for high speed device packaging' ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE December 1998, pages 112 - 118, XP010328959 *
See also references of EP1625680A2 *

Also Published As

Publication number Publication date Type
EP1625680A2 (en) 2006-02-15 application
EP1625680A4 (en) 2009-04-08 application
JP2006526883A (en) 2006-11-24 application
KR101041555B1 (en) 2011-06-15 grant
WO2004082180A2 (en) 2004-09-23 application
CN1989503B (en) 2010-08-04 grant
KR20060006776A (en) 2006-01-19 application
CN1989503A (en) 2007-06-27 application

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