WO2004081978A2 - Radio frequency clamping circuit - Google Patents
Radio frequency clamping circuit Download PDFInfo
- Publication number
- WO2004081978A2 WO2004081978A2 PCT/US2004/003913 US2004003913W WO2004081978A2 WO 2004081978 A2 WO2004081978 A2 WO 2004081978A2 US 2004003913 W US2004003913 W US 2004003913W WO 2004081978 A2 WO2004081978 A2 WO 2004081978A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- diode
- node
- anode
- cathode
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/441—Protection of an amplifier being implemented by clamping means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
- H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
Definitions
- the present invention relates to clamping circuits. More specifically, the present invention relates to radio frequency clamping circuits.
- Clamping circuits are used to protect electronic components, circuits and systems against excessive and potentially harmful currents and voltages.
- clamping circuits have been used to protect analog- to-digital (A/D) converters from over- voltages.
- a preferred approach involves the use of diodes to shunt over- voltages to ground.
- the diode approaches known in the art have suffered from linearity problems. That is, these devices have often failed to accurately pass signals below a clamping threshold without degradation.
- the inventive clamping circuit includes an input/output node, adapted to be coupled to a protected circuit or component; a first diode having an anode comiected to the input/output node; a second diode having a cathode connected to the input/output node; a third diode connected between the cathode of the first diode and the anode of the second diode; a first arrangement for supplying a first potential at the cathode of the first diode to reverse-bias the first diode, while causing the third diode to go into conduction; a second arrangement for supplying a second potential at the anode of the second diode to reverse-bias the second diode, while causing the third diode to go into conduction; a first capacitor connected between the cathode of the first diode and ground; and a second capacitor connected between the anode of the second diode and
- the anode of the third diode is comiected to the cathode of the first diode
- the first arrangement includes a first resistor connected between a first power supply and the cathode of the first diode
- the second arrangement includes a second resistor connected between a second power supply and the anode of the second diode.
- the illustrative embodiment further includes a third resistor connected between the cathode of the first diode and ground and a fourth resistor connected between the anode of the second diode and ground.
- Fig. 1 is a schematic diagram of an illustrative embodiment of a clamping circuit implemented in accordance with the teachings of the present invention.
- Figure 2 shows an alternative embodiment in which the third diode D3 is implemented with two diodes connected in series with a connection to ground at the node there between.
- Fig. 1 is a schematic diagram of an illustrative embodiment of a clamping circuit implemented in accordance with the teachings of the present invention.
- the inventive clamping circuit 10 includes an input/output node 12, adapted to be coupled to a protected circuit or component (not shown).
- a first diode Dl is included with an anode connected to the input/output node 12.
- a second diode D2 is included with the cathode thereof connected to the input/output node 12.
- a third diode D3 is connected between the cathode of the first diode Dl at node 14 and the anode of the second diode D2 at node 16.
- the anode of the third diode D3 is comiected to node 14.
- a first source supplies a first potential at node 14 via a first resistor Rl and a second source supplies a second potential at node 16 via a second resistor R2.
- a first capacitor Cl is connected between node 14 and ground.
- a second capacitor C2 is connected between node 16 and ground.
- the illustrative embodiment further includes a third resistor R3 connected between node 14 and ground and a fourth resistor R4 comiected between node 16 and ground.
- the signal is shunted to the input/output node 12 of the clamp 10 of the present invention. If the peak voltage of the input signal is below the clamping threshold, the first and second diodes Dl and D2 are reverse biased by their respective supply voltages and the voltage drop across the third diode D3. This keeps Dl and D2 off and prevents the desired signals from being shunted.
- the first diode Dl conducts and places a more-positive voltage at the anode of the third diode.
- the second diode D2 conducts and places a more-negative voltage at the cathode of the third diode D3.
- this causes the third diode D3 to conduct more heavily to limit the change in voltage at the cathode of Dl and at the anode of D2.
- the third diode D3 works with the first and second capacitors Cl and C2 to allow for large over- voltage current to be shunted with a small biasing voltages current.
- the circuit 10 During normal drive levels (below clipping), the circuit 10 provides a high shunt impedance to the RF signal and presents only a small fraction of a dB loss in a typical 50 ohm system.
- a small biasing current (e.g., 3 ma) flows through the third diode D3 and develops reverse bias for both the first and the second diodes Dl and D2. Because of symmetry, half the voltage drop across D3 becomes the amount of reverse bias for Dl and D2.
- approximately 0.3V reverse bias is applied to Dl and D2. The reverse bias voltage value sets the clipping level for the limiter.
- This value can be altered by changing D3 (to a zener diode for example), or by adding another diode in series with D3 as shown in Fig 2 below.
- D3 to a zener diode for example
- D3 the dynamic impedance of D3 affects the amount that the output level will rise as the input signal level increases past the initial clamp level.
- Figure 2 shows an alternative embodiment in which the third diode D3 is implemented with two diodes connected in series with a connection to ground at the node there between.
- Dl and D2 are fast silicon diodes that have low leakage current, and low dynamic impedance when in conduction.
- the low leakage current provides the high third order intercept point (IP3) for small signal levels.
- IP3 third order intercept point
- the low dynamic on resistance reduces the increase in power as the input increases.
- the increase in positive voltage at Cl during the positive half cycle is nullified by the increase in negative voltage at C2 during the negative half cycle, since D3 moves heavily into conduction and effectively connects these points together.
- the third diode would be a zener diode to raise the clamping voltage to even higher levels, hi this case the third diode connection would be reversed so that conduction occurs due to zener breakdown instead of forward conduction.
- a capacitor is placed across the third diode, either as a third capacitor, or as a substitute for the first and second capacitors.
- the inventive clamp protects a device from damage while providing high third order intercept point (IP3) for levels below full scale.
- IP3 third order intercept point
- the RF output signal from the clamping circuit 10 is applied to the input of a transformer, which in turn differentially drives an analog to digital converter.
- the RF terminals are at DC ground.
- blocking capacitors can be used, with a high value resistor (typical IK ohm) placed between the input/output node and ground, and with the blocking capacitor between the input/output node and the DC voltage.
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Emergency Protection Circuit Devices (AREA)
- Amplifiers (AREA)
Abstract
A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cathode connected to the input/output node (12); a third diode (D3) connected between the cathode of the first diode (D1) at a first node (14) and the anode of the second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode of the first diode at first node (14); a second arrangement for supplying a second potential at the anode of the second diode at second node (16); a first capacitor (C1) connected between the cathode of the first diode at first node (14) and ground; and a second capacitor connected between the anode of the second diode at second node (16) and ground. In the illustrative embodiment, the anode of the third diode (D3) is connected to the first node (14), the first arrangement includes a first power supply and a first resistor (R1), and the second arrangement includes a second power supply and a second resistor (R2). The illustrative embodiment further includes a third resistor (R3) connected between the first node (14) and ground and a fourth resistor (R4) connected between the second node (16) and ground.
Description
RADIO FREQUENCY CLAMPING CIRCUIT
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to clamping circuits. More specifically, the present invention relates to radio frequency clamping circuits.
Description of the Related Art
Clamping circuits are used to protect electronic components, circuits and systems against excessive and potentially harmful currents and voltages. In radio frequency systems, for example, clamping circuits have been used to protect analog- to-digital (A/D) converters from over- voltages.
One conventional clamping approach involves the use of switches to isolate the protected circuit or circuit component from a deleterious source of excessively high energy. However, this approach requires a detector and therefore tends to be relatively expensive, h addition, it is difficult to achieve a sufficiently fast response time to provide adequate protection in many cases.
Accordingly, a preferred approach involves the use of diodes to shunt over- voltages to ground. However, the diode approaches known in the art have suffered
from linearity problems. That is, these devices have often failed to accurately pass signals below a clamping threshold without degradation.
Accordingly, a need remains in the art for an improved system or method for protecting circuits, components and systems from excessive voltages and currents with good linearity and minimal expense.
SUMMARY OF THE INVENTION
The need in the art is addressed by the clamping circuit of the present invention. The inventive clamping circuit includes an input/output node, adapted to be coupled to a protected circuit or component; a first diode having an anode comiected to the input/output node; a second diode having a cathode connected to the input/output node; a third diode connected between the cathode of the first diode and the anode of the second diode; a first arrangement for supplying a first potential at the cathode of the first diode to reverse-bias the first diode, while causing the third diode to go into conduction; a second arrangement for supplying a second potential at the anode of the second diode to reverse-bias the second diode, while causing the third diode to go into conduction; a first capacitor connected between the cathode of the first diode and ground; and a second capacitor connected between the anode of the second diode and ground.
In the illustrative embodiment, the anode of the third diode is comiected to the cathode of the first diode, the first arrangement includes a first resistor connected between a first power supply and the cathode of the first diode, and the second arrangement includes a second resistor connected between a second power supply and the anode of the second diode. The illustrative embodiment further includes a third resistor connected between the cathode of the first diode and ground and a fourth resistor connected between the anode of the second diode and ground.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic diagram of an illustrative embodiment of a clamping circuit implemented in accordance with the teachings of the present invention.
Figure 2 shows an alternative embodiment in which the third diode D3 is implemented with two diodes connected in series with a connection to ground at the node there between.
DESCRIPTION OF THE INVENTION
Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
Fig. 1 is a schematic diagram of an illustrative embodiment of a clamping circuit implemented in accordance with the teachings of the present invention. As shown in Fig. 1, the inventive clamping circuit 10 includes an input/output node 12, adapted to be coupled to a protected circuit or component (not shown). A first diode Dl is included with an anode connected to the input/output node 12. A second diode D2 is included with the cathode thereof connected to the input/output node 12. A third diode D3 is connected between the cathode of the first diode Dl at node 14 and the anode of the second diode D2 at node 16. In the illustrative embodiment, the anode of
the third diode D3 is comiected to node 14. A first source supplies a first potential at node 14 via a first resistor Rl and a second source supplies a second potential at node 16 via a second resistor R2. A first capacitor Cl is connected between node 14 and ground. A second capacitor C2 is connected between node 16 and ground. The illustrative embodiment further includes a third resistor R3 connected between node 14 and ground and a fourth resistor R4 comiected between node 16 and ground. Those of ordinary skill in the art will choose component values for the elements shown based on the requirements of a given application.
In operation, when an RF input signal is applied to the input terminal of a protected device (not shown), the signal is shunted to the input/output node 12 of the clamp 10 of the present invention. If the peak voltage of the input signal is below the clamping threshold, the first and second diodes Dl and D2 are reverse biased by their respective supply voltages and the voltage drop across the third diode D3. This keeps Dl and D2 off and prevents the desired signals from being shunted.
During an overdrive condition, when an RF signal with an over- voltage is present, on the positive cycle, the first diode Dl conducts and places a more-positive voltage at the anode of the third diode. On a negative cycle, the second diode D2 conducts and places a more-negative voltage at the cathode of the third diode D3. In both cases, this causes the third diode D3 to conduct more heavily to limit the change in voltage at the cathode of Dl and at the anode of D2. Those skilled in the art will appreciate that the third diode D3 works with the first and second capacitors Cl and C2 to allow for large over- voltage current to be shunted with a small biasing voltages current.
During normal drive levels (below clipping), the circuit 10 provides a high shunt impedance to the RF signal and presents only a small fraction of a dB loss in a typical 50 ohm system. A small biasing current (e.g., 3 ma) flows through the third diode D3 and develops reverse bias for both the first and the second diodes Dl and
D2. Because of symmetry, half the voltage drop across D3 becomes the amount of reverse bias for Dl and D2. Using a 1N4148 for D3, approximately 0.3V reverse bias is applied to Dl and D2. The reverse bias voltage value sets the clipping level for the limiter. This value can be altered by changing D3 (to a zener diode for example), or by adding another diode in series with D3 as shown in Fig 2 below. However, the dynamic impedance of D3 affects the amount that the output level will rise as the input signal level increases past the initial clamp level.
Figure 2 shows an alternative embodiment in which the third diode D3 is implemented with two diodes connected in series with a connection to ground at the node there between.
In the best mode, Dl and D2 are fast silicon diodes that have low leakage current, and low dynamic impedance when in conduction. The low leakage current provides the high third order intercept point (IP3) for small signal levels. The low dynamic on resistance reduces the increase in power as the input increases.
As mentioned above, when a large signal level is applied, Dl conducts on the positive half cycle, and D2 conducts on the negative half cycle to limit the output voltage swing. During a positive voltage swing, Dl conducts and the voltage at Cl begins to rise. The value of Cl should be chosen to reduce the amount that this voltage can rise during a single half cycle. If D3 were not present, then the rectified RF would slowly charge Cl mitil only a small amount of average current (equal to the bias current through Rl and R3) would flow through Dl. Thus, if D3 were not present, the only way to have optimal limiting would be to use high bias current.
With D3 in the circuit, the increase in positive voltage at Cl during the positive half cycle is nullified by the increase in negative voltage at C2 during the negative half cycle, since D3 moves heavily into conduction and effectively connects these points together.
Another alternative embodiment would be for the third diode to be a zener diode to raise the clamping voltage to even higher levels, hi this case the third diode connection would be reversed so that conduction occurs due to zener breakdown instead of forward conduction.
In yet another embodiment, a capacitor is placed across the third diode, either as a third capacitor, or as a substitute for the first and second capacitors. In the illustrative application, the inventive clamp protects a device from damage while providing high third order intercept point (IP3) for levels below full scale. In a typical application, the RF output signal from the clamping circuit 10 is applied to the input of a transformer, which in turn differentially drives an analog to digital converter. Thus the RF terminals are at DC ground. In applications where a DC voltage is present, blocking capacitors can be used, with a high value resistor (typical IK ohm) placed between the input/output node and ground, and with the blocking capacitor between the input/output node and the DC voltage.
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof.
It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.
Accordingly,
WHAT IS CLAIMED IS
Claims
1. A clamping circuit (10) for a circuit or component to be protected characterized by: an input/output node (12) adapted to be coupled to said protected circuit or component; a first diode (Dl) having an anode connected to said input/output node (12); a second diode (D2) having a cathode connected to said input/output node
(12); a third diode (D3) connected between the cathode of said first diode (Dl) at a first node (14) and the anode of said second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode said first diode at node (14); and a second arrangement for supplying a second potential at the anode of said second diode at node (16).
2. The invention of Claim 1 further including a first capacitor (Cl) connected between the cathode of said first diode at node (14) and ground.
3. The invention of Claim 2 further including a second capacitor (C2) connected between the anode of said second diode at node (16) and ground.
4. The invention of Claim 1 further including a capacitor comiected across said third diode.
5. The invention of Claim 1 wherein the anode of said third diode (D3) is connected to said first node (14) or the cathode of said third diode (D3) is connected to said first node (14) when a zener diode is utilized for D3
6. The invention of Claim 1 wherein said first arrangement includes a first power supply (+V) and a first resistor (Rl).
7. The invention of Claim 6 wherein said second arrangement includes a second power supply (-V) and a second resistor (R2).
8. The invention of Claim 1 further including a resistor (R3) connected between said first node (14) and ground.
9. The invention of Claim 1 further including a resistor connected between said second node (16) and ground.
10. The invention of Claim 1 wherein the third diode is a zener diode and the anode thereof is connected to the cathode of the said first diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006508711A JP4728222B2 (en) | 2003-03-11 | 2004-02-10 | Radio frequency clamping circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/385,800 US6777996B2 (en) | 2000-02-09 | 2003-03-11 | Radio frequency clamping circuit |
| US10/385,800 | 2003-03-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2004081978A2 true WO2004081978A2 (en) | 2004-09-23 |
| WO2004081978A3 WO2004081978A3 (en) | 2004-11-04 |
Family
ID=32987308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2004/003913 Ceased WO2004081978A2 (en) | 2003-03-11 | 2004-02-10 | Radio frequency clamping circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6777996B2 (en) |
| JP (1) | JP4728222B2 (en) |
| KR (1) | KR100635404B1 (en) |
| WO (1) | WO2004081978A2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777996B2 (en) * | 2000-02-09 | 2004-08-17 | Raytheon Company | Radio frequency clamping circuit |
| JP3759135B2 (en) * | 2003-09-12 | 2006-03-22 | ローム株式会社 | Semiconductor device and electronic device |
| US7254003B2 (en) * | 2005-03-24 | 2007-08-07 | Freescale Semiconductor, Inc. | Differential nulling avalanche (DNA) clamp circuit and method of use |
| DE102006026803A1 (en) * | 2006-06-07 | 2007-12-13 | Deutsche Thomson-Brandt Gmbh | Protective circuit for e.g. sensitive microphone preamplifier, has two zener diodes attached to input stage over other four zener diodes, capacitors arranged parallel to two diodes, and resistors arranged between four diodes and capacitors |
| US7911236B2 (en) * | 2006-11-22 | 2011-03-22 | Intel Mobile Communications GmbH | Detection circuit and detection method |
| US20090001270A1 (en) * | 2007-06-28 | 2009-01-01 | Aleph America | RF detector and temperature sensor |
| US8237456B2 (en) | 2009-03-02 | 2012-08-07 | Atmel Corporation | Capacitive sensing |
| US8837099B2 (en) * | 2009-08-17 | 2014-09-16 | Analog Devices, Inc. | Guarded electrical overstress protection circuit |
| DE102020104090A1 (en) * | 2020-02-17 | 2021-08-19 | Comet Ag | High-frequency amplifier arrangement for a high-frequency generator |
| CN111416614B (en) * | 2020-04-10 | 2023-10-27 | 成都仕芯半导体有限公司 | High-linearity radio frequency circuit and method for improving linearity of radio frequency circuit |
| CN111799608B (en) * | 2020-07-09 | 2025-02-28 | 东莞市贝恩电子科技有限公司 | Socket circuit and socket having the same |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51137353A (en) * | 1975-05-22 | 1976-11-27 | Graphtec Corp | Amplitude limiting circuit |
| JPS5621405A (en) * | 1979-07-31 | 1981-02-27 | Hitachi Ltd | Clamp circuit |
| US4571511A (en) * | 1983-06-27 | 1986-02-18 | Rca Corporation | Noise reduction system |
| JPS6077141U (en) * | 1983-10-31 | 1985-05-29 | 三洋電機株式会社 | FM radio receiver overload prevention circuit |
| US4736271A (en) * | 1987-06-23 | 1988-04-05 | Signetics Corporation | Protection device utilizing one or more subsurface diodes and associated method of manufacture |
| JP2919566B2 (en) * | 1990-06-29 | 1999-07-12 | 沖電気工業株式会社 | Semiconductor device |
| US5610790A (en) * | 1995-01-20 | 1997-03-11 | Xilinx, Inc. | Method and structure for providing ESD protection for silicon on insulator integrated circuits |
| US6130811A (en) * | 1997-01-07 | 2000-10-10 | Micron Technology, Inc. | Device and method for protecting an integrated circuit during an ESD event |
| JPH10214905A (en) * | 1997-01-29 | 1998-08-11 | New Japan Radio Co Ltd | Signal input circuit |
| US6777996B2 (en) * | 2000-02-09 | 2004-08-17 | Raytheon Company | Radio frequency clamping circuit |
| US6456472B1 (en) * | 2000-04-07 | 2002-09-24 | Philsar Semiconductor Inc. | ESD protection in mixed signal ICs |
| TW449842B (en) * | 2000-07-13 | 2001-08-11 | United Microelectronics Corp | SOI electrostatic discharge protection circuit |
| JP3386042B2 (en) * | 2000-08-02 | 2003-03-10 | 日本電気株式会社 | Semiconductor device |
| WO2002023692A2 (en) * | 2000-09-12 | 2002-03-21 | Fusion Lighting, Inc. | Voltage clamping circuit |
| JP2002368563A (en) * | 2001-06-11 | 2002-12-20 | Victor Co Of Japan Ltd | Amplitude limiting circuit |
-
2003
- 2003-03-11 US US10/385,800 patent/US6777996B2/en not_active Expired - Lifetime
-
2004
- 2004-02-10 WO PCT/US2004/003913 patent/WO2004081978A2/en not_active Ceased
- 2004-02-10 JP JP2006508711A patent/JP4728222B2/en not_active Expired - Lifetime
- 2004-02-10 KR KR1020057016816A patent/KR100635404B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6777996B2 (en) | 2004-08-17 |
| KR100635404B1 (en) | 2006-10-19 |
| JP2006520166A (en) | 2006-08-31 |
| WO2004081978A3 (en) | 2004-11-04 |
| KR20050109544A (en) | 2005-11-21 |
| US20030189453A1 (en) | 2003-10-09 |
| JP4728222B2 (en) | 2011-07-20 |
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