WO2004068665A2 - Wafer scale packaging technique for sealed optical elements and sealed packages produced thereby - Google Patents

Wafer scale packaging technique for sealed optical elements and sealed packages produced thereby Download PDF

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Publication number
WO2004068665A2
WO2004068665A2 PCT/US2004/001790 US2004001790W WO2004068665A2 WO 2004068665 A2 WO2004068665 A2 WO 2004068665A2 US 2004001790 W US2004001790 W US 2004001790W WO 2004068665 A2 WO2004068665 A2 WO 2004068665A2
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WO
WIPO (PCT)
Prior art keywords
wafer
front surface
devices
semiconductor die
connections
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PCT/US2004/001790
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French (fr)
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WO2004068665A3 (en
Inventor
Ronald Foster
Ajay P. Malshe
Chad O'neal
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The Board Of Trustees Of The University Of Arkansas Research And Sponsored Programs
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Application filed by The Board Of Trustees Of The University Of Arkansas Research And Sponsored Programs filed Critical The Board Of Trustees Of The University Of Arkansas Research And Sponsored Programs
Publication of WO2004068665A2 publication Critical patent/WO2004068665A2/en
Publication of WO2004068665A3 publication Critical patent/WO2004068665A3/en

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Abstract

A wafer scale method for packaging semiconductor die or other devices in a sealed environment uses a plurality of wafers that are aligned and attached to each other to form an assembly. A front surface of a first wafer (10) has via regions (14) and laterally-extending conductors (15) electrically connected to metal at the via regions. Semiconductor die (25) or other devices are attached to thr front surface and electrically connected (28) to the conductors. A second wafer (20) has holes (22) which form recesses in which the semiconductor die or other devices and the vias are located. A third wafer (30) forms a cap for the recesses to provide a sealed environment (35) therein.

Description

Inventors: Ron Foster, Ajay P. Malshe, Chad O'Neal
Title: Wafer Scale Packaging Technique for Sealed
Optical Elements and Sealed Packages Produced Thereby-
Cross-Reference to Related Application
This application claims the benefit of provisional application 60/442,064 filed January 24, 2003, incorporated herein by reference.
Background of the Invention
[0001] This invention is concerned with packaging techniques for optical elements or devices which require electrical and/or optical input signals, actuation or conversion of input signals between optical and electrical domains, and electrical and/or optical outputs. Packaging techniques are flexible, allowing for a variety of devices to be placed in a miniature sealed cavity, and to have external electrical and optical connections. Electrical connections are made in a manner to minimize interference with optical signals. Both single element devices and arrays, of devices may be packaged by the methods disclosed.
[0002] Optical components have been packaged for many years in a relatively standardized T046 Lens can. Many state-of-the-art optical devices, such as Vertical Cavity Surface Emitting Laser (VCSEL) or photodetectors are currently packaged into hermetically sealed T046 packages, which is generally a metal container with a window or lens attached to the top of the package such that light may enter or be emitted from the package. Additionally, these T046 packages may be custom designed in order to facilitate coupling of the light into an optical fiber. These packages are both large and expensive . What is needed is an updated approach that will result in significant reduction in both size and cost of the components, enabling higher packing density of electronics .
[0003] Additionally, optical systems are rapidly trending towards higher frequencies. The T046 package is limited..in,ability_to provide for high, frequencies-, due to a number of parasitic capacitances and inductances related to the package itself. Newer packages are required which minimize parasitic capacitance and inductance, and enable further increase in system operating frequencies.
[0004] For arrays of optical devices, packaging methods have typically been developed as hybrid approaches, with subassemblies created and placed into higher level packages. Such hybrid approaches are expensive, often exposing the semiconductor die or other components to a variety of environmental variables both during assembly and over life.
[0005] The trend towards application of optical systems in a wide variety of communications platforms results in increasing emphasis on the reliability of such systems . Higher level integration results in increased demand on individual component reliability in order to maintain overall system reliability at an acceptable level. However, simultaneously the emerging standards for system reliability are being elevated. This makes it doubly important that component reliability be increased in each new design. The challenge can be met by applying standardized packaging methods that minimize manual handling .of semiconductor die or other devices, and protecting such devices at every stage of fabrication. The completed component must be hermetically sealed in order to prevent contaminants from affecting the included devices. Further, the ambient within the hermetically sealed cavity must be controlled. For instance, the sealed cavity could be evacuated, or backfilled with a relatively inert gas such as, for example, nitrogen, argon, helium.
[0006] Many approaches have been developed to make through-the-wafer via connections. This allows for electrical connections to be made to a bottom surface of a device. This is especially convenient when it is desirable to have light enter or be emitted from the topside of the assembly.
[0007] When applied properly, backside connection may support minimization of parasitic capacitance and inductance. Interconnection lengths are shortened by proper application. Also, substrate losses may be minimized by choice of materials and design.
[0008] In the past it has been expensive to make through-the-wafer via connections. Generally, procedures must be provided for creating holes through the wafer. If these holes have vertical sidewalls, then the space consumed by the holes- is minimized. However, a second required step is to fill or plug the holes with a conductive material. Typically, conductive material will not deposit uniformly on vertical sidewalls, but rather will tend to thin over the sidewalls. Therefore, it is very difficult to form the plugs. Alternatively, the holes can be sloped, but in this case the area consumed by the holes will increase. For a given slope, the area consumed increases depending on the substrate thickness, as can be demonstrated from simple geometry relationships. Additional complexity may be involved in the necessity to electrically insulate the vias from the substrate and from each other. In one approach, an insulating material such as silicon dioxide or silicon nitride may be deposited following hole formation but prior to depositing a conductive material. A thinner substrate provides a clear advantage in required area for a via , but thinner substrates tend to be fragile, and make fabrication more difficult and costly.
[0009] There is a need for an invention that addresses these problems .
Summary of the Invention:
[0010] Disclosed is a wafer scale technique for packaging optical elements in a miniature sealed cavity -component-.which encloses and protects semiconductor die or other devices. Means are provided for interconnection of devices to one another and to through-the-wafer via connections. The packaging methods are flexible, allowing for a variety of devices to be placed in a miniature sealed cavity, and to have external electrical and optical connections to the completed component . Electrical connections are made in a manner to minimize interference with optical signals. Both single element devices and arrays of devices may be packaged by the methods disclosed. Both passive and active optical elements may be included in the packages . [0011] Also disclosed are means to incorporate passive optical elements such as lenses or mirrors fabricated by low-cost wafer-level methods. Such optical elements are fundamentally integrated into the component design. Also disclosed are means to incorporate active optical elements such as light emitters, moveable mirrors or devices which change index of refraction in response to an applied voltage .
[0012] Technical advantages realized by the invention include reduced cost by application of wafer-level assembly. Also, sensitive devices are protected both during and after assembly. This will result in improved reliability and associated longevity of- t-he completed component.-
[0013] Additional advantages are provided by the invention, including the ability to test for functionality while still in wafer form. This will result in reduced cost.
[0014] Additional advantages are provided by the invention, including the ability to incorporate optical elements into the design and manufacture of the components. [0015] Further advantages will be apparent to those skilled in the art.
Brief Description of Drawings :
[0016] The features of the present invention will be more clearly understood from consideration of the following description in connection with the accompanying drawings in which:
[0017] Figure 1 is a cross-section view of component fabrication steps up to a point where the wafer assembly is complete.
[0018] Figure 2 is a cross-section view of component fabrication steps of thinning the wafer to reveal vias, applying terminal metal, testing and dicing.
[0019] Figure 3 is a plan view of a single component.
Detailed Description of Preferred Embodiments:
[0020] While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. When referring to drawings, like reference numbers are used for like parts throughout the views. Directional references such as, front, back, side, top, bottom, used in the discussion of the drawings are intended for convenient reference to the drawings themselves as laid out on the page, and are not intended to limit the orientation of the invention unless specifically indicated. The drawings are not to scale and some features have been exaggerated in order to show particular aspects of the invention.
[0021] To better understand the invention, reference is made to Figures 1 through 3. In this example of a preferred embodiment of the invention, a silicon substrate or wafer 10 is used. It should be understood by those skilled in the art that other materials may be used such as, for example, a ceramic or glass wafer. In Figures 1 and 2, the package is shown constructed on a silicon wafer 10.
[0022] Preferably, in order to enable anisotropic etching of the silicon, a substrate 10 with <100> faceplane orientation is used. In order to minimize electrical conduction between adjacent through-the-wafer vias, the resistivity of the wafer is selected to be very high, such as greater than 1000 ohm-cm. While the dopant may be either N-type or P-type, the high resistivity will insure that a Schottky contact will be formed between any metal that contacts the silicon and the silicon itself. Additionally, electrical current flow between circuit nodes will be minimized by the high resistance of the silicon itself.
[0023] Typically, a layer of silicon dioxide 12 is grown on the wafer 10, patterned and etched in order to form masking material on the front surface. This initial pattern must be well aligned to the crystal plane, which is referenced to the flat on the substrate. In the preferred embodiment, an oxide thickness of about 0.5 microns is used, although thickness in the range of approximately 0.05 - 5.0 microns may be used.
[0024] The wafer 10 is submitted to wet anisotropic etch in order to create regions 14 for through-the-wafer via connections 52 (see Fig. 3) . In a preferred embodiment, these regions are etched 1 - 2 mils deep, whereas the total wafer thickness may be 10 - 30 mils.
[0025] In the preferred embodiment, silicon dioxide 12 is removed in street areas 16 by pattern and etch method. This prepares the surface 17 in these areas for anodic bonding.
[0026] Metal 15 is deposited over the wafer 10 to coat the slope of the anisotropic etch region as well as the top surface. In a preferred embodiment, this metal 15 comprises an adhesion layer such as chrome or titanium- tungsten alloy, followed by gold. Optionally the gold metal may be thickened by photoresist masking and plating techniques. As is well known in the art, excess metal in the field regions may be etched away by application of photolithography and wet etch techniques, leaving regions of metal electrically isolated from one another. A gold thickness of 5 - 50 microns is preferred in order to minimize electrical resistance to lateral flow of current. Provision is made for gold extended pads or interconnects 18 (see Fig. 3) by appropriate design of photomask.
[0027] A second wafer 20 is prepared by machining holes 22 through the wafer 20. As is well known in the art, a variety of methods may be used for machining the wafer 20, including but not limited to ultrasonic slurry, drilling, sandblasting or wet etching. In a preferred embodiment, this second wafer 20 is pyrex with a relatively high concentration of sodium oxide (i.e. greater than about 2.5% by weight) . Both top and bottom surfaces of the second wafer 20 are maintained to be smooth and polished.
[0028] The first and second wafers 10 and 20 are aligned together such that the through-the-wafer via connections 52 remain exposed by the holes 22 in the second wafer 20. The wafers are bonded together. In a preferred embodiment, anodic bonding also known as thermoelectric bonding is used. At this point in the assembly, no sensitive components are included. Therefore, a wide range of temperature or applied voltage may be used in order to bond the wafers together. For example, anodic bonding may typically be completed at 350 C, with 1200 volts applied between the two wafers .
[0029] Semiconductor die or- other devices 25 are placed onto the surface 26 of the first wafer 10 in the recesses formed by holes 22 in the second wafer 20. These die devices 25 are permanently attached with any of the techniques of thermocompression bonding, eutectic bonding or epoxy bonding. Next, the die devices 25 are interconnected to the substrate by wirebonding, wedgebonding, tape or ribbon bonding 28 from the top of the devices 25 to the gold interconnect layers 18 prepared on the first wafer 10.
[0030] A third wafer 30 designated as a capping wafer is prepared. Typically, this third wafer will be constructed of glass, but any optically clear but dense material may be used. Advantage is made of the third wafer 30 in order to include various optical elements 32, for example lenses and partially reflecting mirrors. Fabrication of mirrors or lenses 32 in the glass can be accomplished using relatively low-cost wafer-level processing. The optical elements 32 are particularly attractive when either a light emitter or light detector is included in the package, and when the light being emitted or detected is essentially monochromatic. In such a case, diffraction methods may be applied in such a way as to obtain the same effects as reflective or refractive optical elements. It may be important to align the capping wafer 30 over included devices 25 such that a lens region 32 of the wafer 30 is positioned correctly to have_ the desired effect .
[0031] There are at least three general ways in which the capping wafer 30 can be made to include an active optical element 32. First, by creating properly-designed nanometer-scale features on the top surface of the glass, the glass can be made to diffract light, and act as a lens or other optical element 32. In principle, any optical element 32 can be made by this technique, with the condition that the light source is essentially monochromatic. In the case of the Vertical Cavity Surface Emitting Laser (VCSEL) , the light emitted generally fits this criterion. Embossing techniques or pattern and etch techniques may be applied to create the diffractive optical element (see, e.g., U.S. 5,597,613; U.S. 5,812,581; U.S. 5,799,030).
[0032] Second, the wafer 30 may be molded or otherwise formed to include raised or indented portions, functioning as refractive optical elements 32. Other optical materials may be added to the surfaces of the wafer 30 in order to enhance the refractive optical responses.
[0033] Third, by applying carefully-designed nanometer-scale coatings to the bottom of the wafer 30
(facing the sealed cavity) , the degree of reflection can be controlled. For example, in a typical VCSEL package, a photodiode is included in order to detect reflected light, and the signal produced by the photodiode is applied to an Automatic Gain Control (AGO circuit. In this fashion, the light output from the VCSEL can be stabilized over the life of the product. In this example, it is an important feature of the design to control the direction and amount of reflected light from an optical element included in the design. [0034] Following wirebonding or other internal interconnection 28, the third wafer 30 is placed over the wafer assembly and sealed together to form a composite assembly 38. Provision is made for control of ambient in the sealed environment 35 by performing the assembly of second and third wafers in a controlled enclosure. Such controlled enclosure or sealed environment 35 may be evacuated, or may contain inert gases such as nitrogen, argon, helium or other.
[0035] The third wafer 30 may be sealed to the second wafer 20 by a variety of techniques, including but not limited to ultraviolet-curable adhesive, fritted glass, epoxy, anodic bonding, or eutectic alloy. It is an important -feature of- this invention to minimize temperature excursions during this bonding such as to maintain the integrity of any semiconductor die or other components that may be enclosed. This limitation on temperature will dictate the choice of bonding material and method.
[0036] The disclosed method results in having electrical connections 41 to the bottom side of the assembly 38. Following the assembly of the three wafers with included devices, the through-the-wafer via connections 52 are revealed by planar etching of the bottom wafer 10. For convenience, the bulk of the wafer 10 thickness may be removed by mechanical methods such as lapping and polishing. However, in a preferred embodiment an isotropic dry silicon etch is used to actually expose the metal 15 in the vias 52. In either case, the final thickness of the bottom wafer 10 is preferably reduced to 1 to 2 mils.
[0037] It may be desirable to apply terminal metal 45 to the through-the-wafer via connections 52. For example, bump metals are well known in the art, and are convenient for connections to printed circuit boards.
[0038] Following completed assembly, electrical and optical testing can be completed, and the wafer assembly 38 diced in order to separate the individual units .
[0039] In an alternative method, the first wafer 10 may be of the type known as wire-in-glass. This provides for through-the-wafer via connections 52 by casting wires in a glass ingot, and then wafering the ingot. In this case, the second wafer 20 may be constructed of silicon. Bonding of first and second wafers 10 and 20 by anodic bonding is enabled by choice of one substrate being glass while the second substrate is silicon. Minimization of substrate losses is assured by maintaining the bottom substrate as relatively thick and of a dielectric material. Optionally, the second wafer 20 may be formed of any arbitrary material, limited only by the condition that an acceptable method may be found to bond the arbitrary material to glass .
[0040] In yet another alternative method, the first wafer 10 may be constructed of a ceramic material, with for example "plugs" formed of tungsten and copper alloys in order to match thermal expansion coefficients as is well known in the art. In this case, the second wafer 20 may be constructed of either silicon or glass or other material, and bonding between the two wafers will be accomplished by above listed methods excepting anodic bonding.
[0041] In a still further embodiment, the second and -t-hi-rd wafers may be fabricated -as a-single composite wafer. In this case, semiconductor die or other devices are placed onto the surface of the first wafer, attached and interconnected by wirebond, wedgebonding, tape or ribbon bonding 28 from the top of the die 25 to the gold interconnect layers 18 prepared on the first wafer 10. Following such interconnection 28, the composite capping wafer may be aligned and bonded over the first wafer 10. While there may be advantages in this approach, one clear disadvantage is the potential to damage devices 25 or interconnect betweens devices during assembly. While preferred embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that changes can be made without departing from the principles and spirit of the invention, the scope of which is defined in the accompanying claims.

Claims

WHAT IS CLAIMED IS:
1. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer having a front surface and a back surface, and containing holes passing through the thickness of the second wafer; and a third wafer having a front surface and a back surface, the back surface having means for partially reflecting an optical signal light, the front surface being constructed to diffract the optical signal light in a controlled fashion; said method comprising: aligning and attaching the first and second wafers to one another to provide an assembly thereof with recesses formed by the front surface of the first wafer and by the holes in the second wafer; attaching semiconductor die or other devices to the front surface of the first wafer in the recesses; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first wafer; aligning and attaching the third wafer to the assembly of first and second wafers to provide a composite assembly in which the semiconductor die or other devices are in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the composite assembly into individual package units .
2. A method according to claim 1, wherein the environment is a hermetically sealed environment.
3. A method according to claim 1, wherein said third wafer is constructed of inorganic, optically clear material.
4. A method according to claim 1, wherein said second wafer is constructed of glass material and said third wafer is constructed of inorganic, optically clear material.
5. A method according to claim 1, wherein said second wafer is constructed of ceramic material and said third wafer is constructed of inorganic, optically clear material.
6. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer having a front surface and a back surface, and containing holes passing through the thickness of the second wafer; and a third wafer having a front surface and a back surface, the front surface being shaped to refract an optical signal .light, in a controlled fashion; said method comprising: aligning and attaching the first and second wafers to one another to provide an assembly thereof with recesses formed by the front surface of the first wafer and by the holes in the second wafer; attaching semiconductor die or other devices to the front surface of the first wafer in the recesses; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first wafer; aligning and attaching the third wafer to the assembly of first and second wafers to provide a composite assembly in which the semiconductor die or other devices are in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the composite assembly into individual package units.
7. A method according to claim 6, wherein the environment is a hermetically sealed environment.
8. A method according to claim 6, wherein both the front surface and back surface of the third wafer are shaped to refract an optical signal light in a controlled, fashion.
9. A method according to claim 6, wherein said third wafer is constructed of inorganic, optically clear material.
10. A method according to claim 6, wherein said second wafer is constructed of glass material and said third wafer is constructed of inorganic, optically clear material.
11. A method according to claim 6, wherein said second wafer is constructed of ceramic material and said third wafer is constructed of inorganic, optically clear material.
12. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer having a front surface and a back surface, and containing holes passing through the thickness of the-, second wafer; and a third wafer having a front surface and a back surface, the front surface containing means for partially reflecting an optical signal light in a controlled fashion; said method comprising: aligning and attaching the first and second wafers to one another to provide an assembly thereof with recesses formed by the front surface of the first wafer and by the holes in the second wafer; attaching semiconductor die or other devices to the front surface of the first wafer in the recesses; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first substrate wafer; aligning and attaching the third wafer to the assembly of first and second wafers to provide a composite assembly in which the semiconductor die or other devices are in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the composite assembly into individual package units .
13. A method according to claim 12 , wherein the environment is a hermetically sealed environment.
14. A method according to claim 12 , wherein said third wafer is constructed of inorganic, optically clear material.
15. A method according to claim 12 , wherein said second wafer is constructed of glass material and said third wafer is constructed of inorganic, optically clear material .
16. A method according to claim 12, wherein said second wafer is constructed of ceramic material and said third wafer is constructed of inorganic, optically clear material .
17. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer having a front surface and a back surface, and containing holes passing through the thickness of the second wafer; and a third wafer having a front surface and a back surface, the front surface containing means for transmitting optical signal light with a minimum of reflection, refraction or diffraction; said method comprising: aligning and attaching the first and second wafers to one another to provide an assembly thereof with the recesses formed by the front surface of the front wafer and by the holes in the second wafer; attaching semiconductor die or other devices to the front surface of the first wafer in recesses; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first wafer; aligning and attaching said third wafer to the assembly of first and second wafers to provide a composite assembly in which the semiconductor die or other devices are in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the composite assembly into individual package units .
18. A method according to claim 17, wherein the environment is a hermetically sealed environment .
19. A method according to claim 17, wherein said third wafer is constructed of inorganic, optically clear material.
20. A method according to claim 17, wherein said second wafer is constructed of glass material and said third wafer is constructed of inorganic, optically clear material.
21. A method according to claim 17, wherein said second wafer is constructed of ceramic material and said third wafer is constructed of inorganic, optically clear material .
22. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer having a front surface and a back surface, and containing holes passing through the thickness of the second wafer; and a third wafer having a front surface and a back surface, the ϋxont surface containing means for diffracting optical signal light in a controlled fashion; said method comprising: aligning and attaching the first and second wafer to one another to provide an assembly thereof with recesses formed by the front surface of the first wafer and by the holes in the second wafer; attaching semiconductor die or other devices to the front surface of the first wafer in the recesses; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first wafer; aligning and attaching said third wafer to the assembly of first and second wafers to provide a composite assembly in which the semiconductor die or other devices are in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the composite assembly into individual package units .
23. A method according to claim 22, wherein the environment is a hermetically sealed environment .
24. A according to claim 22, wherein said third wafer is constructed of inorganic, optically clear material.
25. A method according to claim 22, wherein said second wafer is constructed of glass material and said third wafer is constructed of inorganic, optically clear material.
26. A method according to claim 22, wherein said second wafer is constructed of ceramic material and said third wafer is constructed of inorganic, optically clear material .
27. A wafer scale method for packaging semiconductor die or other devices in a sealed environment, using: a first wafer having a front surface and a back surface, the front surface having regions prepared for through-the-wafer connections and having conductors in electrical contact with said connections and extending laterally over the front surface; a second wafer containing cavities formed therein and partially penetrating the thickness of the wafer; the method comprising: attaching semiconductor die or other devices to the front surface of the first wafer at positions corresponding to the cavities in the second wafer; forming electrical connections between the semiconductor die or other devices and the conductors on the front surface of the first wafer; aligning and attaching the second wafer to the first wafer to provide an assembly thereof in which the semiconductor die or other devices are in the cavities in a sealed environment; thinning the first wafer in order to expose the through-the-wafer connections; and separating the assembly into individual package units .
28. A method according to claim 27, wherein said first wafer is silicon, and said second wafer is inorganic, optically clear material.
29. A method according to claim 27, wherein said first wafer is silicon, said second wafer is glass, and said second wafer includes means for reflecting light in a controlled fashion.
30. A method according to claim 27, wherein; said first wafer is silicon, said second wafer is glass, and said second wafer includes means for reflecting and refracting light in a controlled fashion.
31. A method according to claim 27, wherein said first wafer is ceramic with plug material forming through-the-wafer connections; and said second wafer is glass.
32. A method according to claim 27, wherein said first wafer is glass with wire-in-glass connections; said second wafer is silicon; and semiconductor die or other devices are attached and electrically connected to the conductors on the front surface of the first wafer by a flip-chip method.
33. A method according to claim 27, wherein said first wafer is glass with wire-in-glass connections; said second wafer is ceramic; and semiconductor die or other devices are attached and electrically connected to the conductors on the front surface of the first wafer by a flip-chip method.
34. A method according to any preceding claim in which terminal metal is applied to the exposed through-the-wafer connections.
35. A method according to any preceding claim in which testing of optical and electrical functions is performed prior to separation into individual package units .
36. An optical component produced by the packaging method of any preceding claim.
37. An assembly of optical components produced by the method of any preceding claim up to but not including separationinto individual package units.
38. A wafer scale packaging method substantially as shown and/or described herein.
39. An optical component or a pre-separation assembly of optical components substantially as shown and/or described herein.
40. A wafer scale package in which semiconductor die or other devices are contained in a sealed environment, comprising: a plurality of wafers bonded together to provide a composite assembly in which semiconductor die or other devices are mounted on a surface of one of the wafers in recesses that are closed by a light permeable wafer cap, electrical conductors being provided on the surface to connect the semiconductor die or other devices to through-a- wafer conductors, wherein the wafer cap is structured to modify an optical signal light incident thereon.
41. A wafer scale package according to Claim 40, wherein an external surface of the wafer cap is structured to provide controlled diffraction, refraction, and/or reflection of light.
PCT/US2004/001790 2003-01-24 2004-01-23 Wafer scale packaging technique for sealed optical elements and sealed packages produced thereby WO2004068665A2 (en)

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