WO2004059539A3 - Procede pour prendre en compte une variation de procede dans la conception de circuits integres - Google Patents

Procede pour prendre en compte une variation de procede dans la conception de circuits integres Download PDF

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Publication number
WO2004059539A3
WO2004059539A3 PCT/US2003/040758 US0340758W WO2004059539A3 WO 2004059539 A3 WO2004059539 A3 WO 2004059539A3 US 0340758 W US0340758 W US 0340758W WO 2004059539 A3 WO2004059539 A3 WO 2004059539A3
Authority
WO
WIPO (PCT)
Prior art keywords
accounting
design
integrated circuits
process variation
variation
Prior art date
Application number
PCT/US2003/040758
Other languages
English (en)
Other versions
WO2004059539A2 (fr
Inventor
Louis K Scheffer
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Priority to AU2003297420A priority Critical patent/AU2003297420A1/en
Publication of WO2004059539A2 publication Critical patent/WO2004059539A2/fr
Publication of WO2004059539A3 publication Critical patent/WO2004059539A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé pour simuler un circuit électronique. Ce procédé consiste à déterminer des paramètres de processus et une variation de processus pour chaque paramètre de processus, et à déterminer une valeur pour chaque composant appartenant à une pluralité de composants du circuit, cette valeur étant déterminée en tant que fonction des variations de processus.
PCT/US2003/040758 2002-12-23 2003-12-19 Procede pour prendre en compte une variation de procede dans la conception de circuits integres WO2004059539A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003297420A AU2003297420A1 (en) 2002-12-23 2003-12-19 A method for accounting for process variation in the design of integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/327,738 2002-12-23
US10/327,738 US7474999B2 (en) 2002-12-23 2002-12-23 Method for accounting for process variation in the design of integrated circuits

Publications (2)

Publication Number Publication Date
WO2004059539A2 WO2004059539A2 (fr) 2004-07-15
WO2004059539A3 true WO2004059539A3 (fr) 2005-04-07

Family

ID=32594325

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/040758 WO2004059539A2 (fr) 2002-12-23 2003-12-19 Procede pour prendre en compte une variation de procede dans la conception de circuits integres

Country Status (4)

Country Link
US (2) US7474999B2 (fr)
AU (1) AU2003297420A1 (fr)
TW (1) TWI334093B (fr)
WO (1) WO2004059539A2 (fr)

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Publication number Priority date Publication date Assignee Title
EP1709694B1 (fr) * 2004-01-26 2017-03-15 OSRAM Opto Semiconductors GmbH Del a film mince ayant une structure d'elargissement de courant
US20050177356A1 (en) * 2004-02-10 2005-08-11 Matsushita Electric Industrial Co., Ltd. Circuit simulation method and circuit simulation apparatus
EP1583009A1 (fr) * 2004-03-30 2005-10-05 Interuniversitair Micro-Elektronica Centrum Méthode et appareil pour la conception et fabrication de circuits électroniques sujets à des variations de processus
GB0407070D0 (en) * 2004-03-30 2004-05-05 Imec Inter Uni Micro Electr A method for designing digital circuits, especially suited for deep submicron technologies
JP2005352787A (ja) * 2004-06-10 2005-12-22 Matsushita Electric Ind Co Ltd タイミング解析方法およびタイミング解析装置
US7487475B1 (en) * 2004-10-15 2009-02-03 Cadence Design Systems, Inc. Systems, methods, and apparatus to perform statistical static timing analysis
US7299445B2 (en) * 2004-10-29 2007-11-20 Synopsys, Inc. Nonlinear receiver model for gate-level delay calculation
DE102005025416A1 (de) * 2005-06-02 2006-12-14 Osram Opto Semiconductors Gmbh Lumineszenzdiodenchip mit einer Kontaktstruktur
US7684969B2 (en) * 2005-09-02 2010-03-23 International Business Machines Corporation Forming statistical model of independently variable parameters for timing analysis
US7546562B1 (en) 2005-11-12 2009-06-09 Cadence Design Systems, Inc. Physical integrated circuit design with uncertain design conditions
US7979832B2 (en) * 2006-12-06 2011-07-12 Qualcomm Incorporated Process variation tolerant memory design
US20100076741A1 (en) * 2007-02-19 2010-03-25 Kiyoshi Takeuchi System, method and program for determining worst condition of circuit operation
EP2006784A1 (fr) * 2007-06-22 2008-12-24 Interuniversitair Microelektronica Centrum vzw Procédés de caractérisation de circuits électroniques soumis à des effets de variabilité de procédé
JP4530049B2 (ja) * 2008-01-10 2010-08-25 ソニー株式会社 半導体装置の設計プログラムおよび半導体装置の設計システム
US8245165B1 (en) 2008-04-11 2012-08-14 Cadence Design Systems, Inc. Methods and apparatus for waveform based variational static timing analysis
US8255851B1 (en) * 2008-06-24 2012-08-28 Marvell Israel (M.I.S.L) Ltd. Method and system for timing design
US7992114B1 (en) * 2008-08-19 2011-08-02 Magma Design Automation, Inc. Timing analysis using statistical on-chip variation
JP2010160787A (ja) * 2008-12-11 2010-07-22 Jedat Inc パラメータ情報作成システム、歩留まり算出システム、プログラム及び記録媒体
US8448110B2 (en) * 2009-11-24 2013-05-21 International Business Machines Corporation Method to reduce delay variation by sensitivity cancellation
US8266565B2 (en) 2010-01-29 2012-09-11 International Business Machines Corporation Ordering of statistical correlated quantities
US8176461B1 (en) * 2010-05-10 2012-05-08 Xilinx, Inc. Design-specific performance specification based on a yield for programmable integrated circuits
US20120046929A1 (en) 2010-08-20 2012-02-23 International Business Machines Corporation Statistical Design with Importance Sampling Reuse
US9858368B2 (en) 2011-07-13 2018-01-02 International Business Machines Corporation Integrating manufacturing feedback into integrated circuit structure design
JP5861774B2 (ja) * 2012-04-04 2016-02-16 株式会社村田製作所 コンデンサの等価回路モデルの導出方法
US8464199B1 (en) * 2012-05-16 2013-06-11 International Business Machines Corporation Circuit design using design variable function slope sensitivity
US9171112B2 (en) 2012-12-07 2015-10-27 Synopsys, Inc. Semiconductor hold time fixing
US9262726B2 (en) * 2013-01-17 2016-02-16 Applied Materials, Inc. Using radial basis function networks and hyper-cubes for excursion classification in semi-conductor processing equipment
US9734269B2 (en) * 2015-06-10 2017-08-15 Arm Limited Liberty file generation
US10380286B2 (en) 2017-02-20 2019-08-13 International Business Machines Corporation Multi-sided variations for creating integrated circuits
US11003737B2 (en) * 2017-04-12 2021-05-11 Samsung Electronics Co., Ltd. Generic high-dimensional importance sampling methodology
US10691853B2 (en) 2018-10-24 2020-06-23 International Business Machines Corporation Superposition of canonical timing value representations in statistical static timing analysis
TWI835197B (zh) * 2021-11-18 2024-03-11 國立成功大學 製造程序之最佳良率路徑之搜尋方法及其系統

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625785B2 (en) * 2000-04-19 2003-09-23 Georgia Tech Research Corporation Method for diagnosing process parameter variations from measurements in analog circuits
US7006939B2 (en) * 2000-04-19 2006-02-28 Georgia Tech Research Corporation Method and apparatus for low cost signature testing for analog and RF circuits
US20030229875A1 (en) * 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SCHEFFER LOU: "Explicit Computation of Performance as a Function of Process Variation", ACM/IEEE INTERNATIONAL WORKSHOP ON TIMING ISSUES IN THE SPECIFICATION AND SYNTHESIS OF DIGITAL SYSTEMS 2002, 2 December 2002 (2002-12-02) - 3 December 2002 (2002-12-03), MONTEREY, CALIFORNIA, pages 1 - 8, XP002314583 *

Also Published As

Publication number Publication date
TW200419398A (en) 2004-10-01
US20090199145A1 (en) 2009-08-06
US7474999B2 (en) 2009-01-06
WO2004059539A2 (fr) 2004-07-15
AU2003297420A1 (en) 2004-07-22
US20040122642A1 (en) 2004-06-24
TWI334093B (en) 2010-12-01

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